On 9/29/20 4:48 PM, Jakub Kicinski wrote:
> On Wed, 30 Sep 2020 04:30:39 +0800 Joakim Zhang wrote:
>> @@ -1292,6 +1307,35 @@ static void flexcan_set_bittiming(struct net_device
>> *dev)
>> return flexcan_set_bittiming_ctrl(dev);
>> }
>>
>> +static void flexcan_init_ram(struct net_d
On Wed, 30 Sep 2020 04:30:39 +0800 Joakim Zhang wrote:
> @@ -1292,6 +1307,35 @@ static void flexcan_set_bittiming(struct net_device
> *dev)
> return flexcan_set_bittiming_ctrl(dev);
> }
>
> +static void flexcan_init_ram(struct net_device *dev)
> +{
> + struct flexcan_priv *pri
On 9/29/20 2:50 PM, Joakim Zhang wrote:
>
>> -Original Message-
>> From: Marc Kleine-Budde
>> Sent: 2020年9月29日 20:46
>> To: Joakim Zhang ; linux-...@vger.kernel.org
>> Cc: netdev@vger.kernel.org; dl-linux-imx
>> Subject: Re: [PATCH V4 1/3] can: fle
> -Original Message-
> From: Marc Kleine-Budde
> Sent: 2020年9月29日 20:46
> To: Joakim Zhang ; linux-...@vger.kernel.org
> Cc: netdev@vger.kernel.org; dl-linux-imx
> Subject: Re: [PATCH V4 1/3] can: flexcan: initialize all flexcan memory for
> ECC
> function
On 9/29/20 2:38 PM, Joakim Zhang wrote:
>>> return flexcan_set_bittiming_ctrl(dev); }
>>>
>>> +static void flexcan_init_ram(struct net_device *dev) {
>>> + struct flexcan_priv *priv = netdev_priv(dev);
>>> + struct flexcan_regs __iomem *regs = priv->regs;
>>> + u32 reg_ctrl2;
>>>
On 9/29/20 2:34 PM, Marc Kleine-Budde wrote:
> On 9/29/20 10:30 PM, Joakim Zhang wrote:
>> One issue was reported at a baremetal environment, which is used for
>> FPGA verification. "The first transfer will fail for extended ID
>> format(for both 2.0B and FD format), following frames can be transmi
> -Original Message-
> From: Marc Kleine-Budde
> Sent: 2020年9月29日 20:34
> To: Joakim Zhang ; linux-...@vger.kernel.org
> Cc: netdev@vger.kernel.org; dl-linux-imx
> Subject: Re: [PATCH V4 1/3] can: flexcan: initialize all flexcan memory for
> ECC
> function
On 9/29/20 10:30 PM, Joakim Zhang wrote:
> One issue was reported at a baremetal environment, which is used for
> FPGA verification. "The first transfer will fail for extended ID
> format(for both 2.0B and FD format), following frames can be transmitted
> and received successfully for extended form
One issue was reported at a baremetal environment, which is used for
FPGA verification. "The first transfer will fail for extended ID
format(for both 2.0B and FD format), following frames can be transmitted
and received successfully for extended format, and standard format don't
have this issue. Th
