RE: [PATCH V4 1/3] can: flexcan: initialize all flexcan memory for ECC function

[Joakim Zhang]

> -----Original Message-----
> From: Marc Kleine-Budde <m...@pengutronix.de>
> Sent: 2020年9月29日 20:46
> To: Joakim Zhang <qiangqing.zh...@nxp.com>; linux-...@vger.kernel.org
> Cc: netdev@vger.kernel.org; dl-linux-imx <linux-...@nxp.com>
> Subject: Re: [PATCH V4 1/3] can: flexcan: initialize all flexcan memory for 
> ECC
> function
> 
> On 9/29/20 2:38 PM, Joakim Zhang wrote:
> >>>           return flexcan_set_bittiming_ctrl(dev);  }
> >>>
> >>> +static void flexcan_init_ram(struct net_device *dev) {
> >>> + struct flexcan_priv *priv = netdev_priv(dev);
> >>> + struct flexcan_regs __iomem *regs = priv->regs;
> >>> + u32 reg_ctrl2;
> >>> +
> >>> + /* 11.8.3.13 Detection and correction of memory errors:
> >>> +  * CTRL2[WRMFRZ] grants write access to all memory positions that
> >>> +  * require initialization, ranging from 0x080 to 0xADF and
> >>> +  * from 0xF28 to 0xFFF when the CAN FD feature is enabled.
> >>> +  * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK
> registers
> >> need to
> >>> +  * be initialized as well. MCR[RFEN] must not be set during memory
> >>> +  * initialization.
> >>> +  */
> >>> + reg_ctrl2 = priv->read(&regs->ctrl2);
> >>> + reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ;
> >>> + priv->write(reg_ctrl2, &regs->ctrl2);
> >>> +
> >>> + memset_io(&regs->mb[0][0], 0,
> >>> +           (u8 *)&regs->rx_smb1[3] - &regs->mb[0][0] + 0x4);
> >>
> >> why the cast?
> >
> > Due to mb is defined as a u8. And the count of memset_io is bytes.
> 
> right. this is why you don't need the 2nd cast.

Yes, do you need me send a patch to improve it with offsetof()?

Best Regards,
Joakim Zhang
> Marc
> 
> 
> --
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