On 4/15/2021 2:59 PM, Rob Herring wrote:
> On Wed, Apr 14, 2021 at 05:43:49PM +0200, Andrew Lunn wrote:
>> On Wed, Apr 14, 2021 at 05:26:55PM +0200, Michael Walle wrote:
>>> It is already possible to read the MAC address via a NVMEM provider. But
>>> there are boards, esp. with many ports, which
On 4/15/2021 6:07 AM, Oleksij Rempel wrote:
> Port some parts of the stmmac selftest and reuse it as basic generic selftest
> library. This patch was tested with following combinations:
> - iMX6DL FEC -> AT8035
> - iMX6DL FEC -> SJA1105Q switch -> KSZ8081
> - iMX6DL FEC -> SJA1105Q switch -> KSZ
On 4/15/2021 6:07 AM, Oleksij Rempel wrote:
> PHY loopback is needed for the ethernet controller self test support.
> This PHY was tested with the generic net sefltest in combination with
> FEC ethernet controller and SJA1105 switch.
>
> Signed-off-by: Oleksij Rempel
> ---
> drivers/net/phy/m
Signed-off-by: Tobias Waldekranz
Reviewed-by: Florian Fainelli
--
Florian
protocol to be
> changed on devices with undocumented support for EDSA. But, in those
> cases, make sure to log the fact that an undocumented feature has been
> enabled.
>
> Signed-off-by: Tobias Waldekranz
Reviewed-by: Florian Fainelli
--
Florian
; dynamically changing the tag protocol.
>
> Signed-off-by: Tobias Waldekranz
Reviewed-by: Florian Fainelli
--
Florian
On 4/14/2021 8:29 AM, Thomas Bogendoerfer wrote:
> If there is no mac address passed via platform data try to get it via
> device tree and fall back to a random mac address, if all fail.
>
> Signed-off-by: Thomas Bogendoerfer
> ---
> drivers/net/ethernet/korina.c | 29
On 4/13/2021 12:25 PM, Martin Blumenstingl wrote:
> On Tue, Apr 13, 2021 at 1:45 AM Andrew Lunn wrote:
> [...]
and a few people have forked it and modified it for other DSA
switches. At some point we might want to try to merge the forks back
together so we have one tool to dump a
ned-off-by: Florian Fainelli
Signed-off-by: David S. Miller
Signed-off-by: Florian Fainelli
---
drivers/net/phy/bcm-phy-lib.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/bcm-phy-lib.c b/drivers/net/phy/bcm-phy-lib.c
index d5e0833d69b9..66e4ef8ed345 10
ned-off-by: Florian Fainelli
Signed-off-by: David S. Miller
Signed-off-by: Florian Fainelli
---
drivers/net/phy/bcm-phy-lib.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/bcm-phy-lib.c b/drivers/net/phy/bcm-phy-lib.c
index e10e7b54ec4b..7e5892597533 10
On 4/11/2021 4:53 PM, Vladimir Oltean wrote:
> On Sun, Apr 11, 2021 at 09:50:17PM +0300, Vladimir Oltean wrote:
>> On Sun, Apr 11, 2021 at 08:01:35PM +0200, Marek Behun wrote:
>>> On Sat, 10 Apr 2021 15:34:46 +0200
>>> Ansuel Smith wrote:
>>>
Hi,
this is a respin of the Marek series i
On 4/11/2021 11:39 AM, Andrew Lunn wrote:
> On Sun, Apr 11, 2021 at 08:01:35PM +0200, Marek Behun wrote:
>> On Sat, 10 Apr 2021 15:34:46 +0200
>> Ansuel Smith wrote:
>>
>>> Hi,
>>> this is a respin of the Marek series in hope that this time we can
>>> finally make some progress with dsa support
On 4/5/2021 10:16 PM, Ansuel Smith wrote:
> On Wed, Apr 07, 2021 at 02:41:02AM +0200, Andrew Lunn wrote:
>> On Tue, Apr 06, 2021 at 06:50:40AM +0200, Ansuel Smith wrote:
>>> qca8k 83xx switch have 2 cpu ports. Rework the driver to support
>>> multiple cpu port. All ports can access both cpu port
x200")
> Cc: sta...@vger.kernel.org
> Suggested-by: Hauke Mehrtens
> Acked-by: Hauke Mehrtens
> Signed-off-by: Martin Blumenstingl
Reviewed-by: Florian Fainelli
--
Florian
e link settings on the
> GSWIP ports means that we now use the settings from device-tree also for
> ports with fixed-links.
>
> Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
> Fixes: 3e6fdeb28f4c33 ("net: dsa: lantiq_gswip: Let GSWIP automatically set
> the xMII clock")
> Cc: sta...@vger.kernel.org
> Acked-by: Hauke Mehrtens
> Reviewed-by: Andrew Lunn
> Signed-off-by: Martin Blumenstingl
Reviewed-by: Florian Fainelli
--
Florian
On 4/6/2021 5:32 PM, Andrew Lunn wrote:
>> case PHY_INTERFACE_MODE_RGMII:
>> case PHY_INTERFACE_MODE_RGMII_ID:
>> case PHY_INTERFACE_MODE_RGMII_RXID:
>> case PHY_INTERFACE_MODE_RGMII_TXID:
>> miicfg |= GSWIP_MII_CFG_MODE_RGMII;
>> +
>> +if (phylink_au
On 4/6/2021 5:23 PM, Jakub Kicinski wrote:
> Add missing kdoc for phy tunable callbacks.
>
> Signed-off-by: Jakub Kicinski
Reviewed-by: Florian Fainelli
--
Florian
On 4/6/2021 3:09 PM, Michael Walle wrote:
> of_get_mac_address() already supports fetching the MAC address by an
> nvmem provider. But until now, it was just working for platform devices.
> Esp. it was not working for DSA ports and PCI devices. It gets more
> common that PCI devices have a devic
On 4/6/2021 11:43 AM, Heiner Kallweit wrote:
> On 06.04.2021 20:32, Florian Fainelli wrote:
>>
>>
>> On 4/6/2021 4:42 AM, Heiner Kallweit wrote:
>>>
>>> Waiting for ANEG_COMPLETE to be set wouldn't be a good option. Aneg may
>>> never
>
On 4/6/2021 4:42 AM, Heiner Kallweit wrote:
>
> Waiting for ANEG_COMPLETE to be set wouldn't be a good option. Aneg may never
> complete for different reasons, e.g. no physical link. And even if we use a
> timeout this may add unwanted delays.
>
>> Do you have any other insights that can help
On 4/5/2021 7:58 AM, Heiner Kallweit wrote:
> On 05.04.2021 15:53, Christian Melki wrote:
>> On 4/5/21 2:09 PM, Heiner Kallweit wrote:
>>> On 05.04.2021 10:43, Christian Melki wrote:
On 4/5/21 12:48 AM, Heiner Kallweit wrote:
> On 04.04.2021 16:09, Heiner Kallweit wrote:
>> On 04.04
On 4/3/2021 16:21, Vladimir Oltean wrote:
On Sat, Apr 03, 2021 at 05:05:34PM +0300, Vladimir Oltean wrote:
On Sat, Apr 03, 2021 at 01:48:40PM +0200, Oleksij Rempel wrote:
Some switches (for example ar9331) do not provide enough information
about forwarded packets. If the switch decision was
t and per bridge join operation
so I would drop the rate limiting here. With that fixed:
Reviewed-by: Florian Fainelli
--
Florian
On 4/3/2021 04:48, Oleksij Rempel wrote:
This switch provides global ageing time configuration, so let DSA use
it.
Signed-off-by: Oleksij Rempel
Reviewed-by: Florian Fainelli
--
Florian
On 4/3/2021 04:48, Oleksij Rempel wrote:
In case of this switch we work with 32bit registers on top of 16bit
bus. Some registers (for example access to forwarding database) have
trigger bit on the first 16bit half of request and the result +
configuration of request in the second half. Without
On 4/1/21 12:47 AM, Oleksij Rempel wrote:
> On Wed, Mar 31, 2021 at 02:27:19PM +0200, Andrew Lunn wrote:
>> On Tue, Mar 30, 2021 at 03:54:07PM +0200, Oleksij Rempel wrote:
>>> Port some parts of the stmmac selftest to the FEC. This patch was tested
>>> on iMX6DL.
>>> With this tests it is possible
: Florian Fainelli
---
drivers/net/phy/broadcom.c | 76 +-
1 file changed, 66 insertions(+), 10 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 82fe5f43f0e9..7bf3011b8e77 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net
We should not be advertising EEE for modes that we do not support,
correct that oversight by looking at the PHY device supported linkmodes.
Fixes: 99cec8a4dda2 ("net: phy: broadcom: Allow enabling or disabling of EEE")
Signed-off-by: Florian Fainelli
---
drivers/net/phy/bcm-phy-
On 3/29/21 9:50 AM, Andrew Lunn wrote:
> On Mon, Mar 29, 2021 at 06:30:16PM +0300, Maxim Kochetkov wrote:
>> If PHY is not available on DSA port (described at devicetree but absent or
>> failed to detect) then kernel prints warning after 3700 secs:
>>
>> [ 3707.948771] [ cut here ]-
On 3/25/2021 2:19 AM, Qinglang Miao wrote:
> This patch adds missing MODULE_DEVICE_TABLE definition which generates
> correct modalias for automatic loading of this driver when it is built
> as an external module.
>
> Reported-by: Hulk Robot
> Signed-off-by: Qinglang Miao
dsa: Add Lantiq / Intel DSA driver for vrx200")
> Signed-off-by: Martin Blumenstingl
Reviewed-by: Florian Fainelli
> ---
> It would be great to have this fix backported to Linux 5.4 and 5.10 to
> get rid of one more blocker which prevents OpenWrt from switching to
> this new
On 3/24/2021 8:29 PM, 'Zheng Yongjun wrote:
> From: Zheng Yongjun
>
> Remove including that don't need it.
>
> Reported-by: Hulk Robot
> Signed-off-by: Zheng Yongjun
Acked-by: Florian Fainelli
--
Florian
On 3/24/2021 6:18 PM, Vladimir Oltean wrote:
> On Wed, Mar 24, 2021 at 04:07:47PM -0700, Florian Fainelli wrote:
>>> What are the benefits of mapping packets to TX queues of the DSA master
>>> from the DSA layer?
>>
>> For systemport and bcm_sf2 this was expl
On 3/24/2021 4:45 PM, Marek Behún wrote:
> On Wed, 24 Mar 2021 16:16:41 -0700
> Florian Fainelli wrote:
>
>> On 3/24/2021 4:00 PM, Marek Behún wrote:
>>> On Wed, 24 Mar 2021 14:19:28 -0700
>>> Florian Fainelli wrote:
>>>
>>>>>
On 3/24/2021 4:00 PM, Marek Behún wrote:
> On Wed, 24 Mar 2021 14:19:28 -0700
> Florian Fainelli wrote:
>
>>> Another problem is that if lower modes are supported, we should
>>> maybe use them in order to save power.
>>
>> That is an interesting
On 3/24/2021 3:21 PM, Vladimir Oltean wrote:
> Hi Florian,
>
> On Wed, Mar 24, 2021 at 02:09:02PM -0700, Florian Fainelli wrote:
>>
>>
>> On 3/24/2021 1:13 PM, Vladimir Oltean wrote:
>>> Hi Martin,
>>>
>>> On Wed, Mar 24, 2021 at 0
On 3/24/2021 3:50 PM, Hauke Mehrtens wrote:
> On 3/24/21 10:09 PM, Florian Fainelli wrote:
>>
>>
>> On 3/24/2021 1:13 PM, Vladimir Oltean wrote:
>>> Hi Martin,
>>>
>>> On Wed, Mar 24, 2021 at 09:04:16PM +0100, Martin Blumenstingl wrote:
>&g
On 3/24/2021 3:35 AM, Marek Behún wrote:
> Hello,
>
> the Marvell Alaska PHYs (88X3310, 88E2110) can, depending on their
> configuration, change the PHY mode to the MAC, depending on the
> copper/fiber speed.
>
> The 88X3310, for example, can be configured (via MACTYPE register)
> so that it c
On 3/24/2021 1:13 PM, Vladimir Oltean wrote:
> Hi Martin,
>
> On Wed, Mar 24, 2021 at 09:04:16PM +0100, Martin Blumenstingl wrote:
>> Hello,
>>
>> the PMAC (Ethernet MAC) IP built into the Lantiq xRX200 SoCs has
>> support for multiple (TX) queues.
>> This MAC is connected to the SoC's built-in
On 3/23/2021 7:49 AM, Tobias Waldekranz wrote:
> On Tue, Mar 23, 2021 at 13:41, Andrew Lunn wrote:
>> On Tue, Mar 23, 2021 at 11:23:26AM +0100, Tobias Waldekranz wrote:
>>> All devices are capable of using regular DSA tags. Support for
>>> Ethertyped DSA tags sort into three categories:
>>>
>>>
On 3/23/2021 7:48 AM, Tobias Waldekranz wrote:
> On Tue, Mar 23, 2021 at 13:35, Vladimir Oltean wrote:
>> On Tue, Mar 23, 2021 at 11:23:26AM +0100, Tobias Waldekranz wrote:
>>> All devices are capable of using regular DSA tags. Support for
>>> Ethertyped DSA tags sort into three categories:
>>>
On 3/23/2021 5:03 AM, Vladimir Oltean wrote:
> On Mon, Mar 22, 2021 at 07:40:27PM -0700, Florian Fainelli wrote:
>> On 3/20/2021 3:59 PM, Vladimir Oltean wrote:
>>> Because the 'rx-vlan-filter' feature is now dynamically toggled, and our
>>> .ndo_vlan_rx
On 3/20/2021 3:59 PM, Vladimir Oltean wrote:
> From: Vladimir Oltean
>
> The blamed patch has removed the driver's ability to return -EOPNOTSUPP
> in the .port_vlan_add method when called from .ndo_vlan_rx_add_vid
> (unmassaged by DSA, -EOPNOTSUPP is a hard error for vlan_vid_add).
> But we ha
itch configuration happens later.
>
> Fixes: 357f203bb3b5 ("net: dsa: keep a copy of the tagging protocol in the
> DSA switch tree")
>
> Signed-off-by: George McCollister
Reviewed-by: Florian Fainelli
--
Florian
On 3/22/2021 11:51 AM, Kurt Kanzenbach wrote:
> Report the driver name, ASIC ID and the switch name via devlink. This is a
> useful information for user space tooling.
>
> Signed-off-by: Kurt Kanzenbach
Reviewed-by: Florian Fainelli
--
Florian
NPUT_SKB_CB(skb)->offload_fwd_mark = p->offload_fwd_mark;
> }
>
> Signed-off-by: Vladimir Oltean
> Reviewed-by: Tobias Waldekranz
Reviewed-by: Florian Fainelli
--
Florian
ation time, so:
> (a) drivers had to hardcode the initial value for the address ageing time,
> because they didn't get any notification
> (b) that hardcoded value can be out of sync, if the user changes the
> ageing time before enslaving the port to the bridge
>
&g
On 3/20/2021 2:53 AM, Vladimir Oltean wrote:
> On Fri, Mar 19, 2021 at 03:20:38PM -0700, Florian Fainelli wrote:
>>
>>
>> On 3/18/2021 4:18 PM, Vladimir Oltean wrote:
>>> From: Vladimir Oltean
>>>
>>> I have udhcpcd in my system and this is confi
think we're offloading the bridge master of the LAG, when in
> fact we're not even offloading the LAG. In turn, this will make us set
> skb->offload_fwd_mark = true, which is incorrect and the bridge doesn't
> like it.
>
> Signed-off-by: Vladimir Oltean
Reviewed-by: Florian Fainelli
--
Florian
Hi Christian,
On 3/21/2021 4:29 PM, Cristian Ciocaltea wrote:
> Add new driver for the Ethernet MAC used on the Actions Semi Owl
> family of SoCs.
>
> Currently this has been tested only on the Actions Semi S500 SoC
> variant.
>
> Signed-off-by: Cristian Ciocaltea
[snip]
Do you know the story
side effect that there's no more empty menu on
> configurations without DSA.
>
> 4. Kbuild will now descend into 'drivers/net/dsa' only when
>CONFIG_NET_DSA is y or m.
>
> This is safe since no objects inside this folder can be built without
> DSA core, as well as when CONFIG_NET_DSA=m, no objects can be
> built-in.
>
> Signed-off-by: Alexander Lobakin
Reviewed-by: Florian Fainelli
--
Florian
On 3/19/2021 3:54 PM, Marek Behún wrote:
> On Fri, 19 Mar 2021 15:14:52 -0700
> Florian Fainelli wrote:
>
>> On 3/19/2021 12:47 PM, Marek Behún wrote:
>>> On Fri, 19 Mar 2021 20:58:20 +0200
>>> Vladimir Oltean wrote:
>>>
>>>> On Fr
On 3/18/2021 4:18 PM, Vladimir Oltean wrote:
> From: Vladimir Oltean
>
> Currently this simple setup:
>
> ip link add br0 type bridge vlan_filtering 1
> ip link add bond0 type bond
> ip link set bond0 master br0
> ip link set swp0 master bond0
>
> will not work because the bridge has created
On 3/18/2021 4:18 PM, Vladimir Oltean wrote:
> From: Vladimir Oltean
>
> I have udhcpcd in my system and this is configured to bring interfaces
> up as soon as they are created.
>
> I create a bridge as follows:
>
> ip link add br0 type bridge
>
> As soon as I create the bridge and udhcpcd
On 3/19/2021 12:47 PM, Marek Behún wrote:
> On Fri, 19 Mar 2021 20:58:20 +0200
> Vladimir Oltean wrote:
>
>> On Fri, Mar 19, 2021 at 03:31:49PM +0100, Marek Behún wrote:
>>> We know that the `lane == MV88E6393X_PORT0_LANE`, so we can pass `lane`
>>> to mv88e6390_serdes_read() instead of MV88E6
On 3/18/2021 4:18 PM, Vladimir Oltean wrote:
> From: Vladimir Oltean
>
> The SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME attribute is only emitted from:
>
> sysfs/ioctl/netlink
> -> br_set_ageing_time
>-> __set_ageing_time
>
> therefore not at bridge port creation time, so:
> (a) drivers had to
GE_MROUTER port
> attribute is only emitted from br_mc_router_state_change.
>
> Signed-off-by: Vladimir Oltean
Reviewed-by: Florian Fainelli
--
Florian
emitted by the
> bridge for this port.
>
> Signed-off-by: Vladimir Oltean
Reviewed-by: Florian Fainelli
--
Florian
But this new bridge port will not see any STP state
> change notification and will remain FORWARDING, which is how the
> standalone code leaves it in.
>
> Add a function to the bridge which retrieves the current STP state, such
> that drivers can synchronize to it when they may h
On 3/18/2021 4:18 PM, Vladimir Oltean wrote:
> From: Vladimir Oltean
>
> DSA currently assumes that the bridge port starts off with this
> constellation of bridge port flags:
>
> - learning on
> - unicast flooding on
> - multicast flooding on
> - broadcast flooding on
>
> just by virtue of c
;
> Signed-off-by: Vladimir Oltean
Reviewed-by: Florian Fainelli
--
Florian
dge port is handled in the next
> patches.
>
> Signed-off-by: Vladimir Oltean
Reviewed-by: Florian Fainelli
--
Florian
's what it's for).
>
> Suggested-by: Florian Fainelli
> Signed-off-by: Alex Elder
Reviewed-by: Florian Fainelli
--
Florian
On 3/18/2021 1:01 AM, Rafał Miłecki wrote:
> From: Rafał Miłecki
>
> BCM4908 has only 1 RGMII reg for controlling port 7.
>
> Fixes: 73b7a6047971 ("net: dsa: bcm_sf2: support BCM4908's integrated switch")
> Signed-off-by: Rafał Miłecki
Acked-by: Florian Fainelli
--
Florian
idation could result in getting register offset from out
> of array. Random memory -> random offset -> random reads/writes. It
> affected e.g. BCM4908 for REG_RGMII_CNTRL_P(7).
>
> Fixes: a78e86ed586d ("net: dsa: bcm_sf2: Prepare for different register
> layouts"
On 3/18/2021 11:14 AM, Greg KH wrote:
> On Thu, Mar 18, 2021 at 09:02:22AM -0700, Florian Fainelli wrote:
>>
>>
>> On 3/18/2021 6:25 AM, Heiner Kallweit wrote:
>>> On 18.03.2021 10:09, Wong Vee Khee wrote:
>>>> When using Clause-22 to probe for PHY dev
On 3/18/2021 12:30 AM, Rafał Miłecki wrote:
> On 17.03.2021 22:20, Florian Fainelli wrote:
>> On 3/17/2021 7:37 AM, Rafał Miłecki wrote:
>>> From: Rafał Miłecki
>>>
>>> Simple macro like REG_RGMII_CNTRL_P() is insufficient as:
>>> 1. It doesn'
amp;&
>> +!br_port_flag_is_set(brport, BR_BCAST_FLOOD))
>
> I think I would have liked to see a dsa_port_to_bridge_port helper that
> actually returns NULL when dp->bridge_dev is NULL.
>
> This would make your piece of code look as follows:
>
> brport = dsa_port_to_bridge_port(dp);
> if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)
> continue;
Agreed, with that fixed:
Reviewed-by: Florian Fainelli
--
Florian
least as far back as 6083.
>
> Signed-off-by: Tobias Waldekranz
Reviewed-by: Florian Fainelli
--
Florian
On 3/18/2021 7:15 AM, Tobias Waldekranz wrote:
> Use the conventional declaration style of a MAC address in the
> kernel (u8 addr[ETH_ALEN]) for the broadcast address, then set it
> using the existing helper.
>
> Signed-off-by: Tobias Waldekranz
Reviewed-by: Florian Fainelli
--
Florian
On 3/18/2021 7:15 AM, Tobias Waldekranz wrote:
> The hardware has a somewhat quirky protocol for reading out the VTU
> entry for a particular VID. But there is no reason why we cannot
> create a better API for ourselves in the driver.
>
> Signed-off-by: Tobias Waldekranz
Revie
On 3/18/2021 7:15 AM, Tobias Waldekranz wrote:
> Move the intricacies of correctly iterating over the VTU to a common
> implementation.
>
> Signed-off-by: Tobias Waldekranz
> Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
--
Florian
are does not support move operations on
> LAGs so there is no obvious way to transform the request to target the
> LAG instead.
>
> Instead we document this known limitation and at least avoid wasting
> any time on it.
>
> Signed-off-by: Tobias Waldekranz
Reviewed-by: Florian Fainelli
--
Florian
per that hides some of this complexity from the
> drivers. Then, redefine dsa_port_offloads_bridge_port using the helper
> to avoid double accounting of the set of possible offloaded uppers.
>
> Signed-off-by: Tobias Waldekranz
Reviewed-by: Florian Fainelli
--
Florian
On 3/18/2021 6:51 AM, Alex Elder wrote:
> Use upper_32_bits() to extract the high-order 32 bits of a DMA
> address. This avoids doing a 32-position shift on a DMA address
> if it happens not to be 64 bits wide.
>
> Suggested-by: Florian Fainelli
> Signed-off-by: Alex
On 3/18/2021 6:25 AM, Heiner Kallweit wrote:
> On 18.03.2021 10:09, Wong Vee Khee wrote:
>> When using Clause-22 to probe for PHY devices such as the Marvell
>> 88E2110, PHY ID with value 0 is read from the MII PHYID registers
>> which caused the PHY framework failed to attach the Marvell PHY
>>
On 3/17/2021 3:49 PM, Alex Elder wrote:
> On 3/17/21 5:47 PM, Florian Fainelli wrote:
>>> +/* Encapsulate extracting high-order 32 bits of DMA address */
>>> +static u32 dma_addr_high32(dma_addr_t addr)
>>> +{
>>> +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
&g
On 3/17/2021 3:29 PM, Alex Elder wrote:
> Create a new helper function to encapsulate extracting the
> high-order 32 bits of a DMA address. It returns 0 for builds
> in which a DMA address is not 64 bits.
>
> This avoids doing a 32-position shift on a DMA address if it
> happens not to be 64 b
er a bridging/unbridging cycle.
>
> Signed-off-by: Tobias Waldekranz
Reviewed-by: Florian Fainelli
--
Florian
On 3/17/2021 10:49 AM, Andrew Lunn wrote:
>> BCM6368 (and newer) SoCs have an integrated ethernet switch controller with
>> dedicated internal phys, but it also supports connecting to external phys
>> not integrated in the internal switch.
>> Ports 0-3 are internal, ports 4-7 are external and
On 3/17/2021 7:37 AM, Rafał Miłecki wrote:
> From: Rafał Miłecki
>
> Simple macro like REG_RGMII_CNTRL_P() is insufficient as:
> 1. It doesn't validate port argument
> 2. It doesn't support chipsets with non-lineral RGMII regs layout
>
> Missing port validation could result in getting registe
b3d42 ("Merge branch 'brport-flags'")
which is why we default to enabling learning when the ports gets added
as a bridge member.
Fixes: 967dd82ffc52 ("net: dsa: b53: Add support for Broadcom RoboSwitch")
Signed-off-by: Florian Fainelli
---
drivers/net/dsa/b53/b53_common
b3d42 ("Merge branch 'brport-flags'")
which is why we default to enabling learning when the ports gets added
as a bridge member.
Fixes: 967dd82ffc52 ("net: dsa: b53: Add support for Broadcom RoboSwitch")
Signed-off-by: Florian Fainelli
---
drivers/net/dsa/b53/b53_common.c
Hi Greg, Sasha, Jaakub and David,
This patch series contains backports for a change that recently made it
upstream as f9b3827ee66cfcf297d0acd6ecf33653a5f297ef ("net: dsa: b53:
Support setting learning on port") however that commit depends on
infrastructure that landed in v5.12-rc1.
The way this w
b3d42 ("Merge branch 'brport-flags'")
which is why we default to enabling learning when the ports gets added
as a bridge member.
Fixes: 967dd82ffc52 ("net: dsa: b53: Add support for Broadcom RoboSwitch")
Signed-off-by: Florian Fainelli
---
drivers/net/dsa/b53/b53_common
b3d42 ("Merge branch 'brport-flags'")
which is why we default to enabling learning when the ports gets added
as a bridge member.
Fixes: 967dd82ffc52 ("net: dsa: b53: Add support for Broadcom RoboSwitch")
Signed-off-by: Florian Fainelli
---
drivers/net/dsa/b53/b53_common
b3d42 ("Merge branch 'brport-flags'")
which is why we default to enabling learning when the ports gets added
as a bridge member.
Fixes: 967dd82ffc52 ("net: dsa: b53: Add support for Broadcom RoboSwitch")
Signed-off-by: Florian Fainelli
---
drivers/net/dsa/b53/b53_common.
b3d42 ("Merge branch 'brport-flags'")
which is why we default to enabling learning when the ports gets added
as a bridge member.
Fixes: 967dd82ffc52 ("net: dsa: b53: Add support for Broadcom RoboSwitch")
Signed-off-by: Florian Fainelli
---
drivers/net/dsa/b53/b53_common.c
controller
> driver")
> Signed-off-by: Geert Uytterhoeven
Acked-by: Florian Fainelli
--
Florian
On 3/15/2021 1:09 PM, Vladimir Oltean wrote:
> On Mon, Mar 15, 2021 at 01:03:10PM -0700, Florian Fainelli wrote:
>>
>>
>> On 3/15/2021 10:09 AM, DENG Qingfang wrote:
>>> Support port MDB and bridge flag operations.
>>>
>>> As the hardware can mana
On 3/15/2021 10:09 AM, DENG Qingfang wrote:
> Support port MDB and bridge flag operations.
>
> As the hardware can manage multicast forwarding itself, offload_fwd_mark
> can be unconditionally set to true.
>
> Signed-off-by: DENG Qingfang
> ---
> Changes since RFC:
> Replaced BR_AUTO_MASK w
On 3/15/2021 7:27 AM, Álvaro Fernández Rojas wrote:
> Add support for legacy Broadcom tags, which are similar to DSA_TAG_PROTO_BRCM.
> These tags are used on BCM5325, BCM5365 and BCM63xx switches.
>
> Signed-off-by: Álvaro Fernández Rojas
> ---
> include/net/dsa.h | 2 +
> net/dsa/Kconfig
ing. Whether that works with
only DSA_TAG_PROTO_BRCM_LEGACY or across DSA_PROTO_BRCM_LEGACY +
DSA_TAG_PROTO_BRCM may be something you will have to determine.
Acked-by: Florian Fainelli
--
Florian
On 3/15/2021 8:11 AM, Álvaro Fernández Rojas wrote:
> Add device tree support to b53_mmap.c while keeping platform devices support.
>
> Signed-off-by: Álvaro Fernández Rojas
Acked-by: Florian Fainelli
--
Florian
On 3/13/2021 1:39 AM, Kurt Kanzenbach wrote:
> Allow to dump the FDB table via devlink. This is a useful debugging feature.
>
> Signed-off-by: Kurt Kanzenbach
> Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
--
Florian
On 3/13/2021 1:39 AM, Kurt Kanzenbach wrote:
> hellcreek_select_vlan() takes a boolean instead of an integer.
> So, use false accordingly.
>
> Signed-off-by: Kurt Kanzenbach
> Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
--
Florian
On 3/13/2021 1:39 AM, Kurt Kanzenbach wrote:
> There are two functions which need to populate fdb entries. Move that to a
> helper function.
>
> Signed-off-by: Kurt Kanzenbach
> Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
--
Florian
On 3/13/2021 1:39 AM, Kurt Kanzenbach wrote:
> Allow to dump the VLAN table via devlink. This especially useful, because the
> driver internally leverages VLANs for the port separation. These are not
> visible
> via the bridge utility.
>
> Signed-off-by: Kurt Kanzenbach
Re
The BCM4908 switch has 256 CFP entrie, update that setting so CFP can be
used.
Signed-off-by: Florian Fainelli
---
drivers/net/dsa/bcm_sf2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
index f277df922fcd..60a004f8465d
On 3/11/21 4:04 AM, Joakim Zhang wrote:
>
>> -Original Message-
>> From: Florian Fainelli
>> Sent: 2021年3月9日 1:57
>> To: Joakim Zhang ; Jakub Kicinski
>> ; Andrew Lunn
>> Cc: netdev@vger.kernel.org
>> Subject: Re: stmmac driver timeout issu
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