ading support")
Signed-off-by: DENG Qingfang
---
v1 -> v2:
Refined commit message according to Frank.
drivers/net/ethernet/mediatek/mtk_ppe_offload.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
b/drivers/net/ethe
On Tue, Apr 13, 2021 at 02:12:59PM +0100, Russell King - ARM Linux admin wrote:
> On Tue, Apr 13, 2021 at 11:59:20AM +0800, DENG Qingfang wrote:
> > Within 12 hours, I got some spontaneous link down/ups when EEE is enabled:
> >
> > [16334.236233] mt7530 mdio-bus
.key_offset was assigned to .head_offset instead. Fix the typo.
Fixes: 502e84e2382d ("net: ethernet: mtk_eth_soc: add flow offloading support")
Signed-off-by: DENG Qingfang
---
drivers/net/ethernet/mediatek/mtk_ppe_offload.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
On Tue, Apr 13, 2021 at 02:52:59PM +0200, Andrew Lunn wrote:
> > I guess this is depends whether the most usual case is to have all
> > these interrupts being actively in use or not. Most interrupts only
> > use a limited portion of their interrupt space at any given time.
> > Allocating all interr
On Mon, Apr 12, 2021 at 11:08:36PM +0800, DENG Qingfang wrote:
> On Mon, Apr 12, 2021 at 07:04:49AM +, René van Dorst wrote:
> > Hi Qingfang,
> > > +static void mtk_phy_config_init(struct phy_device *phydev)
> > > +{
> > > + /* Disable EEE */
>
On Mon, Apr 12, 2021 at 06:41:58AM +0200, Ansuel Smith wrote:
> > So, drivers will read the name of every port and decide which CPU port
> > does it use?
> >
>
> Yes, this seems to be an acceptable path to follow. The driver can
> provide a preferred CPU port or just tell DSA that every cpu is equ
On Mon, Apr 12, 2021 at 09:21:12AM +0100, Marc Zyngier wrote:
> On Mon, 12 Apr 2021 04:42:35 +0100,
> DENG Qingfang wrote:
> >
> > Add support for MT7530 interrupt controller to handle internal PHYs.
> > In order to assign an IRQ number to each PHY, the registration of M
On Mon, Apr 12, 2021 at 07:04:49AM +, René van Dorst wrote:
> Hi Qingfang,
> > +static void mtk_phy_config_init(struct phy_device *phydev)
> > +{
> > + /* Disable EEE */
> > + phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
>
> For my EEE patch I changed this line to:
>
> genphy_c
On Sun, Apr 11, 2021 at 09:50:17PM +0300, Vladimir Oltean wrote:
>
> So I'd be tempted to say 'tough luck' if all your ports are not up, and
> the ones that are are assigned statically to the same CPU port. It's a
> compromise between flexibility and simplicity, and I would go for
> simplicity her
Enable MT7530 interrupt controller in the MT7621 SoC.
Signed-off-by: DENG Qingfang
Reviewed-by: Andrew Lunn
---
RFC v3 -> RFC v4:
- Add #interrupt-cells property.
drivers/staging/mt7621-dts/mt7621.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/staging/mt7621-dts/mt7
Add device tree binding to support MT7530 interrupt controller.
Signed-off-by: DENG Qingfang
Reviewed-by: Andrew Lunn
---
RFC v3 -> RFC v4:
- Add #interrupt-cells property.
Documentation/devicetree/bindings/net/dsa/mt7530.txt | 6 ++
1 file changed, 6 insertions(+)
diff --gi
Add support for MT7530 interrupt controller to handle internal PHYs.
In order to assign an IRQ number to each PHY, the registration of MDIO bus
is also done in this driver.
Signed-off-by: DENG Qingfang
---
RFC v3 -> RFC v4:
- No changes.
drivers/net/dsa/Kconfig | 1 +
drivers/net/dsa/mt7
Add support for MediaTek PHYs found in MT7530 and MT7531 switches.
The initialization procedure is from the vendor driver, but due to lack
of documentation, the function of some register values remains unknown.
Signed-off-by: DENG Qingfang
---
RFC v3 -> RFC v4:
- Remove unused include.
driv
Add support for MT7530 interrupt controller.
DENG Qingfang (4):
net: phy: add MediaTek PHY driver
net: dsa: mt7530: add interrupt support
dt-bindings: net: dsa: add MT7530 interrupt controller binding
staging: mt7621-dts: enable MT7530 interrupt controller
.../devicetree/bindings/net
On Sat, Apr 10, 2021 at 03:34:47PM +0200, Ansuel Smith wrote:
> Allow for multiple CPU ports in a DSA switch tree. By default the first
> CPU port is assigned mimic the original assignement logic. A DSA driver
> can define a function to declare a preferred CPU port based on the
> provided port. If
Hi René,
On Sat, Apr 10, 2021 at 6:54 AM René van Dorst wrote:
> --- a/drivers/net/dsa/mt7530.c
> +++ b/drivers/net/dsa/mt7530.c
> @@ -2568,6 +2568,11 @@ static void mt753x_phylink_mac_link_up(struct
> dsa_switch *ds, int port,
> mcr |= PMCR_TX_FC_EN;
> if
Hi René,
On Thu, Apr 8, 2021 at 10:02 PM René van Dorst wrote:
>
> Tested on Ubiquiti ER-X-SFP (MT7621) with 1 external phy which uses irq=POLL.
>
I wonder if the external PHY's IRQ can be registered in the devicetree.
Change MT7530_NUM_PHYS to 6, and add the following to ER-X-SFP dts PHY node:
Enable MT7530 interrupt controller in the MT7621 SoC.
Signed-off-by: DENG Qingfang
Reviewed-by: Andrew Lunn
---
RFC v2 -> RFC v3:
- No changes.
drivers/staging/mt7621-dts/mt7621.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi
b/driv
Add device tree binding to support MT7530 interrupt controller.
Signed-off-by: DENG Qingfang
Reviewed-by: Andrew Lunn
---
RFC v2 -> RFC v3:
- No changes.
Documentation/devicetree/bindings/net/dsa/mt7530.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicet
Add support for MT7530 interrupt controller to handle internal PHYs.
In order to assign an IRQ number to each PHY, the registration of MDIO bus
is also done in this driver.
Signed-off-by: DENG Qingfang
---
RFC v2 -> RFC v3:
- Rework IRQ request and free procedure.
- Add irq_set_nested_thr
Add support for MediaTek PHYs found in MT7530 and MT7531 switches.
The initialization procedure is from the vendor driver, but due to lack
of documentation, the function of some register values remains unknown.
Signed-off-by: DENG Qingfang
Reviewed-by: Andrew Lunn
---
RFC v2 -> RFC v3:
-
Add support for MT7530 interrupt controller.
DENG Qingfang (4):
net: phy: add MediaTek PHY driver
net: dsa: mt7530: add interrupt support
dt-bindings: net: dsa: add MT7530 interrupt controller binding
staging: mt7621-dts: enable MT7530 interrupt controller
.../devicetree/bindings/net
Enable MT7530 interrupt controller in the MT7621 SoC.
Signed-off-by: DENG Qingfang
---
RFC v1 -> RFC v2:
- No changes.
drivers/staging/mt7621-dts/mt7621.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi
b/drivers/staging/mt7621-dts/mt7621.d
Add device tree binding to support MT7530 interrupt controller.
Signed-off-by: DENG Qingfang
---
RFC v1 -> RFC v2:
- No changes.
Documentation/devicetree/bindings/net/dsa/mt7530.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt
Add support for MT7530 interrupt controller to handle internal PHYs.
In order to assign an IRQ number to each PHY, the registration of MDIO bus
is also done in this driver.
Signed-off-by: DENG Qingfang
---
RFC v1 -> RFC v2:
- Split MDIO and IRQ setup function
drivers/net/dsa/Kconfig |
Add support for MediaTek PHYs found in MT7530 and MT7531 switches.
The initialization procedure is from the vendor driver, but due to lack
of documentation, the function of some register values remains unknown.
Signed-off-by: DENG Qingfang
---
RFC v1 -> RFC v2:
- Add PHY interface mode ch
Add support for MT7530 interrupt controller.
DENG Qingfang (4):
net: phy: add MediaTek PHY driver
net: dsa: mt7530: add interrupt support
dt-bindings: net: dsa: add MT7530 interrupt controller binding
staging: mt7621-dts: enable MT7530 interrupt controller
.../devicetree/bindings/net
On Tue, Apr 6, 2021 at 11:49 PM Andrew Lunn wrote:
> O.K. So that makes it similar to the mv88e6xxx. With that driver, i
> kept interrupt setup and mdio setup separate. I add the interrupt
> controller first, and then do mdio setup, calling a helper to map the
> PHY interrupts and assign them to b
On Tue, Apr 6, 2021 at 11:47 PM Chun-Kuang Hu wrote:
>
> Hi, Qingfang:
>
> DENG Qingfang 於 2021年4月6日 週二 下午10:19寫道：
> > --- a/drivers/net/phy/Kconfig
> > +++ b/drivers/net/phy/Kconfig
> > @@ -207,6 +207,11 @@ config MARVELL_88X_PHY
> > Support for
On Tue, Apr 6, 2021 at 11:30 PM Andrew Lunn wrote:
>
> On Tue, Apr 06, 2021 at 10:18:17PM +0800, DENG Qingfang wrote:
> > Add support for MT7530 interrupt controller to handle internal PHYs.
>
> Are the interrupts purely PHY interrupts? Or are there some switch
> operation
On Tue, Apr 6, 2021 at 11:21 PM Andrew Lunn wrote:
>
> On Tue, Apr 06, 2021 at 10:18:16PM +0800, DENG Qingfang wrote:
> > Add support for MediaTek PHYs found in MT7530 and MT7531 switches.
>
> Do you know if this PHY is available standalone?
Not that I know of.
Enable MT7530 interrupt controller in the MT7621 SoC.
Signed-off-by: DENG Qingfang
---
drivers/staging/mt7621-dts/mt7621.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi
b/drivers/staging/mt7621-dts/mt7621.dtsi
index 16fc94f65486..ebf8b0633e88
Add device tree binding to support MT7530 interrupt controller.
Signed-off-by: DENG Qingfang
---
Documentation/devicetree/bindings/net/dsa/mt7530.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt
b/Documentation/devicetree
Add support for MT7530 interrupt controller to handle internal PHYs.
In order to assign an IRQ number to each PHY, the registration of MDIO bus
is also done in this driver.
Signed-off-by: DENG Qingfang
---
drivers/net/dsa/mt7530.c | 203 +++
drivers/net/dsa
Add support for MediaTek PHYs found in MT7530 and MT7531 switches.
The initialization procedure is from the vendor driver, but due to lack
of documentation, the function of some register values remains unknown.
Signed-off-by: DENG Qingfang
---
drivers/net/phy/Kconfig| 5 ++
drivers/net
Add support for MT7530 interrupt controller.
DENG Qingfang (4):
net: phy: add MediaTek PHY driver
net: dsa: mt7530: add interrupt support
dt-bindings: net: dsa: add MT7530 interrupt controller binding
staging: mt7621-dts: enable MT7530 interrupt controller
.../devicetree/bindings/net
On Wed, Mar 24, 2021 at 11:03:54AM +0100, Pablo Neira Ayuso wrote:
>
> For this scenario specifically, it should be possible extend the
> existing flowtable netlink API to allow hostapd to flush entries in
> the flowtable for the client changing AP.
The APs are external, are we going to install h
On Wed, Mar 24, 2021 at 02:30:32AM +0100, Pablo Neira Ayuso wrote:
> This patch adds dev_fill_forward_path() which resolves the path to reach
> the real netdevice from the IP forwarding side. This function takes as
> input the netdevice and the destination hardware address and it walks
> down the d
On Fri, Mar 19, 2021 at 6:49 PM Vladimir Oltean wrote:
> Why would you even want to look at the source net device for forwarding?
> I'd say that if dp->bridge_dev is NULL in the xmit function, you certainly
> want to bypass address learning if you can. Maybe also for link-local traffic.
Also for
On Fri, Mar 19, 2021 at 5:06 PM Vladimir Oltean wrote:
>
> This is a good point actually, which I thought about, but did not give a
> lot of importance to for the moment. Either we go full steam ahead with
> assisted learning on the CPU port for everybody, and we selectively
> learn the addresses
On Fri, Mar 19, 2021 at 01:18:27AM +0200, Vladimir Oltean wrote:
> From: Vladimir Oltean
>
> DSA has gained the recent ability to deal gracefully with upper
> interfaces it cannot offload, such as the bridge, bonding or team
> drivers. When such uppers exist, the ports are still in standalone mod
[ Upstream commit 9200f515c41f4cbaeffd8fdd1d8b6373a18b1b67 ]
A different TPID bit is used for 802.1ad VLAN frames.
Reported-by: Ilario Gelmetti
Fixes: f0af34317f4b ("net: dsa: mediatek: combine MediaTek tag with VLAN tag")
Signed-off-by: DENG Qingfang
Signed-off-by: David S. Miller
On Tue, Mar 16, 2021 at 5:15 AM Vladimir Oltean wrote:
>
> Actually this is just how Qingfang explained it:
> https://patchwork.kernel.org/project/netdevbpf/patch/20210224081018.24719-1-dqf...@gmail.com/
>
> I just assume that MT7530/7531 switches don't need to enable flooding on
> user ports when
Support port MDB and bridge flag operations.
As the hardware can manage multicast forwarding itself, offload_fwd_mark
can be unconditionally set to true.
Signed-off-by: DENG Qingfang
---
Changes since RFC:
Replaced BR_AUTO_MASK with BR_FLOOD | BR_LEARNING
drivers/net/dsa/mt7530.c | 124
Since commit 7b9a2f4bac68 ("net: dsa: use ports list to find slave"),
dsa_master_find_slave() has been iterating over a linked list instead
of accessing arrays, making its time complexity O(n).
The said function is called frequently in DSA RX path, so it may cause
a performance hit, especially for
On Mon, Mar 1, 2021 at 9:48 PM Linus Walleij wrote:
> With my minor changes:
> Tested-by: Linus Walleij
How about using a mutex lock in port_bridge_{join,leave} ?
In my opinion all functions that access multiple registers should be
synchronized.
> Yours,
> Linus Walleij
On Mon, Mar 1, 2021 at 9:55 PM Linus Walleij wrote:
>
> BTW where did you find this register? It's not in any of my
> vendor driver code dumps.
DD-WRT
https://svn.dd-wrt.com/browser/src/linux/universal/linux-4.14/drivers/net/ethernet/ag7100/RTL8366RB_DRIVER/rtl8368s_reg.h#L581
>
> Curious!
>
> Y
A different TPID bit is used for 802.1ad VLAN frames.
Reported-by: Ilario Gelmetti
Fixes: f0af34317f4b ("net: dsa: mediatek: combine MediaTek tag with VLAN tag")
Signed-off-by: DENG Qingfang
---
net/dsa/tag_mtk.c | 19 +--
1 file changed, 13 insertions(+), 6 deletion
. It has been done by DSA core since commit
a3b0b6479700.
- A u16 pointer points to skb data. It should be __be16 for network
byte order.
- Typo in comments. "numer" -> "number".
Fixes: 86dd9868b878 ("net: dsa: tag_rtl4_a: Support also egress tags")
Signed-of
On Sun, Feb 28, 2021 at 7:47 AM Linus Walleij wrote:
>
> I names the previous protocol "RTL4 A" after a 4-byte tag
> with protocol indicted as "A", what about naming this
> "RTL2 9" in the same vein? It will be good if some other
> switch is using the same protocol. (If any...)
RTL8306 uses 0x9 t
lude GPIO support if GPIOLIB is not enabled.
Fixes: 429a0edeefd8 ("net: dsa: mt7530: MT7530 optional GPIO support")
Reported-by: Arnd Bergmann
Signed-off-by: DENG Qingfang
---
drivers/net/dsa/mt7530.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/net/dsa/mt7530.c b/
Hi Arnd,
On Thu, Feb 25, 2021 at 10:40 PM Arnd Bergmann wrote:
>
> From: Arnd Bergmann
>
> The new gpio support may be optional at runtime, but it requires
> building against gpiolib:
>
> ERROR: modpost: "gpiochip_get_data" [drivers/net/dsa/mt7530.ko] undefined!
> ERROR: modpost: "devm_gpiochip_
Hi Vladimir,
On Wed, Feb 24, 2021 at 4:42 PM Vladimir Oltean wrote:
>
> I think the comment is incorrect and this _enables_ flooding (which btw
> is ok until we get the address filtering thing sorted out).
The initial value of these FFP fields is all 1's (0xFF). Writing the
CPU port bit here wil
Support port MDB and bridge flag operations.
As the hardware can manage multicast forwarding itself, offload_fwd_mark
can be unconditionally set to true.
Signed-off-by: DENG Qingfang
---
Changes:
Add bridge flag operations and resend as RFC
drivers/net/dsa/mt7530.c | 123
Use port isolation registers to configure bridge offloading.
Remove the VLAN init, as we have proper CPU tag and bridge offloading
support now.
Signed-off-by: DENG Qingfang
---
This is not tested, as I don't have a RTL8366RB board. And I think there
is potential race condition in port_br
Support port MDB add to/delete from MT7530 ARL.
As the hardware can manage multicast forwarding itself, trapping
multicast traffic to the CPU is no longer required.
Signed-off-by: DENG Qingfang
---
v1 -> v2: fix commit message
drivers/net/dsa/mt7530.c |
As the hardware can manage multicast forwarding itself, trapping
multicast traffic to the CPU is no longer required.
Signed-off-by: DENG Qingfang
---
drivers/net/dsa/mt7530.c | 58 +---
net/dsa/tag_mtk.c| 14 +-
2 files changed, 56 insertions
2 bytes of the MTU are reserved for Atheros DSA tag, but DSA core
has already handled that since commit dc0fe7d47f9f.
Remove the unnecessary reservation.
Fixes: d51b6ce441d3 ("net: ethernet: add ag71xx driver")
Signed-off-by: DENG Qingfang
---
drivers/net/ethernet/atheros/ag71xx.c |
On Wed, Feb 17, 2021 at 7:12 PM Linus Walleij wrote:
>
> Overall the question about whether the switch is 5+1 or 7+1 is my
> big design remark.
>
> Maybe it is only 5+1 who knows...
Yes, it's 5+1.
https://cdn.jsdelivr.net/gh/libc0607/Realtek_switch_hacking@files/rtl8366s_8366sr_datasheet_vpre-1.4
On Wed, Feb 17, 2021 at 7:55 AM Linus Walleij wrote:
>
> +
> + /* Pad out to at least 60 bytes */
> + if (unlikely(eth_skb_pad(skb)))
> + return NULL;
I just found that this will cause double free (eth_skb_pad will free
the skb if allocation fails, and dsa_slave_xmit wil
On Wed, Feb 17, 2021 at 6:55 PM Linus Walleij wrote:
>
> I suppose this switch can just use the existing RTL4 A tag
> code after the recent patch so this one is not needed?
No. Different protocol (0x9 instead of 0xA) and different xmit tag
format (port bit mask instead of port number).
Please tak
Add support for Realtek RTL8366S switch tag
Signed-off-by: DENG Qingfang
---
include/net/dsa.h | 2 +
net/dsa/Kconfig| 6 +++
net/dsa/Makefile | 1 +
net/dsa/tag_rtl8366s.c | 98 ++
4 files changed, 107 insertions(+)
create mode
Support Realtek RTL8366S/SR switch
Signed-off-by: DENG Qingfang
---
drivers/net/dsa/Kconfig|1 +
drivers/net/dsa/Makefile |2 +-
drivers/net/dsa/realtek-smi-core.c |3 +-
drivers/net/dsa/realtek-smi-core.h |1 +
drivers/net/dsa/rtl8366s.c | 1165
Add DSA driver and tag for Realtek RTL8366S/SR.
Posting this as RFC because Linus Walleij told me that Mauri Sandberg was
working on this driver too, and some of the features are not yet tested.
DENG Qingfang (2):
net: dsa: add Realtek RTL8366S switch tag
net: dsa: add Realtek RTL8366S
On Wed, Feb 17, 2021 at 7:55 AM Linus Walleij wrote:
>
> + if (skb_cow_head(skb, RTL4_A_HDR_LEN) < 0)
> + return NULL;
skb_cow_head is unnecessary here. DSA core will do it for you.
> +
> + out = (RTL4_A_PROTOCOL_RTL8366RB << 12) | (2 << 8);
> + /* The lower bits
On Wed, Feb 17, 2021 at 11:29 AM Andrew Lunn wrote:
>
> > + /* Pad out to at least 60 bytes */
> > + if (unlikely(eth_skb_pad(skb)))
> > + return NULL;
>
> The core will do the padding for you. Turn on .tail_tag in
> dsa_device_ops.
>
Please don't. .tail_tag does far more than
Hi Tobias,
I've tested your patch series on kernel 5.4 and found that it only works
when VLAN filtering is enabled.
After some debugging, I noticed DSA will add static entries to ATU 0 if
VLAN filtering is disabled, regardless of default_pvid of the bridge,
which is also the ATU# used by the bridg
On Sun, Jan 31, 2021 at 8:39 AM Vladimir Oltean wrote:
>
> Tobias has a point in a way too, you should get used to adding the
> 'master static' flags to your bridge fdb commands, otherwise weird
> things like this could happen. The faulty code can only be triggered
> when going through dsa_legacy_
Having multiple destination ports for a unicast address does not make
sense.
Make port_db_load_purge override existent unicast portvec instead of
adding a new port bit.
Fixes: 884729399260 ("net: dsa: mv88e6xxx: handle multiple ports in ATU")
Signed-off-by: DENG Qingfang
---
drive
On Mon, Jan 25, 2021 at 11:52 PM Rob Herring wrote:
>
> Please add Acked-by/Reviewed-by tags when posting new versions. However,
> there's no need to repost patches *only* to add the tags. The upstream
> maintainer will do that for acks received on the version they apply.
Sorry. Will do that next
Add device tree binding to support MT7530 GPIO controller.
Signed-off-by: DENG Qingfang
---
Changes v1 -> v2:
No changes.
Documentation/devicetree/bindings/net/dsa/mt7530.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.
MT7530's LED controller can drive up to 15 LED/GPIOs.
Add support for GPIO control and allow users to use its GPIOs by
setting gpio-controller property in device tree.
Signed-off-by: DENG Qingfang
---
Changes v1 -> v2:
Set Output Enable after changing direction to output to avoid signa
MT7530's LED controller can be used as GPIO controller. Add support for
it.
DENG Qingfang (2):
dt-bindings: net: dsa: add MT7530 GPIO controller binding
net: dsa: mt7530: MT7530 optional GPIO support
.../devicetree/bindings/net/dsa/mt7530.txt| 6 +
drivers/net/dsa/mt7
MT762x HW, except for MT7628, supports frame length up to 2048
(maximum length on GDM), so allow setting MTU up to 2030.
Also set the default frame length to the hardware default 1518.
Signed-off-by: DENG Qingfang
---
Changes v1 -> v2:
- Set netdev->max_mtu accordingly
- Mention default
Hi Linus,
On Mon, Jan 18, 2021 at 10:55 PM Linus Walleij wrote:
>
> So for offset 0..14 this becomes bits
> 0, 1, 2, 4, 5, 6, 8, 9, 10, 12 ... 18
>
> What is the logic in this and is it what you intend?
Yes. Bit 0..2 are phy 0's LED 0..2, bit 4..6 are phy 1's LED 0..2, etc.
> Please add a comm
Hi Marek,
On Mon, Jan 11, 2021 at 11:46 PM Marek Behún wrote:
>
> what modes does the LED support? Does it support blinking on rx/tx?
> What about link status?
Yes. But unfortunately they cannot be controlled individually, unless
on GPIO mode.
> I'd like to know because I am still working on pa
On Mon, Jan 11, 2021 at 7:04 PM Russell King - ARM Linux admin
wrote:
>
> FYI, Documentation/driver-api/gpio/consumer.rst says:
>
> For output GPIOs, the value provided becomes the initial output value.
> This helps avoid signal glitching during system startup.
>
> Setting the pin to be an out
MT7530's LED controller can drive up to 15 LED/GPIOs.
Add support for GPIO control and allow users to use its GPIOs by
setting gpio-controller property in device tree.
Signed-off-by: DENG Qingfang
---
drivers/net/dsa/mt7530.c | 96
drivers/ne
Add device tree binding to support MT7530 GPIO controller.
Signed-off-by: DENG Qingfang
---
Documentation/devicetree/bindings/net/dsa/mt7530.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt
b/Documentation/devicetree/bindings
MT7530's LED controller can be used as GPIO controller. Add support for
it.
DENG Qingfang (2):
dt-bindings: net: dsa: add MT7530 GPIO controller binding
drivers: net: dsa: mt7530: MT7530 optional GPIO support
.../devicetree/bindings/net/dsa/mt7530.txt| 6 ++
drivers/net/dsa/mt7
Hi Andrew,
On Wed, Dec 30, 2020 at 11:23 PM Andrew Lunn wrote:
>
> On Wed, Dec 30, 2020 at 09:42:09AM +, Marc Zyngier wrote:
> > > +static irqreturn_t
> > > +mt7530_irq(int irq, void *data)
> > > +{
> > > + struct mt7530_priv *priv = data;
> > > + bool handled = false;
> > > + int phy;
Hi Heiner,
Thanks for your reply.
On Wed, Dec 30, 2020 at 3:39 PM Heiner Kallweit wrote:
> I don't think that's the best option.
I'm well aware of that.
> You may want to add a PHY driver for your chip. Supposedly it
> supports at least PHY suspend/resume. You can use the RTL8366RB
> PHY driver
Hi,
I added MT7530 IRQ support and registered its internal PHYs to IRQ.
It works but my patch used two hacks.
1. Removed phy_drv_supports_irq check, because config_intr and
handle_interrupt are not set for Generic PHY.
2. Allocated ds->slave_mii_bus before calling ds->ops->setup, because
we cann
On Sun, Dec 20, 2020 at 3:49 PM Vladimir Oltean wrote:
> But still, what is at memory address 0x1e11, if the switch is
> accessed over MDIO?
It's "Ethernet GMAC", handled by mtk_eth_soc.
Hi Vladimir,
On Sun, Dec 20, 2020 at 3:48 AM Vladimir Oltean wrote:
>
> Hi Andrew, Florian,
>
> On Sat, Dec 19, 2020 at 09:07:13AM -0800, Florian Fainelli wrote:
> > On 12/19/2020 8:26 AM, Andrew Lunn wrote:
> > >> --- a/drivers/net/dsa/mt7530.c
> > >> +++ b/drivers/net/dsa/mt7530.c
> > >> @@ -26
MT7621 is a SoC, so using "mediatek,mt7621" as its compatible is ambiguous.
Rename it to "mediatek,mt7621-gsw".
Signed-off-by: DENG Qingfang
---
Documentation/devicetree/bindings/net/dsa/mt7530.txt | 8
drivers/net/dsa/mt7530.c | 2 +-
MT7530 has a global RX length register, so we are actually changing its
MRU.
Enable MTU normalization for this reason.
Signed-off-by: DENG Qingfang
---
drivers/net/dsa/mt7530.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index
MT7530 has a global address age control register, so use it to set
ageing time.
The applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds
Signed-off-by: DENG Qingfang
---
drivers/net/dsa/mt7530.c | 41
drivers/net/dsa/mt7530.h | 13 +
2
MT762x HW, except for MT7628, supports frame length up to 2048
(maximum length on GDM), so allow setting MTU up to 2030.
Signed-off-by: DENG Qingfang
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 36 -
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 +--
2 files
On Fri, Nov 20, 2020 at 10:26 AM Andrew Lunn wrote:
> The bridge code will default to 300 seconds. And after a topology
> change, it sets it to 2 * the forwarding delay, which defaults to 15
> seconds. So maybe you can look for these two values, and use
> pre-computed values?
15 and 300 are not l
MT7530 has a global address age control register, so use it to set
ageing time.
The applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds
Signed-off-by: DENG Qingfang
---
drivers/net/dsa/mt7530.c | 41
drivers/net/dsa/mt7530.h | 13 +
2
rfaces. The problem is
> that DSA currently only cares about SWITCHDEV_FDB_ADD_TO_DEVICE events
> received on its own interfaces, such as static FDB entries.
>
> Luckily we can change that, and DSA can listen to all switchdev FDB
> add/del events in the system and figure out i
MT7530/7531 has a global RX packet length register, which can be used
to set MTU.
Supported packet length values are 1522 (1518 if untagged), 1536,
1552, and multiple of 1024 (from 2048 to 15360).
Signed-off-by: DENG Qingfang
---
v2 -> v3:
Fix checkpatch.pl warning
v1 -&
MT7530/7531 has a global RX packet length register, which can be used
to set MTU.
Supported packet length values are 1522 (1518 if untagged), 1536, 1552,
and multiple of 1024 (from 2048 to 15360).
Signed-off-by: DENG Qingfang
---
v1 -> v2:
Avoid duplication of mt7530_rmw()
On Fri, Oct 30, 2020 at 6:42 AM Jakub Kicinski wrote:
>
> On Thu, 29 Oct 2020 02:12:21 +0800 DENG Qingfang wrote:
> > MT7530/7531 has a global RX packet length register, which can be used
> > to set MTU.
> >
> > Signed-off-by: DENG Qingfang
>
> Please wrap you
On Thu, Oct 29, 2020 at 9:02 PM Andrew Lunn wrote:
>
> On Thu, Oct 29, 2020 at 02:39:15PM +0800, DENG Qingfang wrote:
> > MT762x HW supports frame length up to 2048 (maximum length on GDM),
> > so allow setting MTU up to 2030.
> >
> > Signed-off-by: DENG Qingfang
On Thu, Oct 29, 2020 at 4:11 PM Jonathan McDowell wrote:
>
> On Thu, Oct 29, 2020 at 11:32:36AM +0800, DENG Qingfang wrote:
> > On Thu, Oct 29, 2020 at 2:31 AM Vladimir Oltean wrote:
> > >
> > > On Thu, Oct 29, 2020 at 02:12:21AM +0800, DENG Qingfang wr
On Thu, Oct 29, 2020 at 2:31 AM Vladimir Oltean wrote:
>
> On Thu, Oct 29, 2020 at 02:12:21AM +0800, DENG Qingfang wrote:
> > MT7530/7531 has a global RX packet length register, which can be used
> > to set MTU.
> >
> > Signed-off-by: DENG Qingfang
> >
MT762x HW supports frame length up to 2048 (maximum length on GDM),
so allow setting MTU up to 2030.
Signed-off-by: DENG Qingfang
---
I only tested this on MT7621, no sure if it is applicable for other SoCs
especially MT7628, which has an old IP.
---
drivers/net/ethernet/mediatek
MT7530/7531 has a global RX packet length register, which can be used
to set MTU.
Signed-off-by: DENG Qingfang
---
drivers/net/dsa/mt7530.c | 36
drivers/net/dsa/mt7530.h | 12
2 files changed, 48 insertions(+)
diff --git a/drivers/net/dsa
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