Oh, how silly :)
Reviewed-by: Chris Forbes
- Chris
On Fri, Jun 19, 2015 at 11:19 AM, Matt Turner wrote:
> Fixes a performance problem caused by commit b639ed2f.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90895
> ---
> src/mesa/drivers/dri/i965/brw_meta_f
Recent convention has been to use unreachable("str") rather than assert(!"str")
On Tue, Jun 23, 2015 at 1:07 PM, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_vec4_vp.cpp | 9 +++--
> 1 file changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw
Is fairly unpleasant that the clip plane plumbing needs to be so
special in the visitors at all -- but breaking the context dependency
is a win.
- Chris
On Tue, Jun 23, 2015 at 1:07 PM, Jason Ekstrand wrote:
> Previously, these were pulled out of the GL context conditionally based on
> whether w
For the series:
Reviewed-by: Chris Forbes
On Tue, Jun 23, 2015 at 1:07 PM, Jason Ekstrand wrote:
> As of this commit, nothing actually needs the brw_context.
> ---
> src/mesa/drivers/dri/i965/brw_cs.cpp| 6 --
> src/mesa/drivers/dri/i965/brw_fs.cpp
Reviewed-by: Chris Forbes
On Sat, Jun 27, 2015 at 11:31 AM, Kenneth Graunke wrote:
> On Friday, June 26, 2015 04:17:39 PM Jason Ekstrand wrote:
>> On Fri, Jun 26, 2015 at 3:56 PM, Kenneth Graunke
>> wrote:
>> > Legacy user clipping (using gl_Position or gl_C
Seems reasonable to me.
Reviewed-by: Chris Forbes
On Thu, Jul 2, 2015 at 7:18 AM, Ilia Mirkin wrote:
> Commit 4b249d2ee (mesa: Handle transferOps in texstore_rgba) introduced
> proper transferops handling, but in updating the source to the newly
> allocated temporary image neglected
Reviewed-by: Chris Forbes
On Thu, Jul 2, 2015 at 4:16 AM, Mike Stroyan wrote:
> When there are no color buffer render targets, gen6 and gen7 still
> use the first BLEND_STATE element to determine alpha test.
> gen6_upload_blend_state was allocating zero elements when
> ctx->Col
Seems fair.
Reviewed-by: Chris Forbes
On Thu, Jul 2, 2015 at 10:22 AM, Ilia Mirkin wrote:
> The optimization logic relies on being able to read out constbuf values
> from program parameters. However that only works if there's no relative
> addressing involved.
>
Looks OK to me. I didn't think there was going to be much required to
make this work -- is nice that it turned out to be nothing.
Reviewed-by: Chris Forbes
- Chris
On Fri, Jul 3, 2015 at 6:41 AM, Neil Roberts wrote:
> There was a comment saying that in SIMD16 mode the pixel inte
Reviewed-by: Chris Forbes
On Thu, Jul 2, 2015 at 8:08 PM, Kenneth Graunke wrote:
> Matrix vertex attributes have their columns padded out to vec4s, which
> I was failing to account for. Scalar NIR expects them to be packed,
> however.
>
> Cc: mesa-sta...@lists.freedesktop.org
Do you really need is_subroutine_def ? It seems redundant with
num_subroutine_types>0.
On Thu, Jul 9, 2015 at 7:17 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> We need to store two sets of info into the ir_function,
> if this is a function definition with a subroutine list
> (subroutine_def) o
7-12 inclusive are
Reviewed-by: Chris Forbes
On Thu, Jul 9, 2015 at 7:17 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> This type will be used to store the name of subroutine types
>
> as in subroutine void myfunc(void);
> will store myfunc into a subroutine type.
>
>
Perf data?
On Fri, Jul 10, 2015 at 6:41 PM, Timothy Arceri wrote:
> This implementation should be faster and there was no
> need to store a data field.
> ---
> src/glsl/ir_validate.cpp | 24
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/src/glsl/ir
Surely the *right* thing would be to have the correct order expressed
in brw->vb.*, instead so you don't have this workaround in multiple
places.
As a minimal fix for stable though, this seems OK, so -
Reviewed-by: Chris Forbes
On Sat, Jul 11, 2015 at 5:04 AM, Neil Roberts wrote:
&g
s/interpolater/interpolator/g
On Fri, Jul 10, 2015 at 1:31 AM, Neil Roberts wrote:
> For centroid interpolation we can just directly use the values set up
> in the shader payload instead of querying the pixel interpolator. To
> do this we need to modify brw_compute_barycentric_interp_modes to
> d
n the tests,
because they compare with a centroid-qualified input. [I'm assuming
you don't always get these delivered to the FS in SKL, but no docs
access...]
- Chris
On Sat, Jul 11, 2015 at 11:18 AM, Chris Forbes wrote:
> s/interpolater/interpolator/g
>
> On Fri, Jul 10, 2015
Oh, never mind - I see there's another hunk that my mailer had folded away
for some reason. I'm happy that it's correct now :)
On Jul 13, 2015 23:33, "Neil Roberts" wrote:
> Chris Forbes writes:
>
> > Nitpicks aside, I don't think this is a great idea
This fixes my HSW getting dropped back to 3.2 most of the time, and
seems like the reasonable thing to do.
Tested-and-acked-by: Chris Forbes
On Tue, Jul 21, 2015 at 11:58 PM, Chris Wilson wrote:
> I was mistaken, I thought we already had fixed this in the kernel a
> couple of years ago.
For the series
Reviewed-by: Chris Forbes
On Oct 27, 2015 7:03 AM, "Kenneth Graunke" wrote:
> Normally, we could read gl_Layer from bits 26:16 of R0.0. However, the
> specification requires that bogus out-of-range 32-bit values written by
> previous stages need to appear in
Presumably ARB_internalformat_query2?
On Tue, Oct 27, 2015 at 9:31 PM, Eduardo Lima Mitev
wrote:
> Hello,
>
> This is an announcement that a few folks at Igalia team are planning to
> work on adding support for EXT_internalformat_query2 extension to Mesa.
>
> If somebody had started work on this
Ugh, I'd thinko'd this on first reading and assumed that the
adjustment was header.3 += temp -- but it's not; it's header.3 = r0.3
+ temp so this is fine.
Reviewed-by: Chris Forbes
On Fri, Jan 23, 2015 at 10:50 AM, Jason Ekstrand wrote:
> Prior to this commit, the adjus
With the new commit message,
Reviewed-by: Chris Forbes
On Sat, Jan 31, 2015 at 2:08 PM, Laura Ekstrand wrote:
> It's updated to:
>
> GL: Update glext.h to Khronos Revision 29537.
>
> Khronos Revision 29537 fixes ARB_direct_state_access function prototypes
> that
Glenn,
Fixed in the version of this patch which landed (d36fa601913 on master).
- Chris
On Mon, Feb 2, 2015 at 2:08 PM, Glenn Kennard wrote:
> On Wed, 31 Dec 2014 21:43:51 +0100, Micah Fedke
> wrote:
>
>> ---
>> src/glsl/glcpp/glcpp-parse.y| 3 +++
>> src/glsl/glsl_parser_extras.cpp | 1 +
I think 'component_size' would be better over the various dmul, size_mul, etc.
On Fri, Feb 6, 2015 at 5:56 PM, Ilia Mirkin wrote:
> From: Dave Airlie
>
> This adds support for the new uniform interfaces
> from ARB_gpu_shader_fp64.
>
> v2:
> support ARB_separate_shader_objects ProgramUniform*d* (
Looks good to me.
Reviewed-by: Chris Forbes
On Sat, Feb 7, 2015 at 1:32 AM, Kenneth Graunke wrote:
> +82 Piglits - 100% of border color tests now pass on Haswell.
>
> Signed-off-by: Kenneth Graunke
> Cc: Chris Forbes
> Cc: mesa-sta...@lists.freedesktop.org
> ---
> src/
Reviewed-by: Chris Forbes
On Sat, Feb 7, 2015 at 1:32 AM, Kenneth Graunke wrote:
> The hardware's integer luminance formats are completely unusable;
> currently we fall back to RGBA. This means we need to override
> the texture swizzle to obtain the XXX1 values expected for lumin
Renderbuffers are never layered. Previously we'd just leave whatever
value was present from the previous attachment.
Signed-off-by: Chris Forbes
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89026
---
src/mesa/main/fbobject.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src
Apologies -- I'd not noticed that there was an equivalent patch
already attached to the bug report.
In that case, James Legg's patch is:
Reviewed-by: Chris Forbes
(and I'll push it shortly)
On Sun, Feb 8, 2015 at 1:47 PM, Chris Forbes wrote:
> Renderbuffers are never layere
Looks reasonable, if it's going to be a while before an i965 backend is ready..
Reviewed-by: Chris Forbes
On Fri, Feb 20, 2015 at 12:38 PM, Dave Airlie wrote:
> This just fills in some blanks to avoid warnings in the i965 driver.
>
> Signed-off-by: Dave Airlie
> ---
>
Reviewed-by: Chris Forbes
On Fri, Feb 27, 2015 at 5:52 PM, Jason Ekstrand wrote:
> I'll admit that I don't know that portion of the code all that well, but it
> looks sensible to me.
>
> Reviewed-by: Jason Ekstrand
>
> On Thu, Feb 26, 2015 at 3:55
it happened
to match the VS-out layout.
Signed-off-by: Chris Forbes
Cc: "10.4"
---
src/mesa/drivers/dri/i965/brw_gs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c
b/src/mesa/drivers/dri/i965/brw_gs.c
index 1fba76a..efcff09 10
Thanks Matt -- yes, for 10.5 as well.
I'll also note that this fixes:
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=5
On Sat, Feb 28, 2015 at 8:48 PM, Matt Turner wrote:
> On Fri, Feb 27, 2015 at 11:03 PM, Chris Forbes wrote:
>> Previously, we compared our new GS-
Reviewed-by: Chris Forbes
On Wed, Mar 4, 2015 at 2:25 PM, Jordan Justen wrote:
> Same idea as this patch, only for gen6_gs_visitor:
>
> commit 49a938a265f5959c9b558995cc658f80acb6eb18
> Author: Jordan Justen
> Date: Fri Feb 20 12:12:25 2015 -0800
> i965/fs: Use fs_reg
This looks like it misses the interactions with texture completeness.
- Chris
On Wed, Feb 1, 2017 at 7:53 AM, Plamena Manolova wrote:
> This extension provides a new texture and sampler parameter
> (TEXTURE_REDUCTION_MODE_ARB) which allows applications to produce a
> filtered texel value by com
Reviewed-by: Chris Forbes
On Sat, Jul 25, 2015 at 9:07 AM, Ilia Mirkin wrote:
> The 420pack extension enables various GLSL rules that need to be applied
> to any GLSL 4.20+ shader even if the extension is not explicitly
> enabled.
>
> Signed-off-by: Ilia Mirkin
> ---
> sr
-index-inout-mat2-row
* shaders@out-parameter-indexing@vs-inout-index-inout-vec4
* shaders@out-parameter-indexing@vs-inout-index-inout-vec4-array-element
Further changes are needed for other expression types.
Signed-off-by: Chris Forbes
Cc: Ben Widawsky
---
src/glsl/ast_function.cpp | 15
Some perf numbers would be nice. How much is this winning?
- Chris
On Mon, Aug 3, 2015 at 11:18 AM, Timothy Arceri wrote:
> On Sun, 2015-08-02 at 19:50 +0200, Alejandro Seguí wrote:
>
> Maybe just for completeness you could add this to the commit message
>
> The util/hash_table was intended to b
that should be determined, and
> we should just mass-migrate...
>
> -ilia
>
> On Sun, Aug 2, 2015 at 8:05 PM, Chris Forbes wrote:
> > Some perf numbers would be nice. How much is this winning?
> >
> > - Chris
> >
> > On Mon, Aug 3, 2015 at 11:18 AM, Timo
I'd just add a 2015 block and a 2014 block.
On Thu, Aug 13, 2015 at 9:36 AM, Ilia Mirkin wrote:
> On Wed, Aug 12, 2015 at 5:23 PM, Thomas Helland
> wrote:
>> 2015-08-12 18:56 GMT+02:00 Kenneth Graunke :
>>> On Wednesday, August 12, 2015 06:32:50 PM Thomas Helland wrote:
2015-08-12 17:48 GMT
Reviewed-by: Chris Forbes
On Fri, Aug 14, 2015 at 9:52 AM, Kenneth Graunke wrote:
> We now print out the name of the message instead of its numerical
> value, and label the message control and surface numbers.
>
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri
This patch isn't right. These enum values are the same as the desktop
version, so your new cases will never actually be used.
On Mon, Aug 29, 2016 at 2:24 AM, Francesco Ansanelli
wrote:
> Signed-off-by: Francesco Ansanelli
> ---
> src/mesa/main/texparam.c | 48 ++
Now that we also have to consider OES_viewport_array & friends, nothing uses
this.
Signed-off-by: Chris Forbes
---
src/mesa/main/get.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index 5f5e76a..854f8ab 100644
--- a/src/mesa/main/get.c
+++ b
The mesa default is 4, but we program the hardware for 8 on all
generations.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_context.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index
The HW limits here are -8/7 when using the gather4 message. [gather4_po
allows -32/31, and specified per channel]
On Mon, Nov 28, 2016 at 10:49 AM, Ilia Mirkin wrote:
> This matches what NVIDIA and AMD hardware expose.
>
> Signed-off-by: Ilia Mirkin
> ---
>
> Not sure what the true HW limit is
This patch misses adding the #define to the GLSL preprocessor. Other than
that it looks good though, so with that fixed:
Reviewed-by: Chris Forbes
On Thu, Dec 1, 2016 at 8:53 AM, Plamena Manolova wrote:
> This extension allows the fragment shader to control whether values in
> gl_Sample
Excellent, disregard that. Patch looks good.
On Thu, Dec 1, 2016 at 3:10 PM, Ilia Mirkin wrote:
> On Wed, Nov 30, 2016 at 9:10 PM, Chris Forbes wrote:
> > This patch misses adding the #define to the GLSL preprocessor. Other than
>
> The future is today. That's no longer nec
here looks good, so:
Reviewed-by: Chris Forbes
On Thu, Dec 1, 2016 at 9:00 AM, Plamena Manolova wrote:
> This extension allows the fragment shader to control whether values in
> gl_SampleMaskIn[] reflect the coverage after application of the early
> depth and stencil tests.
>
>
Ilia, it is different from the NV variant -- NV unfortunately threw a bunch
of other stuff in (extra subpixel bits in conservative mode).
Series is:
Reviewed-by: Chris Forbes
On Fri, Dec 2, 2016 at 8:21 AM, Ilia Mirkin wrote:
> Ah, I see. The difference is that it exists, unlike the ARB
I don't see any spec justification for masking this. dEQP is broken here.
Implementations have the flexibility to retain more bits in the mask (and
have more bits set in the initial state) than the depth of the deepest
stencil buffer supported. From the ES3 spec, 4.1.4, second to last para:
"In
On Tue, Jul 12, 2016 at 9:59 PM, Marek Olšák wrote:
+ *endian = r600_endian_swap(32);
I don't fully understand r600, but this 32 seems dubious?
- Chris
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On Tue, Jul 19, 2016 at 8:26 AM, Kenneth Graunke
wrote:
> + default:
> + assert(!"invalid intrinsic");
>
unreachable() ?
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Seems a little unfortunate to add a random bool to this interface which is
otherwise fairly descriptive, but OK.
On Tue, Jul 19, 2016 at 8:26 AM, Kenneth Graunke
wrote:
> While my intention is that the new intrinsics should be usable by all
> drivers, we need to make them optional until all driv
I remember arguing about this when it got added -- tradeoff was payload
size/register pressure vs needing to call out to this unit, if centroid
barycentric coords weren't required for anything else? It does seem fairly
pointless, though.
For the series:-
Reviewed-by: Chris Forbes
On Tue
Oh dear, hacks on both sides. Sorry for this nonsense.
Series is:-
Reviewed-by: Chris Forbes
On Tue, Jul 19, 2016 at 5:16 PM, Jason Ekstrand
wrote:
> From the Sky Lake PRM:
>
>"For SURFTYPE_CUBE: For Sampling Engine Surfaces and Typed Data Port
>Surfaces, the range
We have the destination framebuffer object passed in; there's no need to
go digging around in the context.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri
cube
arrays in the VS.
Signed-off-by: Chris Forbes
Cc: "9.2"
---
src/mesa/drivers/dri/i965/brw_cubemap_normalize.cpp | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cubemap_normalize.cpp
b/src/mesa/driver
This series adds support for ARB_texture_gather in core mesa and in i965 for
Gen7+.
Notable changes from V3:
- Only emit extra surface state, recompiles, etc if the shader actually uses
gather4.
- Use SCS to accomplish the workaround on Haswell [will need testing]
Cc: Kenneth Graunke
From: Maxence Le Dore
Reviewed-by: Kenneth Graunke
---
src/mapi/glapi/gen/ARB_texture_gather.xml | 14 ++
src/mapi/glapi/gen/gl_API.xml | 2 +-
src/mesa/main/context.c | 4
src/mesa/main/extensions.c| 1 +
src/mesa/main/get.c
From: Maxence Le Dore
V2 [Chris Forbes]:
- Add new pattern, fixup parameter reading.
V3: Rebase onto new builtins machinery
Reviewed-by: Kenneth Graunke
---
src/glsl/builtin_functions.cpp | 35 +++
src/glsl/glcpp/glcpp-parse.y| 3 +++
src/glsl
Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and
low-level support for emitting it via generate_tex().
V3: Updated for changes in master.
Signed-off-by: Chris Forbes
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_defines.h | 3 +++
src/mesa/drivers
ffset), and then don't do
anything afterward in the shader.
* For 0/1 swizzles blast the appropriate constant over all the output
channels instead of sampling.
V2: Avoid duplicating header enabling block
V3: Avoid sampling at all, for degenerate swizzles.
Signed-off-by: Chris Forbes
---
Pretty much the same as the FS case. Channel select goes in the header,
V2: Less mangling.
V3: Avoid sampling at all, for degenerate swizzles.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 46
---
src/glsl/ir_set_program_inouts.cpp | 9 +
src/mesa/main/mtypes.h | 2 ++
2 files changed, 11 insertions(+)
diff --git a/src/glsl/ir_set_program_inouts.cpp
b/src/glsl/ir_set_program_inouts.cpp
index 1267d6d..ab23538 100644
--- a/src/glsl/ir_set_program_inouts.cpp
+++ b/src
V4: Only flag quirks if there are any uses of gather in the shader,
to avoid spurious recompiles just because someone happened to use
RG32F.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4
src/mesa/drivers/dri/i965/brw_program.h| 5
gather4 GREEN channel against a surface with format R32G32_FLOAT doesn't work
correctly on IVB. w/a from bspec:
- use R32G32_FLOAT_LD = 0x97 instead, for gather4 only.
- select BLUE channel to read GREEN
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_defines.h
Worst-case is that *every* texunit uses a format that needs overriding.
V4: Place the gather slots last, so shaders which don't use gather don't
get penalized by having a huge binding table.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_cont
can decide what w/a to apply.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_context.h | 3 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 38 +++
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 6 +++-
3 files changed, 39 insert
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_context.c | 1 +
src/mesa/drivers/dri/i965/intel_extensions.c | 4
2 files changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 5f58a29..0d677aa
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 8 ++--
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 8 ++--
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri
The new surface channel select bits allow us to avoid having to
recompile the shader for this workaround.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_wm.c| 5 +++--
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 14 --
2 files changed, 11
With those fixes:
Reviewed-by: Chris Forbes
On Wed, Oct 2, 2013 at 6:38 AM, Ian Romanick wrote:
> On 09/30/2013 10:54 PM, Chia-I Wu wrote:
>> From: Chia-I Wu
>
> I agree with both of Ken's comments. With those fixed, this patch is
>
> Reviewed-by: Ian Romanick
Acked-by: Chris Forbes
On Wed, Oct 2, 2013 at 8:38 AM, Paul Berry wrote:
> Previously, we computed dFdy() using the following instruction:
>
> add(8) dst<1>F src<4,4,0)F -src.2<4,4,0>F { align1 1Q }
>
> That had the disadvantage that it computed the same val
Hi Paul,
Sorry, I should have run make check first.
I'll fix this when I get home.
-- Chris
On Thu, Oct 3, 2013 at 1:06 PM, Paul Berry wrote:
> On 30 September 2013 03:08, Chris Forbes wrote:
>>
>> From: Maxence Le Dore
>>
>> Reviewed-by: Kenneth Graunke
&g
Clean up inconsistency in enum decoration:
- Use the undecorated enums where possible.
- MAX_PROGRAM_TEXTURE_GATHER_COMPONENTS_ARB remains decorated, since it
has no undecorated equivalent in GL4.
Signed-off-by: Chris Forbes
---
src/mapi/glapi/gen/ARB_texture_gather.xml | 6 --
src/mapi
This series adds support for ARB_texture_query_levels on i965 Gen6+. The fourth
channel of the resinfo message (used for textureSize()) includes the correct
value for textureQueryLevels().
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Signed-off-by: Chris Forbes
---
src/mesa/main/extensions.c | 1 +
src/mesa/main/mtypes.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index c0f17c5..2507fdf 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main
Signed-off-by: Chris Forbes
---
src/glsl/builtin_functions.cpp | 56 +
src/glsl/glcpp/glcpp-parse.y| 3 ++
src/glsl/glsl_parser_extras.cpp | 1 +
src/glsl/glsl_parser_extras.h | 2 ++
src/glsl/ir.cpp | 4 +--
src
Previously we special-cased textureSize() but this is the more correct
condition.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_cubemap_normalize.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cubemap_normalize.cpp
b/src
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index a8ad659..6141009 100644
--- a
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 9e6cc78..1112b23 100644
--- a
Theoretically would work on Gen5 as well but requires GLSL 1.30, which
is not (yet) enabled by default there.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa
I haven't tested this thoroughly, but this is how it looks like
it ought to work from the PRM.
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Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/gen7_wm_state.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 80073cd..7ddeb6e 100644
--- a/src/mesa
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 52076f7..6f024b4 100644
--- a/src/mesa/drivers/dri/i965
Eek -- so I am. Thanks for spotting this.
On Sat, Oct 5, 2013 at 8:07 PM, Christoph Brill wrote:
> 2013/10/5 Chris Forbes
>>
>> Signed-off-by: Chris Forbes
>> ---
>> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 15 ++-
>> 1 file chan
This series adds some of the new textureGather variants from ARB_gpu_shader5,
and implementation for i965 Gen7+.
- Use with gsampler2DRect
- Component select in the shader
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ARB_gpu_shader5 introduces new variants of textureGather* which have an
explicit component selector, rather than relying purely on the sampler's
swizzle state.
This patch adds the GLSL plumbing for the extra parameter.
Signed-off-by: Chris Forbes
---
src/glsl/builtin_functions.cpp
- gsampler2DRect support
- optional `comp` parameter
Future patches will add shadow sampler support and
textureGatherOffsets().
Signed-off-by: Chris Forbes
---
src/glsl/builtin_functions.cpp | 27 ++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/src
ff-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 6141009..5508cdc 100644
--- a/src/mesa/dr
ff-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 224524e..4307125 100644
--- a/src
As of ARB_gpu_shader5, textureGather doesn't always read the
post-swizzle RED channel -- so we can't just look at the red swizzle
state.
Theoretically we could only flag the quirk if *some* green swizzle is in
use, but that's probably more trouble than it's worth.
Signed-
Yes, that's clearer; what I had was a strange artifact of how it grew :)
-- Chris
On Sun, Oct 6, 2013 at 6:54 AM, Kenneth Graunke wrote:
> On 10/05/2013 03:38 AM, Chris Forbes wrote:
>> ARB_gpu_shader5 introduces new variants of textureGather* which have an
>> explici
e:
> On 10/05/2013 03:38 AM, Chris Forbes wrote:
>> - For HSW: Select the channel based on the component selected (swizzle
>> is done in HW)
>> - For IVB: Select the channel based on the swizzle state for the
>> component selected. Only apply the RG32F w/a if we actua
- gsampler2DRect
- optional `comp` parameter
Signed-off-by: Chris Forbes
---
src/glsl/builtin_functions.cpp | 16
1 file changed, 16 insertions(+)
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index d40888d..aa40876 100644
--- a/src/glsl
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 45 ++--
1 file changed, 42 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 15cfaa7..fb27ad5
This series adds support for the following textureGather* enhancements
that are part of ARB_gpu_shader5:
- new textureGatherOffset variants
- nonconstant offset for all textureGatherOffset variants, when GLSL 4.00 or
ARB_gpu_shader5 is in use. If only ARB_texture_gather is enabled, const
off
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 0cf8277..20221d9 100644
--- a
Prior to ARB_gpu_shader5 / GLSL 4.0, the offset is required to be
a constant expression.
With that extension, it is relaxed to be any dynamically uniform
expression. If the value is not dynamically uniform, the results
are undefined.
Signed-off-by: Chris Forbes
---
src/glsl
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 61c4bf5..19500d1 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b
The generator code ends up clearer this way than if we had to sniff
via mlen. Implemented via the gather4_po message in hardware, which is
present in Gen7 and later.
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_defines.h | 1 +
src/mesa/drivers/dri/i965/brw_fs.cpp
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