On 05/24/2018 11:10 PM, Samuel Pitoiset wrote:
On 05/24/2018 11:00 PM, Tom Stellard wrote:
On 05/24/2018 01:55 PM, Samuel Pitoiset wrote:
It's recommended by the instruction combining pass, and
RadeonSI also runs it.
This pass used to segfault with one shader of F12017 but it
has been fixe
On 05/24/2018 11:00 PM, Tom Stellard wrote:
On 05/24/2018 01:55 PM, Samuel Pitoiset wrote:
It's recommended by the instruction combining pass, and
RadeonSI also runs it.
This pass used to segfault with one shader of F12017 but it
has been fixed somewhere in LLVM 7.
Do you know which patch
On 05/24/2018 01:55 PM, Samuel Pitoiset wrote:
> It's recommended by the instruction combining pass, and
> RadeonSI also runs it.
>
> This pass used to segfault with one shader of F12017 but it
> has been fixed somewhere in LLVM 7.
>
Do you know which patch fixes this? Or do you have an LLVM IR
Reviewed-by: Bas Nieuwenhuizen
On Thu, May 24, 2018 at 10:55 PM, Samuel Pitoiset
wrote:
> It's recommended by the instruction combining pass, and
> RadeonSI also runs it.
>
> This pass used to segfault with one shader of F12017 but it
> has been fixed somewhere in LLVM 7.
>
> Polaris10:
> Totals
It's recommended by the instruction combining pass, and
RadeonSI also runs it.
This pass used to segfault with one shader of F12017 but it
has been fixed somewhere in LLVM 7.
Polaris10:
Totals from affected shaders:
SGPRS: 441352 -> 441648 (0.07 %)
VGPRS: 310888 -> 300784 (-3.25 %)
Spilled SGPRs:
