On 05/24/2018 01:55 PM, Samuel Pitoiset wrote: > It's recommended by the instruction combining pass, and > RadeonSI also runs it. > > This pass used to segfault with one shader of F12017 but it > has been fixed somewhere in LLVM 7. >
Do you know which patch fixes this? Or do you have an LLVM IR test for this? -Tom > Polaris10: > Totals from affected shaders: > SGPRS: 441352 -> 441648 (0.07 %) > VGPRS: 310888 -> 300784 (-3.25 %) > Spilled SGPRs: 13576 -> 12983 (-4.37 %) > Code Size: 22560328 -> 22420544 (-0.62 %) bytes > Max Waves: 40755 -> 41366 (1.50 %) > > Vega10: > Totals from affected shaders: > SGPRS: 442848 -> 442000 (-0.19 %) > VGPRS: 310396 -> 300460 (-3.20 %) > Spilled SGPRs: 13708 -> 12906 (-5.85 %) > Code Size: 22479428 -> 22336216 (-0.64 %) bytes > Max Waves: 45783 -> 46506 (1.58 %) > > Signed-off-by: Samuel Pitoiset <[email protected]> > --- > src/amd/vulkan/radv_nir_to_llvm.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/src/amd/vulkan/radv_nir_to_llvm.c > b/src/amd/vulkan/radv_nir_to_llvm.c > index b174c027d9..d89c22ea06 100644 > --- a/src/amd/vulkan/radv_nir_to_llvm.c > +++ b/src/amd/vulkan/radv_nir_to_llvm.c > @@ -2982,6 +2982,12 @@ static void ac_llvm_finalize_module(struct > radv_shader_context *ctx) > LLVMAddLICMPass(passmgr); > LLVMAddAggressiveDCEPass(passmgr); > LLVMAddCFGSimplificationPass(passmgr); > +#if HAVE_LLVM >= 0x0700 > + /* XXX: This LLVM pass used to segfault with one shader of F12017. This > + * has been fixed somewhere in LLVM 7. */ > + /* This is recommended by the instruction combining pass. */ > + LLVMAddEarlyCSEMemSSAPass(passmgr); > +#endif > LLVMAddInstructionCombiningPass(passmgr); > > /* Run the pass */ > _______________________________________________ mesa-dev mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-dev
