Re: [Mesa-dev] 16-bit comparisons in NIR

On Sat, Apr 21, 2018 at 2:16 AM, Jason Ekstrand wrote: > > I was thinking about this a bit this morning and it gets even more sticky. > What happens if you have > > bool e = (a < b) && (c < d); > > where a and b are 16-bit and c and d are 32-bit? In this case, one > comprison has a 32-bit value a

[Mesa-dev] [ANNOUNCE] mesa 18.1.0-rc1

Hi All, Mesa 18.1.0-rc1 is now available. git tag: mesa-18.1.0-rc1 https://mesa.freedesktop.org/archive/mesa-18.1.0-rc1.tar.gz MD5: be0da4206ca69655887c3e725df58299 mesa-18.1.0-rc1.tar.gz SHA1: f0aab9f0cd2df751eceab37c0d4203526d01d2a3 mesa-18.1.0-rc1.tar.gz SHA256: ec4b77dfd55fc0af70ee3598de2

[Mesa-dev] [PATCH] anv/allocator: Don't srink either end of the block pool

Previously, we only tried to ensure that we didn't shrink either end below what was already handed out. However, due to the way we handle relocations with block pools, we can't shrink the back end at all. It's probably best to not shrink in either direction. Bugzilla: https://bugs.freedesktop.or

[Mesa-dev] [PATCH] i965/fs: Return mlen * 8 for size_written for INTERPOLATE_AT_*

They are send messages and this makes size_written() and mlen agree. For both of these opcodes, the payload is just a dummy so mlen == 1 and this should decrease register pressure a bit. Cc: Francisco Jerez Cc: mesa-sta...@lists.freedesktop.org --- src/intel/compiler/brw_fs.cpp | 2 ++ 1 file ch

Re: [Mesa-dev] [PATCH] radeonsi/gfx9: fix a hang with an empty first IB

Hi Juan, Here is the patch backported to 18.0: https://cgit.freedesktop.org/~mareko/mesa/commit/?h=amd-18.0&id=7ab59306613b08c7dd6e875c3276cac9a61889ae Marek On Fri, Apr 20, 2018 at 10:57 AM, Juan A. Suarez Romero wrote: > On Tue, 2018-04-17 at 15:54 -0400, Marek Olšák wrote: > > From: Marek O

[Mesa-dev] [Bug 62236] the issue of not correct display from MALI Integer Logic sample

https://bugs.freedesktop.org/show_bug.cgi?id=62236 Timothy Arceri changed: What|Removed |Added Component|Other |Drivers/Gallium/softpipe -- You are re

Re: [Mesa-dev] [PATCH 1/3] Autotools: include include/vulkan headers

On Friday, April 20, 2018 7:19:49 PM PDT Dylan Baker wrote: > Signed-off-by: Dylan Baker > --- > Makefile.am | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/Makefile.am b/Makefile.am > index a83f2bcb5f4..a4ff647f418 100644 > --- a/Makefile.am > +++ b/Makefile.am > @

Re: [Mesa-dev] [PATCH 2/3] Autotools: Add passes.h to sources so it will be included in the tarball

On Friday, April 20, 2018 7:19:50 PM PDT Dylan Baker wrote: > Signed-off-by: Dylan Baker > --- > src/gallium/drivers/swr/Makefile.sources | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/src/gallium/drivers/swr/Makefile.sources > b/src/gallium/drivers/swr/Makefile.sources > index dd815d

Re: [Mesa-dev] [PATCH 3/3] Autotools: Include new meson files

On Friday, April 20, 2018 7:19:51 PM PDT Dylan Baker wrote: > Signed-off-by: Dylan Baker > --- > src/compiler/Makefile.am | 1 + > src/gallium/Makefile.am | 4 +++- > src/gallium/tests/trivial/Makefile.am| 2 ++ > src/gallium/tests/unit/Makefile.am | 2 +

[Mesa-dev] [PATCH 2/3] Autotools: Add passes.h to sources so it will be included in the tarball

Signed-off-by: Dylan Baker --- src/gallium/drivers/swr/Makefile.sources | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/swr/Makefile.sources b/src/gallium/drivers/swr/Makefile.sources index dd815dcb581..a06d1d7b929 100644 --- a/src/gallium/drivers/swr/Makefile.sources +++

[Mesa-dev] [PATCH 3/3] Autotools: Include new meson files

Signed-off-by: Dylan Baker --- src/compiler/Makefile.am | 1 + src/gallium/Makefile.am | 4 +++- src/gallium/tests/trivial/Makefile.am| 2 ++ src/gallium/tests/unit/Makefile.am | 2 ++ src/mesa/state_tracker/tests/Makefile.am | 2 ++ 5 files changed, 10

[Mesa-dev] [PATCH 1/3] Autotools: include include/vulkan headers

Signed-off-by: Dylan Baker --- Makefile.am | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Makefile.am b/Makefile.am index a83f2bcb5f4..a4ff647f418 100644 --- a/Makefile.am +++ b/Makefile.am @@ -67,7 +67,7 @@ EXTRA_DIST = \ bin/install_megadrivers.py \ bin

Re: [Mesa-dev] [PATCH 4/4] intel/compiler: Add scheduler deps for instructions that implicitly read g0

If Ken's good with duct tape then so am I. Rb. On April 20, 2018 17:54:00 Kenneth Graunke wrote: On Friday, April 20, 2018 5:01:17 PM PDT Jason Ekstrand wrote: > On Fri, Apr 20, 2018 at 4:30 PM, Ian Romanick wrote: > > > On 04/20/2018 11:56 AM, Jason Ekstrand wrote: > > > Ugh... I was actual

Re: [Mesa-dev] [PATCH] nvc0: fix line width on GM20x+

I've pushed this. But I do wonder if we should just set LINE_WIDTH_SEPARATE to always false and not worry about this on any GPU. It's not like we really need the two line widths. On Fri, Apr 20, 2018 at 6:32 PM, Rhys Perry wrote: > Signed-off-by: Rhys Perry > --- > src/gallium/drivers/nouveau/n

Re: [Mesa-dev] [PATCH 4/4] intel/compiler: Add scheduler deps for instructions that implicitly read g0

On Friday, April 20, 2018 5:01:17 PM PDT Jason Ekstrand wrote: > On Fri, Apr 20, 2018 at 4:30 PM, Ian Romanick wrote: > > > On 04/20/2018 11:56 AM, Jason Ekstrand wrote: > > > Ugh... I was actually thinking about this the other day. How did you > > > come up with your list of instructions? Is t

Re: [Mesa-dev] 16-bit comparisons in NIR

On Fri, Apr 20, 2018 at 5:16 PM, Jason Ekstrand wrote: > On Fri, Apr 20, 2018 at 5:16 AM, Nicolai Hähnle wrote: >> >> On 20.04.2018 10:21, Iago Toral wrote: >>> >>> Hi, >>> >>> while developing support for Vulkan shaderInt16 on Anvil I came across >>> a feature of NIR that was a bit inconvenient:

Re: [Mesa-dev] 16-bit comparisons in NIR

On Fri, Apr 20, 2018 at 5:16 AM, Nicolai Hähnle wrote: > On 20.04.2018 10:21, Iago Toral wrote: > >> Hi, >> >> while developing support for Vulkan shaderInt16 on Anvil I came across >> a feature of NIR that was a bit inconvenient: bools are always 32-bit >> by design, but the Intel hardware produ

Re: [Mesa-dev] 16-bit comparisons in NIR

On Fri, Apr 20, 2018 at 02:16:17PM +0200, Nicolai Hähnle wrote: > On 20.04.2018 10:21, Iago Toral wrote: > >Hi, > > > >while developing support for Vulkan shaderInt16 on Anvil I came across > >a feature of NIR that was a bit inconvenient: bools are always 32-bit > >by design, but the Intel hardware

Re: [Mesa-dev] [PATCH 3/4] intel/compiler: Silence unused parameter warnings in empty vec4_instruction_scheduler methods

First three are Reviewed-by: Jason Ekstrand On Fri, Apr 20, 2018 at 7:59 AM, Ian Romanick wrote: > From: Ian Romanick > > src/intel/compiler/brw_schedule_instructions.cpp: In member function > ‘virtual void vec4_instruction_scheduler::count_reads_remaining(backend_ > instruction*)’: > src/int

Re: [Mesa-dev] [PATCH 4/4] intel/compiler: Add scheduler deps for instructions that implicitly read g0

On Fri, Apr 20, 2018 at 4:30 PM, Ian Romanick wrote: > On 04/20/2018 11:56 AM, Jason Ekstrand wrote: > > Ugh... I was actually thinking about this the other day. How did you > > come up with your list of instructions? Is there some algorithmic way > > to determine it such as sends with no heade

Re: [Mesa-dev] [PATCH 4/4] intel/compiler: Add scheduler deps for instructions that implicitly read g0

On 04/20/2018 11:56 AM, Jason Ekstrand wrote: > Ugh... I was actually thinking about this the other day.  How did you > come up with your list of instructions?  Is there some algorithmic way > to determine it such as sends with no header? I just looked through the generator for pseudo-ops that emi

Re: [Mesa-dev] [PATCH] i965/urb/cnl: Apply gen7 CS stall

On Thu, Apr 19, 2018 at 05:44:06PM +0300, Topi Pohjolainen wrote: > This didn't actually help the failing tests I'm looking at > but hopefully has teeth elsewhere. > > CC: Jason Ekstrand > CC: Jordan Justen > CC: Anuj Phogat > Signed-off-by: Topi Pohjolainen > --- > src/mesa/drivers/dri/i965/

Re: [Mesa-dev] [PATCH] compiler/glsl: close fd's in glcpp_test.py

Dylan Baker writes: > I would have thought falling out of scope would allow the gc to collect > these, but apparently it doesn't, and this hits an fd limit on macos. Reviewed-by: Eric Anholt signature.asc Description: PGP signature ___ mesa-dev mail

Re: [Mesa-dev] [PATCH v3 3/9] i965: Add and use a getter for the miptree aux buffer

On Fri, Apr 20, 2018 at 02:38:37PM -0700, Nanley Chery wrote: > On Fri, Apr 20, 2018 at 09:58:38AM -0700, Rafael Antognolli wrote: > > Nice, I was planning to do something like this later but didn't want to > > include many more changes on my ongoing series. This looks great, just a > > little comm

[Mesa-dev] [Bug 106163] r600/sb: optimizer tries to schedule access to different array elements in one instruction group

https://bugs.freedesktop.org/show_bug.cgi?id=106163 Gert Wollny changed: What|Removed |Added Summary|r600/sb: optimizer tries to |r600/sb: optimizer tries to

[Mesa-dev] [Bug 106163] r600/sb: optimizer tries to schedule access to different array elements in one intstruction group

https://bugs.freedesktop.org/show_bug.cgi?id=106163 Bug ID: 106163 Summary: r600/sb: optimizer tries to schedule access to different array elements in one intstruction group Product: Mesa Version: git Hardware: All

[Mesa-dev] [PATCH] nvc0: fix line width on GM20x+

Signed-off-by: Rhys Perry --- src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c index 99d45a238a..1977a04832 100644 --- a/src/gallium/d

Re: [Mesa-dev] [PATCH] nvc0: fix line width on GM20x+

When both cso->line_smooth and cso->multisample are both false, this fixes the line rendering issue. So it seems it always uses LINE_WIDTH_SMOOTH. The alternative with the ">= GM204_3D" looks fine. On Fri, Apr 20, 2018 at 11:21 PM, Ilia Mirkin wrote: > On Fri, Apr 20, 2018 at 6:16 PM, Rhys Perry

Re: [Mesa-dev] [PATCH] nvc0: fix line width on GM20x+

On Fri, Apr 20, 2018 at 6:16 PM, Rhys Perry wrote: > Signed-off-by: Rhys Perry > --- > src/gallium/drivers/nouveau/nvc0/nvc0_state.c| 9 + > src/gallium/drivers/nouveau/nvc0/nvc0_stateobj.h | 2 +- > 2 files changed, 6 insertions(+), 5 deletions(-) > > diff --git a/src/gallium/driver

Re: [Mesa-dev] [PATCH v3 7/9] i965: Add and use a getter for the clear color

On Fri, Apr 20, 2018 at 03:01:44PM -0700, Nanley Chery wrote: > On Fri, Apr 20, 2018 at 01:35:39PM -0700, Rafael Antognolli wrote: > > On Wed, Apr 11, 2018 at 01:42:24PM -0700, Nanley Chery wrote: > > > This getter allows CNL to sample from fast-cleared sRGB textures > > > correctly. > > > > I th

[Mesa-dev] [PATCH] nvc0: fix line width on GM20x+

Signed-off-by: Rhys Perry --- src/gallium/drivers/nouveau/nvc0/nvc0_state.c| 9 + src/gallium/drivers/nouveau/nvc0/nvc0_stateobj.h | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c b/src/gallium/drivers/nouveau/nvc0/n

Re: [Mesa-dev] [PATCH 1/2] i965: Add and use a helper to update the indirect miptree color

On Wed, Apr 11, 2018 at 01:56:16PM -0700, Nanley Chery wrote: > Split out this functionality to enable a fast-clear optimization for > color miptrees in the next commit. > --- > src/mesa/drivers/dri/i965/brw_clear.c | 54 > --- > src/mesa/drivers/dri/i965/intel_mip

Re: [Mesa-dev] [PATCH v3 7/9] i965: Add and use a getter for the clear color

On Fri, Apr 20, 2018 at 01:35:39PM -0700, Rafael Antognolli wrote: > On Wed, Apr 11, 2018 at 01:42:24PM -0700, Nanley Chery wrote: > > This getter allows CNL to sample from fast-cleared sRGB textures correctly. > > I think it might be worth mentioning in the commit message that the > helper both r

Re: [Mesa-dev] [PATCH v3 3/9] i965: Add and use a getter for the miptree aux buffer

On Fri, Apr 20, 2018 at 09:58:38AM -0700, Rafael Antognolli wrote: > Nice, I was planning to do something like this later but didn't want to > include many more changes on my ongoing series. This looks great, just a > little comment below. > > On Wed, Apr 11, 2018 at 01:42:20PM -0700, Nanley Chery

Re: [Mesa-dev] [PATCH v3 7/9] i965: Add and use a getter for the clear color

On Wed, Apr 11, 2018 at 01:42:24PM -0700, Nanley Chery wrote: > This getter allows CNL to sample from fast-cleared sRGB textures correctly. I think it might be worth mentioning in the commit message that the helper both returns the clear color for inline use, and updates the pointer to the indirec

Re: [Mesa-dev] [PATCH 4/4] intel/compiler: Add scheduler deps for instructions that implicitly read g0

Ugh... I was actually thinking about this the other day. How did you come up with your list of instructions? Is there some algorithmic way to determine it such as sends with no header? On April 20, 2018 08:52:50 "Ian Romanick" wrote: From: Ian Romanick Otherwise the scheduler can move th

[Mesa-dev] [Bug 106151] [amdgpu][vulkan] GPU hang (Vega 56) while running game (Rise of the Tomb Raider)

https://bugs.freedesktop.org/show_bug.cgi?id=106151 --- Comment #4 from Martin F --- I tried again after updating my kernel to 4.17.0-rc1+ (87ef12027b9b1dd0e0b12cf311fbcb19f9d92539) and after cleaning the cache (~/.cache/mesa_shader_cache/), but the game hanged once more. -- You are receiving t

[Mesa-dev] [Bug 106151] [amdgpu][vulkan] GPU hang (Vega 56) while running game (Rise of the Tomb Raider)

https://bugs.freedesktop.org/show_bug.cgi?id=106151 --- Comment #3 from Martin F --- Hi Samuel. I just tried with your commit but still got a hang, with the same syslog messages as before. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the

[Mesa-dev] [Bug 106157] [Tracker] Mesa 18.1 release tracker

https://bugs.freedesktop.org/show_bug.cgi?id=106157 Bug ID: 106157 Summary: [Tracker] Mesa 18.1 release tracker Product: Mesa Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal

[Mesa-dev] [Bug 106157] [Tracker] Mesa 18.1 release tracker

https://bugs.freedesktop.org/show_bug.cgi?id=106157 Dylan Baker changed: What|Removed |Added CC||baker.dyla...@gmail.com -- You are recei

Re: [Mesa-dev] [PATCH v3 3/5] i965: perf: read slice/unslice frequencies from OA reports

On Tuesday, April 17, 2018 5:24:56 PM PDT Lionel Landwerlin wrote: > v2: Add comment breaking down where the frequency values come from (Ken) > > Signed-off-by: Lionel Landwerlin > --- > .../drivers/dri/i965/brw_performance_query.c | 49 +++ > .../drivers/dri/i965/brw_performanc

[Mesa-dev] [Bug 106156] [TRACKER] Mesa 18.2 feature tracker

https://bugs.freedesktop.org/show_bug.cgi?id=106156 Dylan Baker changed: What|Removed |Added CC||ago...@igalia.com, |

[Mesa-dev] [Bug 106156] [TRACKER] Mesa 18.2 feature tracker

https://bugs.freedesktop.org/show_bug.cgi?id=106156 Bug ID: 106156 Summary: [TRACKER] Mesa 18.2 feature tracker Product: Mesa Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal

[Mesa-dev] [Bug 105928] [TRACKER] Mesa 18.1 feature tracker

https://bugs.freedesktop.org/show_bug.cgi?id=105928 Dylan Baker changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

Re: [Mesa-dev] [PATCH] autotools, travis: update libva required version

On Fri, 2018-04-20 at 10:25 -0700, Dylan Baker wrote: > Quoting Juan A. Suarez Romero (2018-04-20 07:36:41) > > Commit fa328456e8f29 added VP9 config support, but this needs a newer > > libva version, 1.7.0 or above. > > > > Fixes: fa328456e8f ("st/va: add VP9 config to enable profile2") > > --- >

Re: [Mesa-dev] [PATCH v3 5/9] i965/wm_surface_state: Use the clear address if it's non-zero

Looks like this is the last patch in the series that is only cleaning up the mess I left behind by adding the clear color bo. Thanks for that. Reviewed-by: Rafael Antognolli On Wed, Apr 11, 2018 at 01:42:22PM -0700, Nanley Chery wrote: > We want to add and use a getter that turns off the indirec

Re: [Mesa-dev] [PATCH] autotools, travis: update libva required version

Quoting Juan A. Suarez Romero (2018-04-20 07:36:41) > Commit fa328456e8f29 added VP9 config support, but this needs a newer > libva version, 1.7.0 or above. > > Fixes: fa328456e8f ("st/va: add VP9 config to enable profile2") > --- > .travis.yml | 2 +- > configure.ac | 2 +- > 2 files changed, 2

Re: [Mesa-dev] [PATCH v2 06/12] glcpp/tests: Convert shell scripts to a python script

Quoting Juan A. Suarez Romero (2018-04-20 10:18:03) > On Thu, 2018-04-05 at 14:51 -0700, Dylan Baker wrote: > > This ports glcpp-test.sh and glcpp-test-cr-lf.sh to a python script that > > accepts arguments for each line ending type. This should allow for > > better reporting to users. > > > > Sig

[Mesa-dev] [PATCH] compiler/glsl: close fd's in glcpp_test.py

I would have thought falling out of scope would allow the gc to collect these, but apparently it doesn't, and this hits an fd limit on macos. CC: v...@freedesktop.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106133 Fixes: db8cd8e36771eed98eb638fd0593c978c3da52a9 ("glcpp/tests:

Re: [Mesa-dev] [PATCH v3 4/9] i965: Add and use a single miptree aux_buf field

On Wed, Apr 11, 2018 at 01:42:21PM -0700, Nanley Chery wrote: > We want to add and use a function that accesses the auxiliary buffer's > clear_color_bo and doesn't care if it has an MCS or HiZ buffer > specifically. > --- > src/mesa/drivers/dri/i965/brw_blorp.c | 4 +- > src/mesa/drivers

Re: [Mesa-dev] [PATCH v2 06/12] glcpp/tests: Convert shell scripts to a python script

On Thu, 2018-04-05 at 14:51 -0700, Dylan Baker wrote: > This ports glcpp-test.sh and glcpp-test-cr-lf.sh to a python script that > accepts arguments for each line ending type. This should allow for > better reporting to users. > > Signed-off-by: Dylan Baker Hi! I think this patch is causing fa

Re: [Mesa-dev] [PATCH v3 3/9] i965: Add and use a getter for the miptree aux buffer

Nice, I was planning to do something like this later but didn't want to include many more changes on my ongoing series. This looks great, just a little comment below. On Wed, Apr 11, 2018 at 01:42:20PM -0700, Nanley Chery wrote: > Make the next patch easier to read by eliminating most of the would

Re: [Mesa-dev] [PATCH v3 2/9] i965/miptree: Delete an unused function

Patches 1 and 2 are Reviewed-by: Rafael Antognolli On Wed, Apr 11, 2018 at 01:42:19PM -0700, Nanley Chery wrote: > We're going to combine ::mcs_buf and ::hiz_buf in later commits. Once > that happens, this function no longer make sense. > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 13

[Mesa-dev] [Bug 106151] [amdgpu][vulkan] GPU hang (Vega 56) while running game (Rise of the Tomb Raider)

https://bugs.freedesktop.org/show_bug.cgi?id=106151 --- Comment #2 from Samuel Pitoiset --- FYI, I have pushed the fix https://cgit.freedesktop.org/mesa/mesa/commit/?id=8f13975713a7a7b8d625e3561a7fc9ce202ac64b -- You are receiving this mail because: You are the QA Contact for the bug. You are t

Re: [Mesa-dev] [PATCH] radv/winsys: allow to submit up to 4 IBs for chips without chaining

On 04/20/2018 03:30 PM, Grazvydas Ignotas wrote: On Fri, Apr 20, 2018 at 3:21 PM, Samuel Pitoiset wrote: The SI family doesn't support chaining which means the maximum size in dwords per CS is limited. When that limit was reached we failed to submit the CS and the application crashed. This p

Re: [Mesa-dev] [PATCH v3] mesa: GL_EXT_texture_norm16 extension plumbing

On Fri, Apr 20, 2018 at 11:33 AM, Tapani Pälli wrote: > Patch enables use of short and unsigned short data for texture uploads, > rendering and reading of framebuffers within the restrictions specified > in GL_EXT_texture_norm16 spec. > > Patch also enables those 16bit format layout qualifiers lis

[Mesa-dev] [Bug 105775] SI reaches the maximum IB size in dwords and fail to submit

https://bugs.freedesktop.org/show_bug.cgi?id=105775 Samuel Pitoiset changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Mesa-dev] [PATCH] ac/nir: fix image dimension for subpass attachments

For subpass attachments we need one more coordinate with the sample index, so make them array types. This fixes a bunch of CTS fails with RADV. Fixes: 24fb3e6aa1 ("ac/nir: use ac_build_image_opcode for image intrinsics") Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_nir_to_llvm.c | 18 ++

[Mesa-dev] [Bug 106151] [amdgpu][vulkan] GPU hang (Vega 56) while running game (Rise of the Tomb Raider)

https://bugs.freedesktop.org/show_bug.cgi?id=106151 --- Comment #1 from Samuel Pitoiset --- Hi, Yeah, 24fb3e6aa166b3afe906eb2845077766075189ed is a broken commit which might hang your GPU. You are lucky because I have just wrote a fix for that issue. :) Can you try https://cgit.freedesktop.org/

Re: [Mesa-dev] [PATCH v2 0/2] Android backtrace support

Series LGTM, I'll push it in. Reviewed-by: Tapani Pälli On 16.04.2018 01:45, Stefan Schake wrote: v2 clarifies the Android special-case in u_debug_stack and collects tags. I have no commit rights, so if it is otherwise satisfactory, I'd ask that someone push the series. Thanks! This series ad

[Mesa-dev] [PATCH 1/4] intel/compiler: Silence unused parameter warnings in generate_foo methods

From: Ian Romanick Since all of the fs_generator::generate_foo methods take a fs_inst * as the first parameter, just remove the name to quiet the compiler. src/intel/compiler/brw_fs_generator.cpp: In member function ‘void fs_generator::generate_barrier(fs_inst*, brw_reg)’: src/intel/compiler/br

[Mesa-dev] [PATCH v3] mesa: GL_EXT_texture_norm16 extension plumbing

Patch enables use of short and unsigned short data for texture uploads, rendering and reading of framebuffers within the restrictions specified in GL_EXT_texture_norm16 spec. Patch also enables those 16bit format layout qualifiers listed in GL_NV_image_formats that depend on EXT_texture_norm16. v

[Mesa-dev] [Bug 106144] Max OpenGL window resolution

https://bugs.freedesktop.org/show_bug.cgi?id=106144 Roland Scheidegger changed: What|Removed |Added Severity|normal |enhancement --- Comment #2 from Ro

Re: [Mesa-dev] [PATCH v2] mesa: GL_EXT_texture_norm16 extension plumbing

On 19.04.2018 02:56, Ilia Mirkin wrote: On Wed, Apr 18, 2018 at 7:49 PM, Tapani Pälli wrote: Patch enables use of short and unsigned short data for texture uploads, rendering and reading of framebuffers within the restrictions specified in GL_EXT_texture_norm16 spec. Patch also enables those

[Mesa-dev] [PATCH v2] travis: update libva required version

Commit fa328456e8f29 added VP9 config support, but this needs a newer libva version, 1.7.0 or above. Fixes: fa328456e8f ("st/va: add VP9 config to enable profile2") --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 45c5b80cbac..e0d

[Mesa-dev] [Bug 106151] [amdgpu][vulkan] GPU hang (Vega 56) while running game (Rise of the Tomb Raider)

https://bugs.freedesktop.org/show_bug.cgi?id=106151 Bug ID: 106151 Summary: [amdgpu][vulkan] GPU hang (Vega 56) while running game (Rise of the Tomb Raider) Product: Mesa Version: git Hardware: x86-64 (AMD64)

Re: [Mesa-dev] [PATCH] radeonsi/gfx9: fix a hang with an empty first IB

On Tue, 2018-04-17 at 15:54 -0400, Marek Olšák wrote: > From: Marek Olšák > > This packet causes the no-op IB detection to fail, so the IB is always > submitted. Also fix the no-op IB detection by moving the begin call. > > Cc: 18.0 This patch does not apply cleanly in 18.0, so I've resolved

[Mesa-dev] [PATCH] ac/nir: handle nir_intrinsic_load_first_vertex like base_vertex

This fixes a ton of CTS crashes. Fixes: c366f422f0 ("nir: Offset vertex_id by first_vertex instead of base_vertex") Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_nir_to_llvm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/am

[Mesa-dev] [PATCH] autotools, travis: update libva required version

Commit fa328456e8f29 added VP9 config support, but this needs a newer libva version, 1.7.0 or above. Fixes: fa328456e8f ("st/va: add VP9 config to enable profile2") --- .travis.yml | 2 +- configure.ac | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.travis.yml b/.travis.y

[Mesa-dev] [PATCH 4/4] intel/compiler: Add scheduler deps for instructions that implicitly read g0

From: Ian Romanick Otherwise the scheduler can move the writes after the reads. Signed-off-by: Ian Romanick Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95012 Cc: Mark Janes Cc: Clayton A Craft --- I'd really like to have this run on the CI with the tests from bugzill #95012 re-enab

[Mesa-dev] [PATCH 3/4] intel/compiler: Silence unused parameter warnings in empty vec4_instruction_scheduler methods

From: Ian Romanick src/intel/compiler/brw_schedule_instructions.cpp: In member function ‘virtual void vec4_instruction_scheduler::count_reads_remaining(backend_instruction*)’: src/intel/compiler/brw_schedule_instructions.cpp:764:72: warning: unused parameter ‘be’ [-Wunused-parameter] vec4_inst

[Mesa-dev] [PATCH 2/4] intel/compiler: Silence unused parameter warning in compile_cs_to_nir

From: Ian Romanick src/intel/compiler/brw_fs.cpp: In function ‘nir_shader* compile_cs_to_nir(const brw_compiler*, void*, const brw_cs_prog_key*, brw_cs_prog_data*, const nir_shader*, unsigned int)’: src/intel/compiler/brw_fs.cpp:7205:44: warning: unused parameter ‘prog_data’ [-Wunused-paramete

Re: [Mesa-dev] [PATCH] radv/winsys: allow to submit up to 4 IBs for chips without chaining

On Fri, Apr 20, 2018 at 3:21 PM, Samuel Pitoiset wrote: > The SI family doesn't support chaining which means the maximum > size in dwords per CS is limited. When that limit was reached > we failed to submit the CS and the application crashed. > > This patch allows to submit up to 4 IBs which is cu

Re: [Mesa-dev] [PATCH] radv/winsys: allow to submit up to 4 IBs for chips without chaining

Reviewed-by: Bas Nieuwenhuizen On Fri, Apr 20, 2018 at 2:21 PM, Samuel Pitoiset wrote: > The SI family doesn't support chaining which means the maximum > size in dwords per CS is limited. When that limit was reached > we failed to submit the CS and the application crashed. > > This patch allows

Re: [Mesa-dev] [PATCH] travis: radv needs LLVM 4.0

This is: Reviewed-by: Andres Gomez On Thu, 2018-04-19 at 16:18 +0200, Juan A. Suarez Romero wrote: > This is a backport for 18.0 from 6ce400782c ("travis: radeonsi and radv > need LLVM 4.0") that fixes Travis build with meson + vulkan. > > CC: 18.0 > --- > .travis.yml | 4 ++-- > 1 file chang

[Mesa-dev] [PATCH 1/2] etnaviv: remove redundant include

Signed-off-by: Christian Gmeiner --- src/gallium/drivers/etnaviv/etnaviv_rs.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/gallium/drivers/etnaviv/etnaviv_rs.c b/src/gallium/drivers/etnaviv/etnaviv_rs.c index b8a3b12ae4..fc4f65dbee 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_rs.

Re: [Mesa-dev] [PATCH] egl/android: remove flink name support

On Fri, Apr 20, 2018 at 6:29 AM, Robert Foss wrote: > Hey Rob, > > This looks good to me. > Do you mind if I carry this patch my series to get it all pushed upstream at > once? No, not at all. Rob ___ mesa-dev mailing list mesa-dev@lists.freedesktop.or

[Mesa-dev] [PATCH 2/2] etnaviv: remove not needed includes

Signed-off-by: Christian Gmeiner --- src/gallium/drivers/etnaviv/etnaviv_translate.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/gallium/drivers/etnaviv/etnaviv_translate.h b/src/gallium/drivers/etnaviv/etnaviv_translate.h index 7c85f81a70..88ce107a92 100644 --- a/src/gallium/drive

[Mesa-dev] [Bug 105775] SI reaches the maximum IB size in dwords and fail to submit

https://bugs.freedesktop.org/show_bug.cgi?id=105775 --- Comment #23 from Samuel Pitoiset --- Here's the fix https://patchwork.freedesktop.org/patch/218066/ I have tested it using RADV_DEBUG=noibs with Dawn Of War III, that seems to work. -- You are receiving this mail because: You are the QA C

[Mesa-dev] [PATCH] radv/winsys: allow to submit up to 4 IBs for chips without chaining

The SI family doesn't support chaining which means the maximum size in dwords per CS is limited. When that limit was reached we failed to submit the CS and the application crashed. This patch allows to submit up to 4 IBs which is currently the limit, but recent amdgpu supports more than that. Ple

Re: [Mesa-dev] 16-bit comparisons in NIR

On 20.04.2018 10:21, Iago Toral wrote: Hi, while developing support for Vulkan shaderInt16 on Anvil I came across a feature of NIR that was a bit inconvenient: bools are always 32-bit by design, but the Intel hardware produces 16-bit bool results for 16- bit comparisons, so that creates a proble

Re: [Mesa-dev] [PATCH] egl/android: remove flink name support

Hey Rob, This looks good to me. Do you mind if I carry this patch my series to get it all pushed upstream at once? Rob. On 04/19/2018 11:09 PM, Rob Herring wrote: Maintaining both flink names and prime fd support which are provided by 2 different gralloc implementations is problematic becaus

[Mesa-dev] [PATCH] st/dri: Fix dangling pointer to a destroyed dri_drawable

If an EGLSurface is created, made current and destroyed, and then a second EGLSurface is created. Then the second malloc in driCreateNewDrawable may return the same pointer address the first surface's drawable had. Consequently, when dri_make_current later tries to determine if it should update the

[Mesa-dev] [Bug 106144] Max OpenGL window resolution

https://bugs.freedesktop.org/show_bug.cgi?id=106144 --- Comment #1 from Inad --- glxgears: /var/tmp/portage/media-libs/mesa-18.0.0/work/mesa-18.0.0/src/gallium/drivers/llvmpipe/lp_state_surface.c:57: llvmpipe_set_framebuffer_state: Assertion `fb->width <= LP_MAX_WIDTH' failed. -- You are receiv

[Mesa-dev] 16-bit comparisons in NIR

Hi, while developing support for Vulkan shaderInt16 on Anvil I came across a feature of NIR that was a bit inconvenient: bools are always 32-bit by design, but the Intel hardware produces 16-bit bool results for 16- bit comparisons, so that creates a problem that manifests like this: vec1 32 ssa_

Re: [Mesa-dev] [RFC] egl/android: Add DRM node probing and filtering

On 04/20/2018 09:38 AM, Tomasz Figa wrote: On Fri, Apr 20, 2018 at 4:17 PM Robert Foss wrote: On 04/20/2018 06:41 AM, Tomasz Figa wrote: Hi Rob, On Thu, Apr 19, 2018 at 1:03 AM Robert Foss wrote: This patch both adds support for probing & filtering DRM nodes and switches away from usi

[Mesa-dev] [Bug 106144] Max OpenGL window resolution

https://bugs.freedesktop.org/show_bug.cgi?id=106144 Bug ID: 106144 Summary: Max OpenGL window resolution Product: Mesa Version: 18.0 Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal

Re: [Mesa-dev] [RFC] egl/android: Add DRM node probing and filtering

On Fri, Apr 20, 2018 at 4:17 PM Robert Foss wrote: > On 04/20/2018 06:41 AM, Tomasz Figa wrote: > > Hi Rob, > > > > On Thu, Apr 19, 2018 at 1:03 AM Robert Foss > > wrote: > > > >> This patch both adds support for probing & filtering DRM nodes > >> and switches away from using the GRALLOC_MODUL

Re: [Mesa-dev] [PATCH 5/5] radeonsi/nir: fix crash in test involving the sample mask

On 12.04.2018 02:13, Timothy Arceri wrote: On 11/04/18 20:56, Nicolai Hähnle wrote: From: Nicolai Hähnle Please add to the commit message which test was fixed by this. Otherwise the change seems reasonable: I agree, unfortunately I couldn't find my notes on this anymore... Cheers, Nicolai

Re: [Mesa-dev] [PATCH 2/5] radeonsi: fix error paths of si_texture_transfer_map

On 12.04.2018 02:10, Timothy Arceri wrote: On 11/04/18 20:56, Nicolai Hähnle wrote: From: Nicolai Hähnle trans is zero-initialized, but trans->resource is setup immediately so needs to be dereferenced. ---   src/gallium/drivers/radeonsi/si_texture.c | 25 -   1 file

Re: [Mesa-dev] [RFC] egl/android: Add DRM node probing and filtering

On 04/20/2018 06:41 AM, Tomasz Figa wrote: Hi Rob, On Thu, Apr 19, 2018 at 1:03 AM Robert Foss wrote: This patch both adds support for probing & filtering DRM nodes and switches away from using the GRALLOC_MODULE_PERFORM_GET_DRM_FD gralloc call. Currently the filtering is based just on t

Re: [Mesa-dev] [PATCH 1/7] ac/surface: handle DCC subresource fast clear restriction on VI

On 18.04.2018 21:53, Marek Olšák wrote: On Wed, Apr 18, 2018 at 5:54 AM, Nicolai Hähnle > wrote: On 17.04.2018 02:41, Marek Olšák wrote: From: Marek Olšák mailto:marek.ol...@amd.com>> ---   src/amd/common/ac_surface.c | 14 +-