+ cs->failed = true;
+ cs->base.cdw = 0;
+ return;
+ }
+
+ /* Store the current one for submitting it later. */
+ cs->old_cs_buffers[cs->num_old_cs_buffers].cdw =
cs->base.cdw;
+ cs->old_cs_buffers[cs->num_old_cs_buffers].max_dw =
cs->base.max_dw;
+ cs->old_cs_buffers[cs->num_old_cs_buffers].buf =
cs->base.buf;
+ cs->num_old_cs_buffers++;
+
+ /* Reset the cs, it will be re-allocated below. */
cs->base.cdw = 0;
- return;
+ cs->base.buf = NULL;
+
+ /* Re-compute the number of dwords to allocate. */
+ ib_dws = MAX2(cs->base.cdw + min_size,
+ MIN2(cs->base.max_dw * 2, limit_dws));
+ if (ib_dws > limit_dws) {
+ fprintf(stderr, "amdgpu: Too high number of "
+ "dwords to allocate\n");
+ cs->failed = true;
+ return;
+ }
}
uint32_t *new_buf = realloc(cs->base.buf, ib_dws * 4);
@@ -400,6 +447,15 @@ static void radv_amdgpu_cs_reset(struct radeon_winsys_cs
*_cs)
cs->ib.ib_mc_address =
radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va;
cs->ib_size_ptr = &cs->ib.size;
cs->ib.size = 0;
+ } else {
+ for (unsigned i = 0; i < cs->num_old_cs_buffers; ++i) {
+ struct radeon_winsys_cs *rcs = &cs->old_cs_buffers[i];
+ free(rcs->buf);
+ }
+
+ free(cs->old_cs_buffers);
+ cs->old_cs_buffers = NULL;
+ cs->num_old_cs_buffers = 0;
}
}
@@ -550,7 +606,8 @@ static void radv_amdgpu_cs_execute_secondary(struct
radeon_winsys_cs *_parent,
static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
struct radeon_winsys_cs **cs_array,
unsigned count,
- struct radv_amdgpu_winsys_bo *extra_bo,
+ struct radv_amdgpu_winsys_bo
**extra_bo_array,
+ unsigned num_extra_bo,
struct radeon_winsys_cs *extra_cs,
const struct radv_winsys_bo_list
*radv_bo_list,
amdgpu_bo_list_handle *bo_list)
@@ -580,7 +637,7 @@ static int radv_amdgpu_create_bo_list(struct
radv_amdgpu_winsys *ws,
bo_list);
free(handles);
pthread_mutex_unlock(&ws->global_bo_list_lock);
- } else if (count == 1 && !extra_bo && !extra_cs && !radv_bo_list &&
+ } else if (count == 1 && !num_extra_bo && !extra_cs && !radv_bo_list &&
!radv_amdgpu_cs(cs_array[0])->num_virtual_buffers) {
struct radv_amdgpu_cs *cs = (struct
radv_amdgpu_cs*)cs_array[0];
if (cs->num_buffers == 0) {
@@ -590,8 +647,8 @@ static int radv_amdgpu_create_bo_list(struct
radv_amdgpu_winsys *ws,
r = amdgpu_bo_list_create(ws->dev, cs->num_buffers,
cs->handles,
cs->priorities, bo_list);
} else {
- unsigned total_buffer_count = !!extra_bo;
- unsigned unique_bo_count = !!extra_bo;
+ unsigned total_buffer_count = num_extra_bo;
+ unsigned unique_bo_count = num_extra_bo;
for (unsigned i = 0; i < count; ++i) {
struct radv_amdgpu_cs *cs = (struct
radv_amdgpu_cs*)cs_array[i];
total_buffer_count += cs->num_buffers;
@@ -619,9 +676,9 @@ static int radv_amdgpu_create_bo_list(struct
radv_amdgpu_winsys *ws,
return -ENOMEM;
}
- if (extra_bo) {
- handles[0] = extra_bo->bo;
- priorities[0] = 8;
+ for (unsigned i = 0; i < num_extra_bo; i++) {
+ handles[i] = extra_bo_array[i]->bo;
+ priorities[i] = 8;
}
for (unsigned i = 0; i < count + !!extra_cs; ++i) {
@@ -773,7 +830,7 @@ static int radv_amdgpu_winsys_cs_submit_chained(struct
radeon_winsys_ctx *_ctx,
}
}
- r = radv_amdgpu_create_bo_list(cs0->ws, cs_array, cs_count, NULL,
initial_preamble_cs,
+ r = radv_amdgpu_create_bo_list(cs0->ws, cs_array, cs_count, NULL, 0,
initial_preamble_cs,
radv_bo_list, &bo_list);
if (r) {
fprintf(stderr, "amdgpu: buffer list creation failed for the "
@@ -842,7 +899,7 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct
radeon_winsys_ctx *_ctx,
memset(&request, 0, sizeof(request));
- r = radv_amdgpu_create_bo_list(cs0->ws, &cs_array[i], cnt, NULL,
+ r = radv_amdgpu_create_bo_list(cs0->ws, &cs_array[i], cnt,
NULL, 0,
preamble_cs, radv_bo_list,
&bo_list);
if (r) {
fprintf(stderr, "amdgpu: buffer list creation failed "
@@ -923,68 +980,127 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct
radeon_winsys_ctx *_ctx,
assert(cs_count);
for (unsigned i = 0; i < cs_count;) {
- struct amdgpu_cs_ib_info ib = {0};
- struct radeon_winsys_bo *bo = NULL;
+ struct amdgpu_cs_ib_info ibs[AMDGPU_CS_MAX_IBS_PER_SUBMIT] =
{0};
+ unsigned number_of_ibs = 1;
+ struct radeon_winsys_bo *bos[AMDGPU_CS_MAX_IBS_PER_SUBMIT] =
{0};
struct radeon_winsys_cs *preamble_cs = i ?
continue_preamble_cs : initial_preamble_cs;
+ struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
uint32_t *ptr;
unsigned cnt = 0;
unsigned size = 0;
unsigned pad_words = 0;
- if (preamble_cs)
- size += preamble_cs->cdw;
- while (i + cnt < cs_count && 0xffff8 - size >=
radv_amdgpu_cs(cs_array[i + cnt])->base.cdw) {
- size += radv_amdgpu_cs(cs_array[i + cnt])->base.cdw;
- ++cnt;
- }
+ if (cs->num_old_cs_buffers > 0) {
+ /* Special path when the maximum size in dwords has
+ * been reached because we need to handle more than one
+ * IB per submit.
+ */
+ unsigned new_cs_count = cs->num_old_cs_buffers + 1;
+ struct radeon_winsys_cs *new_cs_array[4];
