Re: [Mesa-dev] [PATCH] gallium/radeon: fix r600g build if LLVM is disabled

On 08.08.2015 21:05, Marek Olšák wrote: > From: Marek Olšák > > MESA_LLVM_VERSION_PATCH is undefined. Reviewed-by: Michel Dänzer -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer __

Re: [Mesa-dev] [PATCH] radeonsi: add new OLAND pci id

On 11.08.2015 04:36, Alex Deucher wrote: > Signed-off-by: Alex Deucher > Cc: mesa-sta...@lists.freedesktop.org Reviewed-by: Michel Dänzer -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer __

Re: [Mesa-dev] [PATCH] st/mesa: Map packed gallium formats to packed mesa formats.

On 10.08.2015 21:48, Oded Gabbay wrote: > > I believe the deeper problem is from the fact we move from gallium > format name x8y8z8w8, which doesn't take into account platform > endianness, to mesa format name, which does take platform endianness > into account (using the swizzle). That should on

Re: [Mesa-dev] [Intel-gfx] [PATCH libdrm v3 1/2] intel: Add EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag

On Fri, 2015-08-07 at 12:36 +0100, Michel Thierry wrote: > Hi Michał, > > Ben suggested having the set/clear in emit reloc as this is the only > place mesa cares about these wa. > > But I see your point, this will be used not only by mesa, so we > should > have something that is good for all t

Re: [Mesa-dev] [Intel-gfx] [PATCH mesa v3] i965/gen8+: bo in state base address must be in 32-bit address range

Hi, Thanks for the comments, On 8/7/2015 11:46 PM, Kristian Høgsberg wrote: On Fri, Aug 7, 2015 at 2:45 AM, Michel Thierry wrote: Gen8+ supports 48-bit virtual addresses, but some objects must always be allocated inside the 32-bit address range. In specific, any resource used with flat/heapl

Re: [Mesa-dev] [PATCH 4/4] r600g: use a bitfield to track dirty atoms

On Mon, Aug 10, 2015 at 1:47 PM, Marek Olšák wrote: > Please never use "long" in Mesa. It only has 32 bits on 32-bit > systems. uint64_t is generally used for all unsigned 64-bit variables > and "llu" or "ull" is the number suffix. Also, the 64-bit ctz is ctzll > and a proper HAVE macro should be

Re: [Mesa-dev] [PATCH] mesa: add NV_read_{depth, stencil, depth_stencil} extensions

Reviewed-by: Marek Olšák Marek On Mon, Aug 10, 2015 at 11:28 PM, Rob Clark wrote: > From: Rob Clark > > These extensions allow reading depth/stencil for GLES contexts, which is > useful for tools like apitrace. > > Signed-off-by: Rob Clark > --- > v2: rework format/type checking > > src/mesa

Re: [Mesa-dev] [PATCH 2/6] i965: Fix comments about blit constraints

On Mon, Aug 10, 2015 at 4:15 PM, Ben Widawsky wrote: > > The spec does say that the blitter is capable of transferring 64k scanlines > in a > single blit operation. Perhaps this was true, or is still true on some > operations, but for all commands that we use, we are restricted to 16b signed: > >

Re: [Mesa-dev] [PATCH 1/6] i965: Kill y_or_x variable in miptree tiling selection

On Mon, Aug 10, 2015 at 4:15 PM, Ben Widawsky wrote: > NOTE: The commit message is retained for posterity, however there were some > changes in the code since the patch was originally written that may make > the old > commit message false. Starting with v4 is actually much simpler than the > orig

Re: [Mesa-dev] [PATCH] radeonsi: add new OLAND pci id

Reviewed-by: Edward O'Callaghan -- Edward O'Callaghan edward.ocallag...@koparo.com On Tue, Aug 11, 2015, at 05:36 AM, Alex Deucher wrote: > Signed-off-by: Alex Deucher > Cc: mesa-sta...@lists.freedesktop.org > --- > include/pci_ids/radeonsi_pci_ids.h | 1 + > 1 file changed, 1 insertion(+

Re: [Mesa-dev] [Intel-gfx] [PATCH mesa v3] i965/gen8+: bo in state base address must be in 32-bit address range

On Mon, Aug 10, 2015 at 2:21 AM, Michel Thierry wrote: > Hi, > > Thanks for the comments, > > On 8/7/2015 11:46 PM, Kristian Høgsberg wrote: >> >> On Fri, Aug 7, 2015 at 2:45 AM, Michel Thierry >> wrote: >>> >>> Gen8+ supports 48-bit virtual addresses, but some objects must always be >>> allocate

[Mesa-dev] [PATCH 6/6] i965: Allow Y-tiled allocations for large surfaces

This patch will use a new calculation to determine if a surface can be blitted from or to. Previously, the "total_height" member was used. Total_height in the case of 2d, 3d, and cube map arrays is the height of each slice/layer/face. Since the GL map APIS only ever deal with a slice at a time howe

[Mesa-dev] [PATCH 2/6] i965: Fix comments about blit constraints

The spec does say that the blitter is capable of transferring 64k scanlines in a single blit operation. Perhaps this was true, or is still true on some operations, but for all commands that we use, we are restricted to 16b signed: For example, from the XY_SRC_COPY_CHROMA_BLT definition: > Destinat

[Mesa-dev] [PATCH 5/6] i965: Attempt to blit for larger textures

The blit engine is limited to 32Kx32K transfer. In cases where we have to fall back to the blitter, and when trying to blit a slice of a 2d texture array, or face of a cube map, we don't need to transfer the entire texture. I doubt this patch will get exercised at this point since we'll always all

[Mesa-dev] [PATCH 4/6] i965: Extract blit height max

The blit engine in GEN hardware has constraints. These constraints are a function of tile parameters as well as height. The current code is very dumb in terms of determine max blit parameters. Since we'll be expanding on it, having the abstraction makes things easier. Note that this doesn't change

[Mesa-dev] [PATCH 0/6] [REPOST] More blits

This is a repost of a patch series from several months ago. The original motivation was to allow blitting (and therefore, usage of Y-tiling on more buffers). The original code for handling this stuff was horrendous. This patch series improved our internal Terrain benchmark by a phenomenal amount.

[Mesa-dev] [PATCH 1/6] i965: Kill y_or_x variable in miptree tiling selection

NOTE: The commit message is retained for posterity, however there were some changes in the code since the patch was originally written that may make the old commit message false. Starting with v4 is actually much simpler than the original change. This patch is needed to help keep some of the churn

[Mesa-dev] [PATCH 3/6] i965: Create and use #defines for blitter constraints

v2: Rebased. Some manual intervention required. Signed-off-by: Ben Widawsky --- src/mesa/drivers/dri/i965/brw_tex_layout.c| 6 -- src/mesa/drivers/dri/i965/intel_blit.c| 10 ++ src/mesa/drivers/dri/i965/intel_blit.h| 3 +++ src/mesa/drivers/dri/i965/intel_copy_i

Re: [Mesa-dev] [PATCH 1/2] i965: Add SKL support to brw_miptree_get_horizontal_slice_pitch().

On Sat, Aug 8, 2015 at 2:58 AM, Francisco Jerez wrote: > Jason Ekstrand writes: > >> I'm not a huge fan of this patch. Really, given how complicated 3-D >> textures are on SKL, there really is no sensible horizontal slice >> pitch. We could return 0 as an "invalid value" but I think I'd rather

[Mesa-dev] [PATCH] nir: Add a value range propagation pass

Add section to pessimize on branching on undef Incorporate some of Connors feedback Incorporate some of Matt's feedback Rework set_float_range API Reworked to not have a separate initialization run Handle loops better Squash a bug where we where adding ourself as user instead of the user Special c

Re: [Mesa-dev] [PATCH 06/13] mesa: Replace sampler object locks with atomic inc/dec.

On Mon, 2015-08-10 at 09:16 -0700, Matt Turner wrote: > On Fri, Aug 7, 2015 at 10:09 AM, Ian Romanick wrote: > > I know we've talked about this about 100 times, but something in the > > back of my mind tells me that we have a pre-existing race. What happens > > if the p_atomic_dec_zero happens on

Re: [Mesa-dev] [PATCH 1/2] retrace: support depth/stencil attachment for gles

On Mon, Aug 10, 2015 at 2:36 PM, Rob Clark wrote: > oh, and these two patches are for apitrace.. guess I should have put > something in the subject line to make that more clear. No idea if > this is the right place to send apitrace patches.. It's not. There's an apitrace mailing list: apitr...@l

Re: [Mesa-dev] [PATCH] mesa: add NV_read_{depth, stencil, depth_stencil} extensions

On Mon, Aug 10, 2015 at 5:37 PM, Ilia Mirkin wrote: > On Mon, Aug 10, 2015 at 5:28 PM, Rob Clark wrote: >> From: Rob Clark >> >> These extensions allow reading depth/stencil for GLES contexts, which is >> useful for tools like apitrace. >> >> Signed-off-by: Rob Clark >> --- >> v2: rework format

Re: [Mesa-dev] [PATCH] mesa: add NV_read_{depth, stencil, depth_stencil} extensions

On Mon, Aug 10, 2015 at 5:28 PM, Rob Clark wrote: > From: Rob Clark > > These extensions allow reading depth/stencil for GLES contexts, which is > useful for tools like apitrace. > > Signed-off-by: Rob Clark > --- > v2: rework format/type checking > > src/mesa/main/extensions.c | 3 +++ > src/

Re: [Mesa-dev] [PATCH 1/2] retrace: support depth/stencil attachment for gles

oh, and these two patches are for apitrace.. guess I should have put something in the subject line to make that more clear. No idea if this is the right place to send apitrace patches.. BR, -R On Mon, Aug 10, 2015 at 5:35 PM, Rob Clark wrote: > If we have the NV_read_depth_stencil extension, we

[Mesa-dev] [PATCH 1/2] retrace: support depth/stencil attachment for gles

If we have the NV_read_depth_stencil extension, we can actually read depth/stencil. Takes a bit of gymnastics to actually figure out that it is a depth/stencil buffer in the first place. TODO: this still seems to fall over w/ z24_s8, somehow ends up attempting to glReadPixels() with GL_FLOAT type

[Mesa-dev] [PATCH 2/2] retrace: use GREMEDY_string_marker to emit call no's

If the extension is present, use it to log call numbers for draw commands. Signed-off-by: Rob Clark --- retrace/glretrace.hpp | 2 ++ retrace/glretrace_main.cpp | 15 +++ retrace/retrace.hpp| 2 ++ retrace/retrace_main.cpp | 4 4 files changed, 23 insertions(+)

[Mesa-dev] [PATCH] mesa: add NV_read_{depth, stencil, depth_stencil} extensions

From: Rob Clark These extensions allow reading depth/stencil for GLES contexts, which is useful for tools like apitrace. Signed-off-by: Rob Clark --- v2: rework format/type checking src/mesa/main/extensions.c | 3 +++ src/mesa/main/readpix.c| 48 +-

Re: [Mesa-dev] [PATCH] i965/gen9: Don't use fast copy blit in case of non power of 2 cpp

On Mon, Aug 10, 2015 at 11:17 AM, Anuj Phogat wrote: > Many piglit tests (if using fast copy blit in Mesa) failed earlier > because I missed adding this condition. Fast copy blit is currently > enabled for use only with Yf/Ys tiling. > > Signed-off-by: Anuj Phogat > --- > src/mesa/drivers/dri/i

Re: [Mesa-dev] [PATCH] mesa: add NV_read_{depth, stencil, depth_stencil} extensions

On Mon, Aug 10, 2015 at 3:28 PM, Marek Olšák wrote: > On Mon, Aug 10, 2015 at 9:15 PM, Rob Clark wrote: >> On Mon, Aug 10, 2015 at 12:54 PM, Marek Olšák wrote: >>> On Mon, Aug 10, 2015 at 1:02 PM, Rob Clark wrote: From: Rob Clark These extensions allow reading depth/stencil for

[Mesa-dev] [PATCH] radeonsi: add new OLAND pci id

Signed-off-by: Alex Deucher Cc: mesa-sta...@lists.freedesktop.org --- include/pci_ids/radeonsi_pci_ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index c01ee20..52eada1 100644 --- a/include/pci_ids/radeonsi_pci_id

Re: [Mesa-dev] [PATCH] mesa: add NV_read_{depth, stencil, depth_stencil} extensions

On Mon, Aug 10, 2015 at 9:15 PM, Rob Clark wrote: > On Mon, Aug 10, 2015 at 12:54 PM, Marek Olšák wrote: >> On Mon, Aug 10, 2015 at 1:02 PM, Rob Clark wrote: >>> From: Rob Clark >>> >>> These extensions allow reading depth/stencil for GLES contexts, which is >>> useful for tools like apitrace.

Re: [Mesa-dev] [PATCH 2/5] i965/fs: Lower 32x32 bit multiplication on BXT.

On Mon, Aug 10, 2015 at 12:01 PM, Neil Roberts wrote: > Are you sure this patch is necessary? The documentation for the multiply > instruction on BDW+ says: > > SourceType :*D > DestinationType : *D > Project : EXCLUDE(CHV) > > This to me implies that it should work on BXT because

Re: [Mesa-dev] [PATCH] mesa: add NV_read_{depth, stencil, depth_stencil} extensions

On Mon, Aug 10, 2015 at 12:54 PM, Marek Olšák wrote: > On Mon, Aug 10, 2015 at 1:02 PM, Rob Clark wrote: >> From: Rob Clark >> >> These extensions allow reading depth/stencil for GLES contexts, which is >> useful for tools like apitrace. >> >> Signed-off-by: Rob Clark >> --- >> I have a patch,

Re: [Mesa-dev] [PATCH] i965/shader: Don't use OptimizeForAOS for NIR vec4 vertex shaders

On 08/07/2015 11:22 PM, Jason Ekstrand wrote: > Shader-db results for vec4 programs using NIR on HSW: > >total instructions in shared programs: 1838157 -> 1828469 (-0.53%) >instructions in affected programs: 275978 -> 266290 (-3.51%) >helped:2827 >

[Mesa-dev] [PATCH] gallium/radeon: fix r600g build if LLVM is disabled

Tested-by: Benjamin Bellec On Sat, Aug 8, 2015, at 10:05 PM, Marek Olšák wrote: >* From: Marek Olšák > *> >* MESA_LLVM_VERSION_PATCH is undefined. *>* --- *>* src/gallium/drivers/radeon/r600_pipe_common.c | 9 + *>* 1 file changed,

Re: [Mesa-dev] [PATCH 0/5] Some register allocation improvements

On Mon, Aug 10, 2015 at 11:24 AM, Matt Turner wrote: > On Fri, Jul 31, 2015 at 10:05 AM, Jason Ekstrand wrote: >> The following 5 patches contain a few register allocation cleanups and >> performance improvements. Chris Wilson noticed that setting up register >> sets on i965 calls reralloc an ab

Re: [Mesa-dev] [PATCH 2/5] i965/fs: Lower 32x32 bit multiplication on BXT.

Are you sure this patch is necessary? The documentation for the multiply instruction on BDW+ says: SourceType :*D DestinationType : *D Project : EXCLUDE(CHV) This to me implies that it should work on BXT because it doesn't say EXCLUDE(BXT). I made a little test case

Re: [Mesa-dev] [PATCH 07/70] i965: Combine the multiple pipelined register detection into one round-trip

On Friday, August 07, 2015 09:13:11 PM Chris Wilson wrote: > Combining the multiple access checks into a few batches and a single > serialising read can reduce detection times from around 100us to 70us on > a fast Haswell system. > > Signed-off-by: Chris Wilson > Cc: Kenneth Graunke > --- > src

Re: [Mesa-dev] [PATCH 2/2] i965/fs: Make resolve_source_modifiers consistent with the vec4 version

On Mon, Aug 10, 2015 at 11:53 AM, Jason Ekstrand wrote: > --- > src/mesa/drivers/dri/i965/brw_fs.cpp | 15 --- > src/mesa/drivers/dri/i965/brw_fs.h | 2 +- > src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 14 +++--- > 3 files changed, 16 insertions(+), 15 deletions(-) >

Re: [Mesa-dev] [PATCH 1/2] i965/vec4_visitor: Make some function arguments const references

On Mon, Aug 10, 2015 at 11:53 AM, Jason Ekstrand wrote: > --- > src/mesa/drivers/dri/i965/brw_vec4.h | 4 ++-- > src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h > b/src/mes

[Mesa-dev] [PATCH 2/2] i965/fs: Make resolve_source_modifiers consistent with the vec4 version

--- src/mesa/drivers/dri/i965/brw_fs.cpp | 15 --- src/mesa/drivers/dri/i965/brw_fs.h | 2 +- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 14 +++--- 3 files changed, 16 insertions(+), 15 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drive

[Mesa-dev] [PATCH 1/2] i965/vec4_visitor: Make some function arguments const references

--- src/mesa/drivers/dri/i965/brw_vec4.h | 4 ++-- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h index 0c13d43..24bf354 100644 --- a/src/

Re: [Mesa-dev] [PATCH] i965: Don't check for draw-time errors that cannot occur in core profile

On Mon, Aug 10, 2015 at 10:12 AM, Ian Romanick wrote: > From: Ian Romanick > > On many CPU-limited applications, this is *the* hot path. The idea is > to generate per-API versions of brw_draw_prims that elide some checks. > This patch removes render-mode and "is everything in VBOs" checks from >

Re: [Mesa-dev] [PATCH 4/5] i965/vec4_nir: Do boolean source modifier resolves on BDW+

On Mon, Aug 10, 2015 at 11:37 AM, Jason Ekstrand wrote: > On Mon, Aug 10, 2015 at 11:30 AM, Matt Turner wrote: >> On Mon, Aug 10, 2015 at 11:19 AM, Jason Ekstrand >> wrote: >>> On Mon, Aug 10, 2015 at 11:16 AM, Matt Turner wrote: On Mon, Aug 3, 2015 at 5:22 PM, Jason Ekstrand wrote

Re: [Mesa-dev] [PATCH 4/5] i965/vec4_nir: Do boolean source modifier resolves on BDW+

On Mon, Aug 10, 2015 at 11:30 AM, Matt Turner wrote: > On Mon, Aug 10, 2015 at 11:19 AM, Jason Ekstrand wrote: >> On Mon, Aug 10, 2015 at 11:16 AM, Matt Turner wrote: >>> On Mon, Aug 3, 2015 at 5:22 PM, Jason Ekstrand wrote: On BDW+, the negation source modifier on NOT, AND, OR, and XOR, i

[Mesa-dev] [PATCH 1/2] r600, compute: refactor 1st arg of evergreen_set_rat

--- src/gallium/drivers/r600/evergreen_compute.c | 21 + 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c index d89e3de..8b27a66 100644 --- a/src/gallium/drivers/r600/ever

Re: [Mesa-dev] [PATCHv2 07/14] i965: Implement surface state set-up for shader images.

On Sat, Aug 8, 2015 at 4:04 AM, Francisco Jerez wrote: > Jason Ekstrand writes: > >> On Wed, May 13, 2015 at 9:43 AM, Francisco Jerez >> wrote: >>> v2: Add SKL support. >>> --- >>> src/mesa/drivers/dri/i965/brw_context.h | 2 + >>> src/mesa/drivers/dri/i965/brw_surface_formats.c |

[Mesa-dev] [PATCH 2/2] r600, compute: setup RATs for write-only images

--- src/gallium/drivers/r600/evergreen_compute.c | 101 --- src/gallium/drivers/r600/evergreen_state.c | 44 +++- src/gallium/drivers/r600/r600_pipe.h | 4 +- src/gallium/drivers/radeon/r600_texture.c| 1 + 4 files changed, 109 insertions(+), 41 d

[Mesa-dev] [PATCH 2/2] clover: recognize sampler kernel arguments

--- src/gallium/state_trackers/clover/llvm/invocation.cpp | 9 + 1 file changed, 9 insertions(+) diff --git a/src/gallium/state_trackers/clover/llvm/invocation.cpp b/src/gallium/state_trackers/clover/llvm/invocation.cpp index 86859af..50c4557 100644 --- a/src/gallium/state_trackers/clove

[Mesa-dev] [PATCH] r600, compute: setup compute sampler states and views

--- src/gallium/drivers/r600/evergreen_compute.c | 25 ++ src/gallium/drivers/r600/evergreen_state.c | 30 -- src/gallium/drivers/r600/evergreend.h| 5 + src/gallium/drivers/r600/r600_pipe.h | 7 +- src/gallium/drivers/r600/r6

Re: [Mesa-dev] [PATCH v2] glsl: avoid compiler's segfault when processing operators with void arguments

Should this patch be cc'd to stable branches? Without it, the compiler crashes on invalid inputs, instead of generating an error. This patch applies cleanly to 10.5 and 10.6. -Mark Renaud Gaubert writes: > This is done by returning an rvalue of type void in the > ast_function_expression::hi

[Mesa-dev] [PATCH 1/2] clover: upload sample bitfield to kernel

--- src/gallium/state_trackers/clover/core/kernel.cpp | 7 +++ src/gallium/state_trackers/clover/core/sampler.cpp | 12 src/gallium/state_trackers/clover/core/sampler.hpp | 1 + 3 files changed, 20 insertions(+) diff --git a/src/gallium/state_trackers/clover/core/kernel.cpp b

Re: [Mesa-dev] [PATCH 4/5] i965/vec4_nir: Do boolean source modifier resolves on BDW+

On Mon, Aug 10, 2015 at 11:19 AM, Jason Ekstrand wrote: > On Mon, Aug 10, 2015 at 11:16 AM, Matt Turner wrote: >> On Mon, Aug 3, 2015 at 5:22 PM, Jason Ekstrand wrote: >>> On BDW+, the negation source modifier on NOT, AND, OR, and XOR, is actually >>> a boolean negate and not an integer negate.

Re: [Mesa-dev] [PATCH 5/5] i965/fs: Don't do redundant RA setup on IVB+

On Fri, Jul 31, 2015 at 10:05 AM, Jason Ekstrand wrote: > --- > src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 9 + > 1 file changed, 9 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp > b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp > index 211f

Re: [Mesa-dev] [PATCH 0/5] Some register allocation improvements

On Fri, Jul 31, 2015 at 10:05 AM, Jason Ekstrand wrote: > The following 5 patches contain a few register allocation cleanups and > performance improvements. Chris Wilson noticed that setting up register > sets on i965 calls reralloc an absurd number of times. I did a little > hacking and found o

Re: [Mesa-dev] [PATCH 4/5] i965/vec4_nir: Do boolean source modifier resolves on BDW+

On Mon, Aug 10, 2015 at 11:16 AM, Matt Turner wrote: > On Mon, Aug 3, 2015 at 5:22 PM, Jason Ekstrand wrote: >> On BDW+, the negation source modifier on NOT, AND, OR, and XOR, is actually >> a boolean negate and not an integer negate. However, NIR's soruce >> modifiers are the integer version.

[Mesa-dev] [PATCH] i965/gen9: Add a condition for starting pixel in fast copy blit

This condition restricts the use of fast copy blit to cases where starting pixel of src and dst is oword (16 byte) aligned. Many piglit tests (if using fast copy blit in Mesa) failed earlier because I missed adding this condition.Fast copy blit is currently enabled for use only with Yf/Ys tiling.

Re: [Mesa-dev] [PATCH 0/5] i965/vec4_nir: Various fixes for ILK- and BDW+

On Mon, Aug 3, 2015 at 5:22 PM, Jason Ekstrand wrote: > This is a quick little series that fixes a bunch of piglit regressions with > vec4 NIR on ILK- and BDW+. With this series, vec4 NIR has (I think) zero > regressions versus non-NIR on all intel platforms. I haven't yet tested > NIR with vec4

[Mesa-dev] [Bug 91591] rounding.h:102:2: error: #error "Unsupported or undefined LONG_BIT"

https://bugs.freedesktop.org/show_bug.cgi?id=91591 --- Comment #14 from Jose Fonseca --- Comment on attachment 117618 --> https://bugs.freedesktop.org/attachment.cgi?id=117618 patch Review of attachment 117618: - Looks great. Re

Re: [Mesa-dev] [PATCH 12/70] i965: Rename intel_batchbuffer to brw_batch

On Mon, Aug 10, 2015 at 5:49 AM, Martin Peres wrote: > On 10/08/15 15:45, Chris Wilson wrote: >> >> On Mon, Aug 10, 2015 at 03:37:24PM +0300, Martin Peres wrote: >>> >>> 10-12 are: >>> >>> Reviewed-by: Martin Peres >> >> One thing to consider, do we want to do a s/typedef/struct brw_batch/ >> cle

[Mesa-dev] [PATCH] i965/gen9: Don't use fast copy blit in case of non power of 2 cpp

Many piglit tests (if using fast copy blit in Mesa) failed earlier because I missed adding this condition. Fast copy blit is currently enabled for use only with Yf/Ys tiling. Signed-off-by: Anuj Phogat --- src/mesa/drivers/dri/i965/intel_blit.c | 6 -- 1 file changed, 4 insertions(+), 2 dele

Re: [Mesa-dev] [PATCH 4/5] i965/vec4_nir: Do boolean source modifier resolves on BDW+

On Mon, Aug 3, 2015 at 5:22 PM, Jason Ekstrand wrote: > On BDW+, the negation source modifier on NOT, AND, OR, and XOR, is actually > a boolean negate and not an integer negate. However, NIR's soruce > modifiers are the integer version. We have to resolve it with a MOV prior > to emitting the ac

Re: [Mesa-dev] [PATCH 3/5] i965/vec4-nir: Handle boolean resolvese on ILK-

On Mon, Aug 3, 2015 at 5:22 PM, Jason Ekstrand wrote: > The analysis code was already there and running, we just weren't doing > anything with the result of it yet. > --- > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 13 + > 1 file changed, 13 insertions(+) > > diff --git a/src/mesa/

Re: [Mesa-dev] [PATCH] mesa/format_utils: Add src_bits == dst_bits cases to [us]norm functions

On Mon, Aug 10, 2015 at 4:35 AM, Neil Roberts wrote: > Jason Ekstrand writes: > >> @@ -151,8 +153,10 @@ _mesa_snorm_to_snorm(int x, unsigned src_bits, unsigned >> dst_bits) >>return -MAX_INT(dst_bits); >> else if (src_bits < dst_bits) >>return EXTEND_NORMALIZED_INT(x, src_bit

Re: [Mesa-dev] [PATCH] i965/skl: Remove early platform support

On Mon, Aug 10, 2015 at 9:49 AM, Ben Widawsky wrote: > On Mon, Aug 10, 2015 at 09:09:41AM -0700, Jason Ekstrand wrote: >> On Aug 10, 2015 4:14 AM, "Neil Roberts" wrote: >> > >> > If we go with this patch perhaps it would be good to remove >> > supports_simd16_3src entirely from brw_device_info an

[Mesa-dev] [Bug 91591] rounding.h:102:2: error: #error "Unsupported or undefined LONG_BIT"

https://bugs.freedesktop.org/show_bug.cgi?id=91591 Matt Turner changed: What|Removed |Added Attachment #117615|0 |1 is obsolete|

[Mesa-dev] [Bug 91468] LLVM 3.8(svn): llvm changes llvm-config output again?

https://bugs.freedesktop.org/show_bug.cgi?id=91468 Krzysztof A. Sobiecki changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Mesa-dev] [Bug 91591] rounding.h:102:2: error: #error "Unsupported or undefined LONG_BIT"

https://bugs.freedesktop.org/show_bug.cgi?id=91591 --- Comment #12 from Jose Fonseca --- if __STDC_LIMIT_MACROS is indeed the problem, then it must be defined globally in configure.ac. Defining in rounding.h won't be effective if by any reason limits.h is included before rounding.h is (ie, the t

[Mesa-dev] [PATCH] i965: Don't check for draw-time errors that cannot occur in core profile

From: Ian Romanick On many CPU-limited applications, this is *the* hot path. The idea is to generate per-API versions of brw_draw_prims that elide some checks. This patch removes render-mode and "is everything in VBOs" checks from core-profile contexts. On my IVB laptop (which may have experien

Re: [Mesa-dev] [PATCH] st/dri: Use packed RGB formats

Reviewed-by: Marek Olšák Marek On Mon, Aug 10, 2015 at 11:44 AM, Michel Dänzer wrote: > From: Michel Dänzer > > Fixes Gallium based DRI drivers failing to load on big endian hosts > because they can't find any matching fbconfigs. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71789

Re: [Mesa-dev] [PATCH] mesa: add NV_read_{depth, stencil, depth_stencil} extensions

On Mon, Aug 10, 2015 at 1:02 PM, Rob Clark wrote: > From: Rob Clark > > These extensions allow reading depth/stencil for GLES contexts, which is > useful for tools like apitrace. > > Signed-off-by: Rob Clark > --- > I have a patch, which I will send out after some cleanup, that makes > apitrace

Re: [Mesa-dev] [PATCH 1/4] mesa: expose dimension check for glTex*Storage functions

On 08/10/2015 02:06 AM, Tapani Pälli wrote: This is done so that following patch can use it to verify dimenstions for multisample variants of glTex*Storage. Signed-off-by: Tapani Pälli --- src/mesa/main/texstorage.c | 22 +- src/mesa/main/texstorage.h | 3 +++ 2 files c

Re: [Mesa-dev] [PATCH] i965/skl: Remove early platform support

On Mon, Aug 10, 2015 at 09:09:41AM -0700, Jason Ekstrand wrote: > On Aug 10, 2015 4:14 AM, "Neil Roberts" wrote: > > > > If we go with this patch perhaps it would be good to remove > > supports_simd16_3src entirely from brw_device_info and any code that is > > referring to it in order to avoid car

[Mesa-dev] [PATCH] Add mesa.icd to the .gitignore

Since 4d7e0fa8c731776 this file is generated by the configure script. --- src/gallium/targets/opencl/.gitignore | 1 + 1 file changed, 1 insertion(+) create mode 100644 src/gallium/targets/opencl/.gitignore diff --git a/src/gallium/targets/opencl/.gitignore b/src/gallium/targets/opencl/.gitigno

[Mesa-dev] [Bug 91591] rounding.h:102:2: error: #error "Unsupported or undefined LONG_BIT"

https://bugs.freedesktop.org/show_bug.cgi?id=91591 --- Comment #11 from Matt Turner --- Created attachment 117615 --> https://bugs.freedesktop.org/attachment.cgi?id=117615&action=edit patch Try this -- defines __STDC_LIMIT_MACROS before including limits.h. -- You are receiving this mail beca

Re: [Mesa-dev] [PATCH 06/13] mesa: Replace sampler object locks with atomic inc/dec.

On Fri, Aug 7, 2015 at 10:09 AM, Ian Romanick wrote: > I know we've talked about this about 100 times, but something in the > back of my mind tells me that we have a pre-existing race. What happens > if the p_atomic_dec_zero happens on thread A while thread B is between > the _mesa_lookup_renderb

[Mesa-dev] [PATCH 3/3] freedreno: implement emit_string_marker

From: Rob Clark Writes string to cmdstream in payload of a no-op packet. Signed-off-by: Rob Clark --- src/gallium/drivers/freedreno/freedreno_context.c | 27 +++ src/gallium/drivers/freedreno/freedreno_screen.c | 2 +- 2 files changed, 28 insertions(+), 1 deletion(-) dif

[Mesa-dev] [PATCH 1/3] mesa: add GREMEDY_string_marker

From: Rob Clark Signed-off-by: Rob Clark --- src/mapi/glapi/gen/GREMEDY_string_marker.xml | 18 ++ src/mapi/glapi/gen/Makefile.am | 1 + src/mapi/glapi/gen/gl_API.xml| 2 ++ src/mesa/main/dd.h | 6 ++ src/mesa/main/d

[Mesa-dev] [PATCH 0/3] GREMEDY_string_marker support

From: Rob Clark Punch it through mesa and gallium, plus implementation in freedreno to serve as an example. Radeon should be able to do a similar thing with no-op packets. Not sure about other drivers. Plan to use this extension from apitrace, to emit call and frame #'s for draw commands, so I

[Mesa-dev] [PATCH 2/3] gallium: add GREMEDY_string_marker

From: Rob Clark Signed-off-by: Rob Clark --- src/gallium/docs/source/screen.rst | 1 + src/gallium/drivers/freedreno/freedreno_screen.c | 1 + src/gallium/drivers/i915/i915_screen.c | 1 + src/gallium/drivers/ilo/ilo_screen.c | 1 + src/gallium/drivers/llvmpi

[Mesa-dev] [Bug 91591] rounding.h:102:2: error: #error "Unsupported or undefined LONG_BIT"

https://bugs.freedesktop.org/show_bug.cgi?id=91591 --- Comment #10 from Roland Scheidegger --- (In reply to Jose Fonseca from comment #9) > Anwyay, roundeven_test.c is a C file, so I don't believe that's the problem. Well the last build failure showed a failure with glsl_types.cpp - only the pre

Re: [Mesa-dev] [PATCH] i965/skl: Remove early platform support

On Aug 10, 2015 4:14 AM, "Neil Roberts" wrote: > > If we go with this patch perhaps it would be good to remove > supports_simd16_3src entirely from brw_device_info and any code that is > referring to it in order to avoid carrying around useless code. > Currently it seems like it would be quite eas

[Mesa-dev] [Bug 91591] rounding.h:102:2: error: #error "Unsupported or undefined LONG_BIT"

https://bugs.freedesktop.org/show_bug.cgi?id=91591 --- Comment #9 from Jose Fonseca --- (In reply to Roland Scheidegger from comment #8) > I found some reference that for c++ you need to define __STDC_LIMIT_MACROS > before including to make it work. Dunno though if that's the > problem here. We

Re: [Mesa-dev] [PATCH 22/70] i965: Add dword aliases to bitfield structs

On 07/08/15 23:13, Chris Wilson wrote: When processing the packed fields, it often much easier to pass around verb missing after "it"? the dword value (as would be seen by hardware) than it is manipulating the bitfield. By aliasing the bitfield with a uint32_t member, we can treat the value a

[Mesa-dev] [Bug 91591] rounding.h:102:2: error: #error "Unsupported or undefined LONG_BIT"

https://bugs.freedesktop.org/show_bug.cgi?id=91591 --- Comment #8 from Roland Scheidegger --- What a mess... I found some reference that for c++ you need to define __STDC_LIMIT_MACROS before including to make it work. Dunno though if that's the problem here. Also, do we need to include ? Otherwi

Re: [Mesa-dev] [PATCH] mesa/format_utils: Add src_bits == dst_bits cases to [us]norm functions

Am 10.08.2015 um 07:03 schrieb Jason Ekstrand: > This better ensures that the src_bits == dst_bits case gets optimized away. > --- > src/mesa/main/format_utils.h | 8 ++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/src/mesa/main/format_utils.h b/src/mesa/main/format_ut

Re: [Mesa-dev] [PATCH] st/mesa: Map packed gallium formats to packed mesa formats.

Am 10.08.2015 um 07:00 schrieb Jason Ekstrand: > On Sun, Aug 9, 2015 at 6:46 AM, Roland Scheidegger wrote: >> Am 09.08.2015 um 12:11 schrieb Oded Gabbay: >>> On Sun, Aug 9, 2015 at 2:43 AM, Jason Ekstrand wrote: On Sat, Aug 8, 2015 at 3:14 PM, Oded Gabbay wrote: > On Sun, Aug 9, 2015 at

Re: [Mesa-dev] [PATCH 07/70] i965: Combine the multiple pipelined register detection into one round-trip

On Mon, Aug 10, 2015 at 04:08:07PM +0300, Martin Peres wrote: > > > On 10/08/15 16:00, Chris Wilson wrote: > >On Mon, Aug 10, 2015 at 03:17:26PM +0300, Martin Peres wrote: > >>>+static int > >>>+intel_detect_pipelined_oacontrol(struct intel_screen *screen, > >>>+ s

Re: [Mesa-dev] [PATCH 07/70] i965: Combine the multiple pipelined register detection into one round-trip

On 10/08/15 16:00, Chris Wilson wrote: On Mon, Aug 10, 2015 at 03:17:26PM +0300, Martin Peres wrote: +static int +intel_detect_pipelined_oacontrol(struct intel_screen *screen, + struct detect_pipelined_register *detect) { if (screen->devinfo->gen < 6 || s

Re: [Mesa-dev] [PATCH 07/70] i965: Combine the multiple pipelined register detection into one round-trip

On Mon, Aug 10, 2015 at 03:17:26PM +0300, Martin Peres wrote: > >+static int > >+intel_detect_pipelined_oacontrol(struct intel_screen *screen, > >+ struct detect_pipelined_register *detect) > > { > > if (screen->devinfo->gen < 6 || screen->devinfo->gen >= 8) > >

Re: [Mesa-dev] [PATCH 13/70] i965: Add a couple of utility functions to ref/unref a brw_bo

On 07/08/15 23:13, Chris Wilson wrote: To further reduce churn when replacing the buffer object implementation, wrap the existing drm_intel_bo_reference/drm_intel_bo_unreference. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h | 12 +++ src/mesa/dri

Re: [Mesa-dev] [PATCH 12/70] i965: Rename intel_batchbuffer to brw_batch

On 10/08/15 15:45, Chris Wilson wrote: On Mon, Aug 10, 2015 at 03:37:24PM +0300, Martin Peres wrote: 10-12 are: Reviewed-by: Martin Peres One thing to consider, do we want to do a s/typedef/struct brw_batch/ cleanup after the transition is complete? brw_batch vs struct brw_batch ? brw_bo vs

Re: [Mesa-dev] [PATCH] st/mesa: Map packed gallium formats to packed mesa formats.

On Mon, Aug 10, 2015 at 10:43 AM, Jason Ekstrand wrote: > On Mon, Aug 10, 2015 at 12:41 AM, Oded Gabbay wrote: >> On Mon, Aug 10, 2015 at 10:30 AM, Jason Ekstrand >> wrote: >>> On Mon, Aug 10, 2015 at 12:07 AM, Oded Gabbay wrote: On Mon, Aug 10, 2015 at 7:58 AM, Jason Ekstrand wrot

Re: [Mesa-dev] [PATCH 12/70] i965: Rename intel_batchbuffer to brw_batch

On Mon, Aug 10, 2015 at 03:37:24PM +0300, Martin Peres wrote: > 10-12 are: > > Reviewed-by: Martin Peres One thing to consider, do we want to do a s/typedef/struct brw_batch/ cleanup after the transition is complete? brw_batch vs struct brw_batch ? brw_bo vs struct brw_bo ? -Chris -- Chris Wi

Re: [Mesa-dev] [PATCH 08/70] i965: Remove early release of DRI2 miptree

On 10/08/15 15:26, Chris Wilson wrote: On Mon, Aug 10, 2015 at 03:18:09PM +0300, Martin Peres wrote: On 07/08/15 23:13, Chris Wilson wrote: intel_update_winsys_renderbuffer_miptree() will release the existing miptree when wrapping a new DRI2 buffer, so we can remove the early release and so pre

Re: [Mesa-dev] [PATCH 12/70] i965: Rename intel_batchbuffer to brw_batch

10-12 are: Reviewed-by: Martin Peres On 07/08/15 23:13, Chris Wilson wrote: In order to reduce future churn, rename the intel_batchbuffer struct. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h | 4 ++-- src/mesa/drivers/dri/i965/brw_context.h | 2 +-

Re: [Mesa-dev] [PATCH 08/70] i965: Remove early release of DRI2 miptree

On Mon, Aug 10, 2015 at 03:18:09PM +0300, Martin Peres wrote: > On 07/08/15 23:13, Chris Wilson wrote: > >intel_update_winsys_renderbuffer_miptree() will release the existing > >miptree when wrapping a new DRI2 buffer, so we can remove the early > >release and so prevent a NULL mt dereference shoul

Re: [Mesa-dev] [PATCH 09/70] i965: Remove direct includes of intel_batchbuffer.h

On 07/08/15 23:13, Chris Wilson wrote: Upcoming patches eliminate the intel_batchbuffer interface and one of the minor changes that causes a lot of churn is the removal of the header, along with the occassional need to now call intel_reg.h themselves. This patch moves the individual includes into

Re: [Mesa-dev] [PATCH v2] glsl/es3.1: Fix up GL_ARB_compute_shader for GLSL ES 3.1

On Mon, 2015-08-10 at 13:04 +0200, Marta Lofstedt wrote: > From: Marta Lofstedt > > GL_ARB_compute_shader is limited for GLSL version 430. > This enables for GLSL ES version 310. > > V2: Updated error string to also include GLSL 3.10 > > Signed-off-by: Marta Lofstedt > --- > src/glsl/glsl_par

  1   2   >