With Petri and Ilia's comments addressed, this patch is
Reviewed-by: Ian Romanick
On 04/29/2015 01:56 AM, kevin.rogo...@intel.com wrote:
> From: Kevin Rogovin
>
> Mark GL_ARB_framebuffer_no_attachments as done for i965.
>
> ---
> docs/GL3.txt | 2 +-
> docs/relnotes/10.6.0.html
On 04/29/2015 01:56 AM, kevin.rogo...@intel.com wrote:
> From: Kevin Rogovin
>
> Enable GL_ARB_framebuffer_no_attachments in i965 for Gen7 and higher.
>
> ---
> src/mesa/drivers/dri/i965/brw_context.c | 6 ++
> src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
> 2 files changed, 7 in
On 04/29/2015 01:56 AM, kevin.rogo...@intel.com wrote:
> From: Kevin Rogovin
>
> If the fragment shader has atomic buffer access, the shader must execute
> even if the current draw buffer has no attachments.
>
> ---
> src/mesa/drivers/dri/i965/gen7_wm_state.c | 7 +++
> src/mesa/drivers/dri
On 04/29/2015 01:56 AM, kevin.rogo...@intel.com wrote:
> From: Kevin Rogovin
>
> Implement GL_ARB_framebuffer_no_attachments in Mesa core
> - changes to conditions for framebuffer completenss
> - implement set/get functions for framebuffers for
>new functions in GL_ARB_framebuffer_no_attac
You haven't been running 'make check'. :) You also need to update
src/mesa/tests/dispatch_sanity.cpp.
On 04/29/2015 01:56 AM, kevin.rogo...@intel.com wrote:
> From: Kevin Rogovin
>
> Define the enumeration constants, function entry points and
> glGet for the GL_ARB_framebuffer_no_attachments
>
These patches are partitioned in a atypical way. The usual way is
- A patch that modifies extensions.c, struct gl_extensions, the XML
files (in patch #2), dispatch_sanity (see my comment on patch #2),
and adds the stub functions (in patch #2).
- A patch that adds the other necessary bits
Increases pass rate of ES31-CTS.*program_interface_query* tests
when run with MESA_EXTENSION_OVERRIDE='GL_ARB_compute_shader'. Many
of the negative tests that happen to use compute stage in queries
start passing.
Signed-off-by: Tapani Pälli
---
src/mesa/main/shader_query.cpp | 22 +++
On Wed, 6 May 2015 11:00:13 +1000
Dave Airlie wrote:
> On 2 May 2015 at 20:15, Axel Davy wrote:
> > Only EGL_WINDOW_BIT is supported. Remove tests related.
>
> Is this there no plans to support pixmap/pbuffer/ or any of the other bits?
>
> Seems like a step in the wrong direction if we really
This seems to be used in ast_function.cpp for implementing constructors
where this type of conversion can happen, so not a implicit conversion
but a 'conversion constructor'.
(5.4.1 Conversion and Scalar Constructors)
You would need to change that also.
On 05/06/2015 09:17 AM, Dave Airlie wr
From: Dave Airlie
Implicit conversion can only happen the other way.
This fixes a bug I just saw from writing an incorrect test.
Signed-off-by: Dave Airlie
---
src/glsl/ast_to_hir.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 14
On Wednesday, May 06, 2015 06:08:17 PM Chris Forbes wrote:
> Signed-off-by: Chris Forbes
> ---
> src/mesa/drivers/dri/i965/brw_context.c | 4 ++--
> src/mesa/drivers/dri/i965/brw_defines.h | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_c
On 05/06/2015 08:38 AM, Jason Ekstrand wrote:
On May 5, 2015 10:17 PM, "Tapani Pälli" mailto:tapani.pa...@intel.com>> wrote:
>
>
> On 05/06/2015 04:57 AM, Kenneth Graunke wrote:
>>
>> Vertex shader attribute and fragment shader output queries rely on being
>> able to inspect top-level ir
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/intel_extensions.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index c28c171..3088a1a 100644
--- a/src/me
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_structs.h | 2 ++
src/mesa/drivers/dri/i965/gen6_viewport_state.c | 29 +++--
2 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h
b/src/mesa/drivers/dri
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_context.c | 4 ++--
src/mesa/drivers/dri/i965/brw_defines.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 6c00f6c..fd7420
Signed-off-by: Chris Forbes
---
src/mesa/drivers/dri/i965/gen6_viewport_state.c | 40 +
1 file changed, 21 insertions(+), 19 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_viewport_state.c
b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
index 0c63283..95d204f
On Tue, 2015-05-05 at 16:41 +0300, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> > We can do this when the surface index is an immediate, as we do for
> > reads. Otherwise the visitor should handle this.
> > ---
> > Francisco, maybe you choose not to do this for a reason? It seems a bit
On May 5, 2015 10:17 PM, "Tapani Pälli" wrote:
>
>
> On 05/06/2015 04:57 AM, Kenneth Graunke wrote:
>>
>> Vertex shader attribute and fragment shader output queries rely on being
>> able to inspect top-level ir_variable objects. So, we have to keep
>> those. However, functions and global tempora
On 05/06/2015 04:57 AM, Kenneth Graunke wrote:
Vertex shader attribute and fragment shader output queries rely on being
able to inspect top-level ir_variable objects. So, we have to keep
those. However, functions and global temporary variables can be deleted
with impunity.
Saves 58MB of memor
Mainly for Ian, this is the fix to the outstanding patch,
with an R-b on this I think they due a push.
Dave.
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From: Dave Airlie
Just more boilerplate stuff.
v2:
bad fallthrough on versioning,
this is my ugly but self contained solution (Ian)
Reviewed-by: Ilia Mirkin
Signed-off-by: Dave Airlie
---
src/glsl/ast_to_hir.cpp | 3 +++
src/glsl/glcpp/glcpp-parse.y| 3 +++
src/glsl/glsl_parser_e
https://bugs.freedesktop.org/show_bug.cgi?id=90147
--- Comment #5 from Jeremy Huddleston ---
Yeah, I think the sysctl() approach is probably more portable if you want to go
that route.
I was also thinking that this should be refactored into a more abstract layer
since other places in mesa would
On Mon 04 May 2015, Daniel Stone wrote:
> Hi,
>
> On 1 May 2015 at 21:02, Chad Versace wrote:
> > +static bool
> > +brw_fence_has_completed(struct brw_fence *fence)
> > +{
> > + if (fence->signalled)
> > + return true;
> > +
> > + if (fence->batch_bo && !drm_intel_bo_busy(fence->batch_bo
Vertex shader attribute and fragment shader output queries rely on being
able to inspect top-level ir_variable objects. So, we have to keep
those. However, functions and global temporary variables can be deleted
with impunity.
Saves 58MB of memory when replaying a Dota 2 trace on Broadwell.
Sig
On Tuesday, May 05, 2015 06:28:03 PM Jason Ekstrand wrote:
> This is a v2 of the series that I sent out a month or two ago to fix up the
> LOAD_PAYLOAD instruction in the i965 FS backend compiler. This new version
> incorporates comments from a variety of people.
>
> The last patch in the series
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 6 +-
src/mesa/drivers/dri/i965/brw_fs.h | 3 ++-
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 3 ++-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 20 +++-
4 files changed, 20 inse
From: Kenneth Graunke
This especially helps with NIR because we currently emit MOVs at the top
of the shader to copy from various ATTR registers to a giant VGRF array
of all inputs. (This could potentially be done better, but since
there's only ever one write to each register, it should be trivi
We rework LOAD_PAYLOAD to verify that all of the sources that count as
headers are, indeed, exactly one register and that all of the non-header
sources match the destination width. We then take the exec_size for
LOAD_PAYLOAD directly from the destination width.
Reviewed-by: Kenneth Graunke
---
The effective_width field was an ill-concieved hack to get around issues in
the LOAD_PAYLOAD instruction. Now that the LOAD_PAYLOAD instruction is far
more sane, this field can die.
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 25 --
Previously, setup_color_payload was a a big helper function that did a lot
of gen-specific special casing for setting up the color sources of the
LOAD_PAYLOAD instruction. Now that lower_load_payload is much more sane,
most of that complexity isn't needed anymore. Instead, we can do a simple
fixu
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 31 ---
1 file changed, 24 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
index a582e6a..db01f8c 100644
--- a/s
Instead of the complicated and broken-by-design pile of heuristics we had
before, we now have a straightforward lowering:
1) All header sources are copied directly using force_writemask_all and,
since they are guaranteed to be a single register, there are no
force_sechalf issues.
2) All
v2: Get rid of the block parameter and make src a const reference
Reviewed-by: Topi Pohjolainen
Reviewed-by: Matt Turner
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 75
1 file changed, 38 insertions(+), 37 deletions(-)
diff --gi
From: Francisco Jerez
Immediates are generally uniform, they yield the same value to both
halves of any instruction.
Reviewed-by: Matt Turner
---
src/mesa/drivers/dri/i965/brw_ir_fs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index e7095c9..d0a3bdd 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965
This commit adds a new is_copy_payload helper to fs_inst that takes the
place of the similarly named functions in cse and register coalesce. The
two is_copy_payload functions in CSE and register coalesce were subtly
different and potentially subtly broken. The new version unifies the two
and shou
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 813df22..c3ccc9d 100644
--- a/src/me
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 16 +---
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index
Previously, we had a special case for uniforms and immediates and then a
bunch of asserts for various other pessimal things. This commit changes it
so that it explicitly does something on each register file. Some of them
are disallowed and others are treated properly.
---
src/mesa/drivers/dri/i9
This is a v2 of the series that I sent out a month or two ago to fix up the
LOAD_PAYLOAD instruction in the i965 FS backend compiler. This new version
incorporates comments from a variety of people.
The last patch in the series is one that I think at least 3 of us have
independantly written to en
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 4 +--
src/mesa/drivers/dri/i965/brw_fs.cpp | 18 ++---
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 20 +++
src/mes
On 2 May 2015 at 20:15, Axel Davy wrote:
> Enables to use dri config for swrast, like vblank_mode.
>
> Signed-off-by: Axel Davy
Reviewed-by: Dave Airlie
> ---
> src/egl/drivers/dri2/egl_dri2.c| 21 ++---
> src/gallium/state_trackers/dri/drisw.c | 1 +
> src/mesa/driver
On 2 May 2015 at 20:15, Axel Davy wrote:
> Signed-off-by: Axel Davy
I think I'd like to see the os-compatibility ported code
be in a separate file, I wonder if any of it would be useful
in other places,
But even that isn't a major problem,
Reviewed-by: Dave Airlie
> +static int
> +dri2_wl_sw
On 2 May 2015 at 20:15, Axel Davy wrote:
> Only EGL_WINDOW_BIT is supported. Remove tests related.
Is this there no plans to support pixmap/pbuffer/ or any of the other bits?
Seems like a step in the wrong direction if we really should be supporting
other things than WINDOW_BIT in the future.
D
On 2 May 2015 at 20:15, Axel Davy wrote:
> When the server gpu and requested gpu are different:
> . They likely don't support the same tiling modes
> . They likely do not have fast access to the same locations
>
> Thus we do:
> . render to a tiled buffer we do not share with the server
> . Copy th
This uses the i915_oa '3D' metric set to expose many more interesting OA
counters including information about depth, alpha and stencil testing,
sampler usage/bottlneck stats and cache throughputs.
Signed-off-by: Robert Bragg
---
src/mesa/drivers/dri/i965/brw_performance_query.c | 402 +++
This adds a bare-bones backend for the INTEL_performance_query extension
that exposes the pipeline statistics on gen 6 and 7 hardware.
Although this could be considered redundant given that the same
statistics are now available via query objects, they are a simple
starting point for this extension
This adds support for exposing basic ('aggregate') Observation
Architecture performance counters on Haswell.
This support is based on the i915_oa perf kernel interface which is used
to configure the OA unit, allowing Mesa to emit MI_REPORT_PERF_COUNT
commands around queries to collect counter snap
To allow the backend interfaces for AMD_performance_monitor and
INTEL_performance_query to evolve independently based on the more
specific requirements of each extension this starts by separating
the frontends of these extensions.
Even though there wasn't much tying these frontends together, this
As we've learned more about the observability capabilities of Gen
graphics we've found that it's not enough to only try and configure the
OA unit from userspace without any dedicated support from the kernel.
As it is currently the i965 backends for both AMD_performance_monitor
and INTEL_performanc
Instead of using the same backend interface as AMD_performance_monitor
this defines a dedicated INTEL_performance_query interface that is based
on the ARB_query_buffer_object interface (considering the similarity of
the extensions) with the addition of vfuncs for enumerating queries and
their count
In its current state the unified i965 backend for
AMD_performance_monitor and INTEL_performance_query isn't able to report
meaningful Observation Architecture metrics since we haven't so far had
the necessary kernel support to fully configure the OA unit, nor the
corresponding support for normalizi
On Tue, May 5, 2015 at 5:16 PM, Connor Abbott wrote:
> Typo in the subject line.
Fixed Locally
--Jason
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On 2 May 2015 at 20:15, Axel Davy wrote:
> It is possible the server advertises a render-node.
> In that case no authentication is needed,
> and Gem names are forbidden.
>
> Signed-off-by: Axel Davy
Reviewed-by: Dave Airlie
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m
On 2 May 2015 at 20:15, Axel Davy wrote:
> Checks blitImage is implemented.
> Initially having the __DRIimageExtension extension
> at version 9 at least meant blitImage was supported.
> However some implementations do advertise version >= 9
> without implementing it.
>
> Signed-off-by: Axel Davy
On 2 May 2015 at 20:15, Axel Davy wrote:
> the wl_registry and the wl_queue allocated weren't destroyed.
>
> Signed-off-by: Axel Davy
Reviewed-by: Dave Airlie
> ---
> src/egl/drivers/dri2/egl_dri2.c | 2 ++
> src/egl/drivers/dri2/platform_wayland.c | 5 -
> 2 files changed, 6 inse
On 2 May 2015 at 20:15, Axel Davy wrote:
> EGL_SOFTWARE is not supported anywhere in the code,
> whereas LIBGL_ALWAYS_SOFTWARE is.
>
> Signed-off-by: Axel Davy
Reviewed-by: Dave Airlie
> ---
> docs/egl.html | 8
> 1 file changed, 8 deletions(-)
>
> diff --git a/docs/egl.html b/docs/eg
Typo in the subject line.
On Tue, Apr 28, 2015 at 12:03 AM, Jason Ekstrand wrote:
> ---
> src/glsl/nir/nir_validate.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/src/glsl/nir/nir_validate.c b/src/glsl/nir/nir_validate.c
> index a7aa798..35a853d 100644
> --- a/src/glsl/nir/nir_vali
On Tue, May 5, 2015 at 4:20 PM, Matt Turner wrote:
> On Tue, May 5, 2015 at 4:13 PM, Jason Ekstrand wrote:
>> On Wed, Apr 15, 2015 at 6:44 PM, Matt Turner wrote:
>>> On Wed, Apr 15, 2015 at 5:13 PM, Jason Ekstrand
>>> wrote:
On Wed, Apr 15, 2015 at 1:31 PM, Matt Turner wrote:
> On We
On Tue, May 5, 2015 at 4:13 PM, Jason Ekstrand wrote:
> On Wed, Apr 15, 2015 at 6:44 PM, Matt Turner wrote:
>> On Wed, Apr 15, 2015 at 5:13 PM, Jason Ekstrand wrote:
>>> On Wed, Apr 15, 2015 at 1:31 PM, Matt Turner wrote:
On Wed, Apr 1, 2015 at 6:19 PM, Jason Ekstrand
wrote:
> I
On Wed, Apr 15, 2015 at 6:44 PM, Matt Turner wrote:
> On Wed, Apr 15, 2015 at 5:13 PM, Jason Ekstrand wrote:
>> On Wed, Apr 15, 2015 at 1:31 PM, Matt Turner wrote:
>>> On Wed, Apr 1, 2015 at 6:19 PM, Jason Ekstrand wrote:
Instead of the complicated and broken-by-design pile of heuristics w
On 05/06/2015 12:03 AM, Brian Paul wrote:
On 05/05/2015 04:00 PM, Ian Romanick wrote:
On 05/05/2015 02:50 PM, Brian Paul wrote:
Was missing the context parameter. Fixes MSVC warning.
Does this then result in a GCC warning about unused parameters?
Not that I've seen (only tried a debug bui
https://bugs.freedesktop.org/show_bug.cgi?id=90147
Julien Isorce changed:
What|Removed |Added
CC||jerem...@freedesktop.org
--- Comment #4
On Tuesday, May 05, 2015 02:31:39 PM Jason Ekstrand wrote:
> On Tue, May 5, 2015 at 1:34 PM, Matt Turner wrote:
> > On Tue, May 5, 2015 at 1:13 PM, Jason Ekstrand wrote:
> >> On Tue, Apr 14, 2015 at 1:28 AM, Kenneth Graunke
> >> wrote:
> >>> 2. CSE didn't use equals(), so it allowed things like
On Tuesday, May 05, 2015 03:05:02 PM Matt Turner wrote:
> On Tue, May 5, 2015 at 2:17 PM, Francisco Jerez wrote:
> > Kenneth Graunke writes:
> >> That then begs the question - could we do the format conversion and
> >> address calculations in a i965-specific NIR pass? It could simplify
> >> the
https://bugs.freedesktop.org/show_bug.cgi?id=90147
--- Comment #3 from Brian Paul ---
So which patch do you want to use? Either looks OK to me.
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https://bugs.freedesktop.org/show_bug.cgi?id=90325
nmcve...@gmail.com changed:
What|Removed |Added
Resolution|NOTABUG |FIXED
--- Comment #9 from nmcve...@g
On Tue, May 5, 2015 at 2:17 PM, Francisco Jerez wrote:
> Kenneth Graunke writes:
>> That then begs the question - could we do the format conversion and
>> address calculations in a i965-specific NIR pass? It could simplify
>> the backend changes. NIR also has better CSE, which could help for
>>
https://bugs.freedesktop.org/show_bug.cgi?id=90325
--- Comment #8 from Ian Romanick ---
BTW... you should checkout libGLEW or libepoxy.
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On 05/05/2015 04:00 PM, Ian Romanick wrote:
On 05/05/2015 02:50 PM, Brian Paul wrote:
Was missing the context parameter. Fixes MSVC warning.
Does this then result in a GCC warning about unused parameters?
Not that I've seen (only tried a debug build).
-Brian
__
Weird that I didn't notice this when I wrote the code. :( Sorry about
that. This patch is
Reviewed-by: Ian Romanick
On 05/05/2015 02:50 PM, Brian Paul wrote:
> Silences gcc warning:
> builtin_functions.cpp:204:23: warning: suggest parentheses around '&&'
> within '||' [-Wparentheses]
> ---
> s
On 05/05/2015 02:50 PM, Brian Paul wrote:
> Was missing the context parameter. Fixes MSVC warning.
Does this then result in a GCC warning about unused parameters?
> ---
> src/mesa/state_tracker/st_cb_perfmon.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/st
Series is
Reviewed-by: Ilia Mirkin
On Tue, May 5, 2015 at 5:50 PM, Brian Paul wrote:
> Fixes MSVC build error.
> ---
> src/mesa/state_tracker/st_cb_perfmon.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/state_tracker/st_cb_perfmon.c
> b/src/mesa/state_trac
https://bugs.freedesktop.org/show_bug.cgi?id=90325
Ian Romanick changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=66346
--- Comment #16 from Julien Isorce ---
Created attachment 115566
--> https://bugs.freedesktop.org/attachment.cgi?id=115566&action=edit
darwin: Suppress type conversion warnings for GLhandleARB
Patch from macports:
https://trac.macports.org/bro
https://bugs.freedesktop.org/show_bug.cgi?id=90147
Julien Isorce changed:
What|Removed |Added
CC||bri...@vmware.com
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https://bugs.freedesktop.org/show_bug.cgi?id=90325
--- Comment #6 from nmcve...@gmail.com ---
QueryCounters was an extension but it was added to the core profile in 3.3, you
can see it right there in section 5.1
(https://www.opengl.org/registry/doc/glspec33.core.20100311.withchanges.pdf).
--
You
https://bugs.freedesktop.org/show_bug.cgi?id=90147
--- Comment #2 from Julien Isorce ---
Created attachment 115565
--> https://bugs.freedesktop.org/attachment.cgi?id=115565&action=edit
swrast: Build fix for darwin
Other solution from macports.
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---
src/mesa/drivers/dri/i965/brw_shader.cpp | 32
src/mesa/drivers/dri/i965/brw_shader.h | 2 ++
2 files changed, 34 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index c1fd859..61ef0c0 100644
-
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 497b8f7..a774f98 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 889079b..1eaec10 100644
--- a/src/mesa/drivers/dri/i965/
---
src/mesa/drivers/dri/i965/brw_fs.h | 1 +
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 55 +++-
2 files changed, 48 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index aac9c4b..4f7d95e 10064
Images take up zero uniform slots in the nir_shader::num_uniforms
calculation, but nir_setup_uniforms needs to be executed even if the
program has no non-image uniforms so the driver-specific image
parameters are uploaded. nir_setup_uniforms is a no-op if there are
really no uniforms, so checking
Rewrite the GLSL IR atomic counter intrinsics translation code making
use of the recently introduced surface builder. This will allow the
removal of some of the functionality duplicated in the visitor and
surface builder.
v2: Drop VEC4 suport.
---
src/mesa/drivers/dri/i965/brw_fs.h |
Fixes MSVC build error.
---
src/mesa/state_tracker/st_cb_perfmon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_cb_perfmon.c
b/src/mesa/state_tracker/st_cb_perfmon.c
index c8d4490..1bb5be3 100644
--- a/src/mesa/state_tracker/st_cb_perfmon.c
+++ b/s
Silences gcc warning:
builtin_functions.cpp:204:23: warning: suggest parentheses around '&&'
within '||' [-Wparentheses]
---
src/glsl/builtin_functions.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index 1df6
v2: Drop VEC4 suport.
---
.../drivers/dri/i965/brw_fs_surface_builder.cpp| 216 +
src/mesa/drivers/dri/i965/brw_fs_surface_builder.h | 17 ++
2 files changed, 233 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp
b/src/mesa/drivers/dri/i965/
---
src/mesa/drivers/dri/i965/brw_fs.h | 7 --
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 13 ++-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 125 ++-
3 files changed, 10 insertions(+), 135 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b
Reviewed-by: Paul Berry
v2: Disable the extension for the time being if NIR is in use until it
grows the necessary intrinsics.
v3: Drop GLSL IR support. Disable the extension if NIR is *not* in use.
---
src/mesa/drivers/dri/i965/intel_extensions.c | 2 ++
1 file changed, 2 insertions(+)
di
Rewrite the NIR atomic counter intrinsics translation code making use
of the recently introduced surface builder. This will allow the
removal of some of the functionality duplicated in the visitor and
surface builder.
v2: Drop VEC4 suport.
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 56 ++
These utility functions check whether an image access is valid.
According to the spec an invalid image access should have no effect on
the image and yield well-defined results. Typically the hardware
implements correct bounds and surface checking by itself, but in some
cases (typed atomics on IVB
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 158 +++
1 file changed, 158 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index a166e59..497b8f7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++
Image variables need to allocate additional uniform slots over
nir_shader::num_uniforms. nir_setup_uniforms() overwrites the values
imported from the SIMD8 visitor and then exits early before entering
the nir_shader::uniforms loop, so image uniforms are never re-created.
Instead leave the imported
Define bitfield packing, unpacking and type conversion operations in
terms of which the image format conversion code will be implemented.
These don't directly know about image formats: The packing and
unpacking functions take a 4-tuple of bit shifts and a 4-tuple of bit
widths as arguments, determi
Was missing the context parameter. Fixes MSVC warning.
---
src/mesa/state_tracker/st_cb_perfmon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_cb_perfmon.c
b/src/mesa/state_tracker/st_cb_perfmon.c
index 4bde679..c8d4490 100644
--- a/src/mesa/state
Implement helper functions that can be used to construct and send
untyped and typed surface read, write and atomic messages to the
shared dataport unit.
v2: Drop VEC4 suport.
---
.../drivers/dri/i965/brw_fs_surface_builder.cpp| 232 +
src/mesa/drivers/dri/i965/brw_fs_surfa
Define some utility functions to query the bitfield layout of a given
image format and whether it satisfies a number of more or less
hardware-specific properties.
v2: Drop VEC4 suport.
---
src/mesa/drivers/dri/i965/brw_fs_surface_builder.h | 147 +
1 file changed, 147 insertio
v2: Update NIR atomic intrinsic handling too (Ken).
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 8 ++--
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 3 +++
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4
src/mesa/drivers/dri/i965/brw_v
Define a function to calculate the memory address of the image
location given by a vector of coordinates. This is required in cases
where we need to fall back to untyped surface access, which take a raw
memory offset and know nothing about surface coordinates, type
conversion or memory tiling and
These functions implement the memory layout of a vecN value in a
message or return payload. The conversion is not always trivial
because the shared unit may not support the SIMD16 or SIMD4x2 vector
layouts, requiring splitting the payload in half and merging the reply
in the former case, or spread
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