[Mesa-dev] [Bug 89260] macros.h:34:25: fatal error: util/u_math.h: No such file or directory

https://bugs.freedesktop.org/show_bug.cgi?id=89260 Bug ID: 89260 Summary: macros.h:34:25: fatal error: util/u_math.h: No such file or directory Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (

Re: [Mesa-dev] [PATCH 2/4] common: Correct PBO 2D_ARRAY handling.

There needs to be some corresponding Piglit test to guarantee that skip pixels is really a problem here. Otherwise, I'm flying blind trying to fix it. On Fri, Feb 20, 2015 at 5:04 PM, Jason Ekstrand wrote: > This is mostly correct and it's a good solution. The only problem is that > it doesn't

Re: [Mesa-dev] [PATCH 1/7] i965: Introduce the BROADCAST pseudo-opcode.

Ian Romanick writes: > I want to be sure I understand what this series is doing and why it's > necessary. > > Sampler arrays and UBO arrays can, with some restrictions, be indexed > dynamically. The primary restriction is that any active SIMD channels > that access the array must access the same

Re: [Mesa-dev] [PATCH 1/4] common: Correct texture initialization in create_texture_for_pbo.

On Fri, Feb 20, 2015 at 4:30 PM, Laura Ekstrand wrote: > Solves bugs related to the driver not setting up the texture miptree > correctly, leading to faulty PBO uploads and downloads. > --- > src/mesa/drivers/common/meta_tex_subimage.c | 13 + > src/mesa/drivers/dri/i965/intel_tex.c

Re: [Mesa-dev] [PATCH 2/4] common: Correct PBO 2D_ARRAY handling.

This is mostly correct and it's a good solution. The only problem is that it doesn't handle the skipRows packing property properly. This property tells the driver the stride (in rows) between image planes in the data. Most of the places where depth is used below, we should be using the stride (in

Re: [Mesa-dev] [PATCH 06/16] main: Added entry point for glTransformFeedbackBufferRange

On Mon, Feb 16, 2015 at 6:13 AM, Martin Peres wrote: > v2: review from Laura Ekstrand > - use the refactored code to lookup the objects > - improve some error messages > - factor out the gl method name computation > - better handle the spec differences between the DSA and non-DSA cases > - quote

Re: [Mesa-dev] [PATCH 1/7] i965: Introduce the BROADCAST pseudo-opcode.

I want to be sure I understand what this series is doing and why it's necessary. Sampler arrays and UBO arrays can, with some restrictions, be indexed dynamically. The primary restriction is that any active SIMD channels that access the array must access the same index. When you get to a particu

Re: [Mesa-dev] [PATCH 05/16] main: Added entry point for glTransformFeedbackBufferBase

You still seem to be confused about the names of internal functions. If a function exists outside of its "class," (ie. is extern-ed from a *.h file), it should have the "_mesa" in front. If a function exists purely inside of a *.c file, it should be static and not have "_mesa." Since _mesa_looku

[Mesa-dev] [Bug 89245] [bisected] "Drop dependency on mtypes.h for core NIR" patch broke Gallium builds

https://bugs.freedesktop.org/show_bug.cgi?id=89245 Benjamin Bellec changed: What|Removed |Added Status|NEW |RESOLVED CC|

Re: [Mesa-dev] [PATCH 1/5] nir: Add a couple of simplifications of csel operations.

Aside from one minor suggestion for patch 2, this series is Reviewed-by: Connor Abbott On Fri, Feb 20, 2015 at 3:28 PM, Matt Turner wrote: > The series is > > Reviewed-by: Matt Turner > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > h

Re: [Mesa-dev] [PATCH 2/5] nir: Allow nir_opt_algebraic to see booleanness through &&, ||, !.

On Fri, Feb 20, 2015 at 3:04 PM, Eric Anholt wrote: > We have some useful optimizations to drop things like 'ine a, 0' on a > boolean argument, but if 'a' came from logical operations on bools, it > couldn't tell. These kinds of constructs appear as a result of TGSI->NIR > quite frequently (at le

[Mesa-dev] [PATCH 3/6] i965/skl: Fix the qpitch value

On Skylake the qpitch value is uploaded as part of the surface state so we don't need to add the extra rows that are done for other generations. However for 3D textures it needs to be aligned to the tile height. Unlike previous generations the qpitch is measured as a multiple of the block size for

[Mesa-dev] [PATCH 1/6] i965/skl: Layout 3D textures the same as array textures

On Gen9+ the 3D textures use the same mipmap layout as 2D array textures. --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index 0e2

[Mesa-dev] [PATCH 2/6] i965/skl: Layout a 1D miptree horizontally

On Gen9+ the 1D miptree is laid out with all of the mipmap levels in a horizontal line. --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 62 +- 1 file changed, 60 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/

[Mesa-dev] [PATCH 0/6] i965/skl: Texture layout fixes

Here is a v2 of my patch series to fix 1D textures on Skylake. It's now turned into just some general fixes and also helps with 3D textures. It fixes 110 piglit tests but sadly seems to cause 3 regressions. It might not be worth landing until I can work out what the regressions are so I guess I'm j

[Mesa-dev] [PATCH 4/6] i965: Don't force x-tiling for 16-bpp formats on Gen>7

Sandybridge doesn't support y-tiling for surface formats with 16 or more bpp. There was previously an override to explicitly allow this for Gen7. However, this restriction is also removed in Gen8+ so we should use y-tiling there too. This is important to do for Skylake which doesn't support x-tili

[Mesa-dev] [PATCH 6/6] i965/skl: Don't use ALL_SLICES_AT_EACH_LOD

The render surface state command for Skylake doesn't have the surface array spacing bit so I don't think it's possible to select this layout. This avoids a kernel panic when running the piglit test below: ext_framebuffer_multisample-no-color 8 stencil single However the test still fails so there

[Mesa-dev] [PATCH 5/6] i965/skl: Align compressed textures to four times the block size

On Skylake it is possible to choose your own alignment values for compressed textures but they are expressed as a multiple of the block size. The minimum alignment value we can use is 4 so we effectively have to align to 4 times the block size. This patch makes it initially set mt->align_[wh] to th

Re: [Mesa-dev] [PATCH] i965/fs: Use fs_reg for CS/VS atomics pixel mask immediate data

On Fri, Feb 20, 2015 at 1:14 PM, Jordan Justen wrote: > The brw_imm_ud will yield a HW_REG which then will introduce a barrier > for certain optimization opportunities. > > No piglit regressions seen with gen8 (simd8vs). > > Suggested-by: Matt Turner > Signed-off-by: Jordan Justen > Cc: Matt Tur

Re: [Mesa-dev] [PATCH 2/3] i965/fs/nir: Optimize (gl_FrontFacing ? x : y) where x and y are ±1.0.

On Fri, Feb 20, 2015 at 1:41 PM, Eric Anholt wrote: >> Or maybe I'm just wrong and some bit is guaranteed to be set? > > A "This negation looks like it's safe in practice, because bits 0:4 will > surely be TRIANGLES" comment seems fine with me. Thanks, will do. R-b? I realized I was looking at V

Re: [Mesa-dev] [PATCH] mesa: Have configure define NDEBUG, not mtypes.h.

On Friday, February 20, 2015 12:44:53 PM Matt Turner wrote: > mtypes.h had been defining NDEBUG (used by assert) if DEBUG was not > defined. Confusing and bizarre that you don't get NDEBUG if you don't > include mtypes.h. > > ... which is just what happened in commit bef38f62e. > > Let's let conf

Re: [Mesa-dev] [PATCH] drivers/x11: add gallium include dirs to Makefile.am

Matt Turner writes: > On Fri, Feb 20, 2015 at 12:20 PM, Brian Paul wrote: >> Fixes xlib driver build after e8c5cbfd921680c. >> --- >> src/mesa/drivers/x11/Makefile.am | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/src/mesa/drivers/x11/Makefile.am >> b/src/mesa/drivers/x11/Makefi

Re: [Mesa-dev] [PATCH 2/3] i965/fs/nir: Optimize (gl_FrontFacing ? x : y) where x and y are ±1.0.

Matt Turner writes: > On Fri, Feb 20, 2015 at 11:54 AM, Eric Anholt wrote: >> I wanted patch #1 to land, so I took a look at this one :) > > Thanks! :) > >> Matt Turner writes: >>> + if (brw->gen >= 6) { >>> + /* Bit 15 of g0.0 is 0 if the polygon is front facing. */ >>> + fs_reg g0

[Mesa-dev] [Bug 89245] [bisected] "Drop dependency on mtypes.h for core NIR" patch broke Gallium builds

https://bugs.freedesktop.org/show_bug.cgi?id=89245 Bug ID: 89245 Summary: [bisected] "Drop dependency on mtypes.h for core NIR" patch broke Gallium builds Product: Mesa Version: git Hardware: x86-64 (AMD64)

Re: [Mesa-dev] [PATCH] drivers/x11: add gallium include dirs to Makefile.am

On Fri, Feb 20, 2015 at 12:20 PM, Brian Paul wrote: > Fixes xlib driver build after e8c5cbfd921680c. > --- > src/mesa/drivers/x11/Makefile.am | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/src/mesa/drivers/x11/Makefile.am > b/src/mesa/drivers/x11/Makefile.am > index 76a7cd4..c0596f8

[Mesa-dev] [PATCH 1/4] common: Correct texture initialization in create_texture_for_pbo.

Solves bugs related to the driver not setting up the texture miptree correctly, leading to faulty PBO uploads and downloads. --- src/mesa/drivers/common/meta_tex_subimage.c | 13 + src/mesa/drivers/dri/i965/intel_tex.c | 3 ++- src/mesa/main/dd.h | 1 +

[Mesa-dev] [PATCH 0/4] v2: Fix PBO uploads/downloads.

This is a more robust set of patches to fix Meta PBO texture uploads and downloads. This fixes bugs related to array PBOs that were found using the new set of getteximage-targets tests. Laura Ekstrand (4): common: Correct texture initialization in create_texture_for_pbo. common: Correct PBO 2

[Mesa-dev] [PATCH 3/4] common: Fix PBOs for 1D_ARRAY.

Corrects the way that _mesa_meta_pbo_TexSubImage and _mesa_meta_pbo_GetTexSubImage handle 1D_ARRAY textures. Fixes a failure in the Piglit arb_direct_state_access/gettextureimage-targets test. --- src/mesa/drivers/common/meta_tex_subimage.c | 62 + 1 file changed, 36 i

[Mesa-dev] [PATCH 4/4] i965: Force miptrees for BOs to have all slices in each lod.

Textures made expressly for internal buffer objects shouldn't have extra padding around them, but should be densely packed. --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mes

[Mesa-dev] [PATCH 2/4] common: Correct PBO 2D_ARRAY handling.

Changes PBO uploads and downloads to use a tall (height * depth) 2D texture for blitting. This fixes the bug where 2D_ARRAY, 3D, and CUBE_MAP_ARRAY textures are not properly uploaded and downloaded. --- src/mesa/drivers/common/meta_tex_subimage.c | 6 +++--- 1 file changed, 3 insertions(+), 3 del

Re: [Mesa-dev] nir: Compilation error in nir/nir_to_ssa.c

On Fri, Feb 20, 2015 at 1:23 PM, Dieter Nützel wrote: > make[3]: Entering directory '/opt/mesa/src/glsl' > CC nir/nir_to_ssa.lo > In file included from nir/../glsl_types.h:30:0, > from nir/nir_types.h:32, > from nir/nir.h:36, > from nir/ni

[Mesa-dev] nir: Compilation error in nir/nir_to_ssa.c

make[3]: Entering directory '/opt/mesa/src/glsl' CC nir/nir_to_ssa.lo In file included from nir/../glsl_types.h:30:0, from nir/nir_types.h:32, from nir/nir.h:36, from nir/nir_to_ssa.c:28: nir/nir_to_ssa.c: In function 'rewrite_def_forwards

Re: [Mesa-dev] [PATCH] i965/fs: Use fs_reg for CS/VS atomics pixel mask immediate data

Reviewed-by: Matt Turner It might be a good idea to make the fs_reg(struct brw_reg) explicit to prevent this kind of mistake from happening. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] i965/fs: Use fs_reg for CS/VS atomics pixel mask immediate data

The brw_imm_ud will yield a HW_REG which then will introduce a barrier for certain optimization opportunities. No piglit regressions seen with gen8 (simd8vs). Suggested-by: Matt Turner Signed-off-by: Jordan Justen Cc: Matt Turner --- src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 ++-- 1 fi

Re: [Mesa-dev] [PATCH 23/23] main: Cosmetic changes to GetBufferSubData.

On 20/02/2015 19:58, Laura Ekstrand wrote: Ian has asked that this not be squashed. In fact, they were the same commit last time around on the ML. Ok. Sorry for the noise then :s On Fri, Feb 20, 2015 at 12:29 AM, Martin Peres > wrote: Please squash this co

Re: [Mesa-dev] [PATCH 11/23] main: Refactor ClearBuffer[Sub]Data.

On 20/02/2015 20:03, Laura Ekstrand wrote: This naming convention tries to match the corresponding DD table entry. There's a thread discussing the naming convention for external software fallback functions. Feel free to add your input to the discussion there :) Ack, no strong opinion here :

Re: [Mesa-dev] [PATCH 08/23] main: Add entry point for NamedBufferSubData.

On 20/02/2015 22:17, Laura Ekstrand wrote: That would make the diff easier to read, but it doesn't make sense to lay out the functions in that order in the file. GetBufferSubData is a download function and shouldn't be part of the upload function "group" in the file. Fair enough! That was a

Re: [Mesa-dev] [PATCH] nir: Fix the Mesa build without -DDEBUG.

Regardless of where DEBUG/NDEBUG is defined, it seems like we should do this anyway. Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] mesa: Have configure define NDEBUG, not mtypes.h.

mtypes.h had been defining NDEBUG (used by assert) if DEBUG was not defined. Confusing and bizarre that you don't get NDEBUG if you don't include mtypes.h. ... which is just what happened in commit bef38f62e. Let's let configure define this for us if not using --enable-debug. --- configure.ac

Re: [Mesa-dev] [PATCH] mesa: Have configure define NDEBUG, not mtypes.h.

On Fri, Feb 20, 2015 at 12:44 PM, Matt Turner wrote: > mtypes.h had been defining NDEBUG (used by assert) if DEBUG was not > defined. Confusing and bizarre that you don't get NDEBUG if you don't > include mtypes.h. > > ... which is just what happened in commit bef38f62e. > > Let's let configure de

[Mesa-dev] [PATCH] nir: Fix the Mesa build without -DDEBUG.

With -DDEBUG -UNDEBUG, this assert uses reg_state::stack_size, which doesn't exist, breaking the build: assert(state->states[index].index < state->states[index].stack_size); Switch it to ifndef NDEBUG, so the field will exist if the assertion actually generates code. Signed-off-by: Kenneth Graun

Re: [Mesa-dev] [PATCH 1/5] nir: Add a couple of simplifications of csel operations.

The series is Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] drivers/x11: add gallium include dirs to Makefile.am

Fixes xlib driver build after e8c5cbfd921680c. --- src/mesa/drivers/x11/Makefile.am | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/x11/Makefile.am b/src/mesa/drivers/x11/Makefile.am index 76a7cd4..c0596f8 100644 --- a/src/mesa/drivers/x11/Makefile.am +++ b/src/mesa/drivers/

Re: [Mesa-dev] [PATCH 08/23] main: Add entry point for NamedBufferSubData.

That would make the diff easier to read, but it doesn't make sense to lay out the functions in that order in the file. GetBufferSubData is a download function and shouldn't be part of the upload function "group" in the file. On Fri, Feb 20, 2015 at 2:28 AM, Martin Peres wrote: > On 12/02/2015 0

Re: [Mesa-dev] [PATCH 2/3] i965/fs/nir: Optimize (gl_FrontFacing ? x : y) where x and y are ±1.0.

On Fri, Feb 20, 2015 at 11:54 AM, Eric Anholt wrote: > I wanted patch #1 to land, so I took a look at this one :) Thanks! :) > Matt Turner writes: >> + if (brw->gen >= 6) { >> + /* Bit 15 of g0.0 is 0 if the polygon is front facing. */ >> + fs_reg g0 = fs_reg(retype(brw_vec1_grf(0,

Re: [Mesa-dev] [PATCH 2/2] r600g: add doubles support for CAYMAN

On Fri, Feb 20, 2015 at 3:07 PM, Ilia Mirkin wrote: > On Thu, Feb 19, 2015 at 9:59 PM, Glenn Kennard > wrote: >>> + if ((write_mask & 0x3) != 0x3 && >>> + (write_mask & 0xc) != 0xc) { >>> + fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", >>> write_mask); >>>

Re: [Mesa-dev] [PATCH 2/2] r600g: add doubles support for CAYMAN

On Thu, Feb 19, 2015 at 9:59 PM, Glenn Kennard wrote: >> + if ((write_mask & 0x3) != 0x3 && >> + (write_mask & 0xc) != 0xc) { >> + fprintf(stderr, "illegal writemask for 64-bit: 0x%x\n", >> write_mask); >> + return -1; >> + } I think I noted this

[Mesa-dev] [PATCH 4/5] nir: Collapse repeated bcsels on the same argument.

vc4 results: total instructions in shared programs: 39881 -> 39794 (-0.22%) instructions in affected programs: 6302 -> 6215 (-1.38%) --- src/glsl/nir/nir_opt_algebraic.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/glsl/nir/nir_opt_algebraic.py b/src/glsl/nir/nir_opt_algebraic.py

[Mesa-dev] [PATCH 5/5] nir: Generalize the optimization of subs of subs from 0.

I initially wrote this based on the "(('fneg', ('fneg', a)), a)" above, but we can generalize it and make it more potentially useful. In the specific original case of a 0 for our new 'a' argument, it'll get further algebraic optimization once the 0 is an argument to the new add. No shader-db effe

[Mesa-dev] [PATCH 3/5] nir: When faced with a csel on !condition, just flip the arguments.

total NIR instructions in shared programs: 39426 -> 39411 (-0.04%) NIR instructions in affected programs: 3748 -> 3733 (-0.40%) --- src/glsl/nir/nir_opt_algebraic.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/glsl/nir/nir_opt_algebraic.py b/src/glsl/nir/nir_opt_algebraic.py index

[Mesa-dev] [PATCH 2/5] nir: Allow nir_opt_algebraic to see booleanness through &&, ||, !.

We have some useful optimizations to drop things like 'ine a, 0' on a boolean argument, but if 'a' came from logical operations on bools, it couldn't tell. These kinds of constructs appear as a result of TGSI->NIR quite frequently (at least with if flattening), so being a little more aggressive in

[Mesa-dev] [PATCH 1/5] nir: Add a couple of simplifications of csel operations.

vc4 was already cleaning these up, but it does shave 4 NIR instructions in shader-db. --- src/glsl/nir/nir_opt_algebraic.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/glsl/nir/nir_opt_algebraic.py b/src/glsl/nir/nir_opt_algebraic.py index b0c206a..dd4557f 100644 --- a/src/glsl/nir

Re: [Mesa-dev] [PATCH 2/3] i965/fs/nir: Optimize (gl_FrontFacing ? x : y) where x and y are ±1.0.

I wanted patch #1 to land, so I took a look at this one :) Matt Turner writes: > + if (brw->gen >= 6) { > + /* Bit 15 of g0.0 is 0 if the polygon is front facing. */ > + fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W)); > + > + /* For (gl_FrontFacing ? 1.0 : -1

[Mesa-dev] [PATCH 6/7] i965: Fix variable indexing of UBO arrays under non-uniform control flow.

ARB_gpu_shader5 requires UBO array indexing expressions to be dynamically uniform, this however doesn't have any implications on the control flow that leads to the evaluation of that expression being uniform. Use emit_uniformize() to obtain an arbitrary live value from the binding table index calc

[Mesa-dev] [PATCH 2/7] i965: Perform basic optimizations on the BROADCAST opcode.

--- src/mesa/drivers/dri/i965/brw_fs.cpp| 15 +++ src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 1 + src/mesa/drivers/dri/i965/brw_fs_cse.cpp| 1 + src/mesa/drivers/dri/i965/brw_ir_fs.h | 7 +++ src/mesa/drivers/d

[Mesa-dev] [PATCH 3/7] i965: Introduce the FIND_LIVE_CHANNEL pseudo-opcode.

This instruction calculates the index of an arbitrary channel enabled in the current execution mask. It's expected to be used as input for the BROADCAST opcode, but it's implemented as a separate instruction rather than being baked into BROADCAST because FIND_LIVE_CHANNEL has no dependencies so it

[Mesa-dev] [PATCH 4/7] i965: Perform basic optimizations on the FIND_LIVE_CHANNEL opcode.

--- src/mesa/drivers/dri/i965/brw_fs.cpp | 49 ++ src/mesa/drivers/dri/i965/brw_fs.h | 1 + src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 1 + src/mesa/drivers/dri/i965/brw_vec4.cpp | 41 + src/mesa/drivers/dri/i965/brw_vec4.h

Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().

On Fri, Feb 20, 2015 at 2:43 PM, Francisco Jerez wrote: > Jason Ekstrand writes: > > > One more comment here... This particularly regards your plan of > separating > > it into "things that match the destination" and "other things" and not > copy > > prop uniforms or immediates into the "other t

[Mesa-dev] [PATCH 1/7] i965: Introduce the BROADCAST pseudo-opcode.

The BROADCAST instruction picks the channel from its first source given by an index passed in as second source. This will be used in situations where all channels from the same SIMD thread have to agree on the value of something, e.g. a surface binding table index. --- src/mesa/drivers/dri/i965/b

[Mesa-dev] [PATCH 5/7] i965: Define helper function to copy an arbitrary live component from some register.

--- src/mesa/drivers/dri/i965/brw_fs.h | 2 ++ src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 12 src/mesa/drivers/dri/i965/brw_vec4.h | 3 +++ src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 11 +++ 4 files changed, 28 insertions(+) diff --git a/sr

[Mesa-dev] [PATCH 7/7] i965: Fix variable indexing of sampler arrays under non-uniform control flow.

ARB_gpu_shader5 requires sampler array indexing expressions to be dynamically uniform, this however doesn't have any implications on the control flow that leads to the evaluation of that expression being uniform. Use emit_uniformize() to obtain an arbitrary live value from the binding table index

Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().

Jason Ekstrand writes: > One more comment here... This particularly regards your plan of separating > it into "things that match the destination" and "other things" and not copy > prop uniforms or immediates into the "other things". There is another case > we need to handle. On older gens (SNB

Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().

Jason Ekstrand writes: > On Fri, Feb 20, 2015 at 1:09 PM, Francisco Jerez > wrote: > >> Jason Ekstrand writes: >> >> > On Fri, Feb 20, 2015 at 4:11 AM, Francisco Jerez >> > wrote: >> > >> >> Jason Ekstrand writes: >> >> >> >> > I'm still a little pensive. But >> >> > >> >> > Reviewed-by: Jas

Re: [Mesa-dev] [PATCH 12/32] i965/fs: Fix lower_load_payload() to take into account stride in the metadata guess.

Jason Ekstrand writes: > Where are you getting a destination stride in a load_payload? The whole > point of load_payload was to remove partial writes so this seems to go > against everything it's intended for. > --Jason Yeah, maybe... This case was triggered by some of my image_load_store code

Re: [Mesa-dev] [PATCH 13/23] main: Minor whitespace fixes in ClearNamedBuffer[Sub]Data.

Again, Ian requested that this be a separate commit. On Fri, Feb 20, 2015 at 6:22 AM, Martin Peres wrote: > Please squash this in the previous commit (with git rebase -i). > > > On 12/02/2015 04:05, Laura Ekstrand wrote: > >> --- >> src/mesa/main/bufferobj.c | 4 ++-- >> src/mesa/main/buffero

[Mesa-dev] [Bug 67676] Transparent windows no longer work

https://bugs.freedesktop.org/show_bug.cgi?id=67676 Chad Versace changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|mesa-dev@list

Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().

One more comment here... This particularly regards your plan of separating it into "things that match the destination" and "other things" and not copy prop uniforms or immediates into the "other things". There is another case we need to handle. On older gens (SNB maybe?) the SIMD16 FB write mess

Re: [Mesa-dev] [PATCH 1/6] gallivm: fix uninitialized-variable warnings

On 02/20/2015 12:22 PM, Marek Olšák wrote: From: Marek Olšák --- src/gallium/auxiliary/gallivm/lp_bld_init.c | 2 +- src/gallium/auxiliary/gallivm/lp_bld_sample.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gall

[Mesa-dev] [PATCH 6/6] vbo: fix an unitialized-variable warning

From: Marek Olšák It looks like a bug to me. Cc: 10.5 10.4 10.3 --- src/mesa/vbo/vbo_attrib_tmp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/vbo/vbo_attrib_tmp.h b/src/mesa/vbo/vbo_attrib_tmp.h index ec66934..0c44540 100644 --- a/src/mesa/vbo/vbo_attrib_tmp.h +++ b/src/mesa/v

[Mesa-dev] [PATCH 3/6] targets/d3dadapter9: remove an unused variable

From: Marek Olšák --- src/gallium/targets/d3dadapter9/drm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/targets/d3dadapter9/drm.c b/src/gallium/targets/d3dadapter9/drm.c index cb0c48f..ec594fd 100644 --- a/src/gallium/targets/d3dadapter9/drm.c +++ b/src/galli

[Mesa-dev] [PATCH 5/6] gallium/sw/kms: fix a type-mismatch warning

From: Marek Olšák --- src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c index 781818a..ce3de78 100644 --- a/src/gallium/winsy

[Mesa-dev] [PATCH 2/6] tgsi: fix type-mismatch warning

From: Marek Olšák --- src/gallium/auxiliary/tgsi/tgsi_text.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c b/src/gallium/auxiliary/tgsi/tgsi_text.c index 5069d13..b6b3585 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_text.c +++ b/src/g

[Mesa-dev] [PATCH 1/6] gallivm: fix uninitialized-variable warnings

From: Marek Olšák --- src/gallium/auxiliary/gallivm/lp_bld_init.c | 2 +- src/gallium/auxiliary/gallivm/lp_bld_sample.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c index b9593d

[Mesa-dev] [PATCH 4/6] gallium/sw/kms: don't redefine DEBUG

From: Marek Olšák --- src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c index ed34dfa..781818a 100644 --- a/sr

Re: [Mesa-dev] [PATCH 11/32] i965/fs: Fix lower_load_payload() to take into account non-zero reg_offset.

Reviewed-by: Jason Ekstrand On Fri, Feb 6, 2015 at 9:42 AM, Francisco Jerez wrote: > Fixes metadata guess when instructions in the program specify a > destination register with non-zero reg_offset and when the payload of > a LOAD_PAYLOAD spans several registers. > --- > src/mesa/drivers/dri/i9

Re: [Mesa-dev] [PATCH 1/6] gallium: add some more double opcodes to avoid unnecessary lowering

On Fri, Feb 20, 2015 at 9:37 AM, Roland Scheidegger wrote: > Just some minor nits. > > Am 20.02.2015 um 00:52 schrieb Ilia Mirkin: >> Signed-off-by: Ilia Mirkin >> --- >> src/gallium/auxiliary/tgsi/tgsi_info.c | 5 >> src/gallium/docs/source/tgsi.rst | 39 >>

Re: [Mesa-dev] [PATCH 12/32] i965/fs: Fix lower_load_payload() to take into account stride in the metadata guess.

Where are you getting a destination stride in a load_payload? The whole point of load_payload was to remove partial writes so this seems to go against everything it's intended for. --Jason On Fri, Feb 6, 2015 at 9:42 AM, Francisco Jerez wrote: > --- > src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +

Re: [Mesa-dev] [PATCH 13/32] i965/fs: Fix lower_load_payload() not to use an incorrect half for immediates and uniforms.

Yeah... More proof that the lower_load_payload code is plenty bogus... Reviewed-by: Jason Ekstrand On Fri, Feb 6, 2015 at 9:42 AM, Francisco Jerez wrote: > --- > src/mesa/drivers/dri/i965/brw_fs.cpp | 8 > 1 file changed, 8 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/brw

Re: [Mesa-dev] [PATCH 5/7] i965/fs: Less broken handling of force_writemask_all in lower_load_payload().

Reviewed-by: Jason Ekstrand On Sat, Jan 17, 2015 at 6:04 PM, Francisco Jerez wrote: > It's perfectly fine to read the second half of a register written with > force_writemask_all from a first half MOV instruction or vice versa, and > lower_load_payload shouldn't mark the whole MOV as belonging

Re: [Mesa-dev] glCompressedTex(Sub)Image(2,3) on mapped PBOs

On 02/20/2015 08:13 AM, Eduardo Lima Mitev wrote: > Hello, > > While working on the following dEQP failing tests I ran into an issue > that I think deserves clarification from more experienced people: > > dEQP-GLES3.functional.negative_api.texture.compressedteximage2d_invalid_buffer_target > dEQP

Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().

On Fri, Feb 20, 2015 at 1:09 PM, Francisco Jerez wrote: > Jason Ekstrand writes: > > > On Fri, Feb 20, 2015 at 4:11 AM, Francisco Jerez > > wrote: > > > >> Jason Ekstrand writes: > >> > >> > I'm still a little pensive. But > >> > > >> > Reviewed-by: Jason Ekstrand > >> > > >> Thanks. > >> >

Re: [Mesa-dev] [PATCH 03/16] main: fix the validation of the number of samples

On Mon, Feb 16, 2015 at 9:13 AM, Martin Peres wrote: > Maybe this should be the job of the dispatch layer. > > Signed-off-by: Martin Peres > --- > src/mesa/main/multisample.c | 9 + > 1 file changed, 9 insertions(+) > > diff --git a/src/mesa/main/multisample.c b/src/mesa/main/multisample

Re: [Mesa-dev] [PATCH] i965/skl: Use 1 register for uniform pull constant payload

On Friday, February 20, 2015 10:33:18 AM Ben Widawsky wrote: > On Fri, Feb 20, 2015 at 03:34:21AM -0800, Kenneth Graunke wrote: > > On Thursday, February 19, 2015 10:48:08 PM Ben Widawsky wrote: > > > When under dispatch_width=16 the previous code would allocate 2 registers > > > for > > > the pay

[Mesa-dev] [PATCH v2] glsl: add double support for packing varyings

Doubles are always packed, but a single double will never cross a slot boundary -- single slots can still be wasted in some situations. Signed-off-by: Ilia Mirkin --- Packing *all* doubles is a bit of a hack... we shouldn't need to do it for dvec2/dvec4. And yet, here we are. This means that set

Re: [Mesa-dev] [PATCH 03/16] main: fix the validation of the number of samples

Please provide a page number and a section title in your spec comment. Thanks. On Mon, Feb 16, 2015 at 6:13 AM, Martin Peres wrote: > Maybe this should be the job of the dispatch layer. > > Signed-off-by: Martin Peres > --- > src/mesa/main/multisample.c | 9 + > 1 file changed, 9 inse

Re: [Mesa-dev] [PATCH 04/16] main: Added entry point for glCreateTransformFeedbacks

Looks good to me Reviewed-by: Laura Ekstrand On Mon, Feb 16, 2015 at 6:13 AM, Martin Peres wrote: > v2: Review from Laura Ekstrand > - generate the name of the gl method once > - shorten some lines to stay in the 78 chars limit > > v3: Review from Fredrik Höglund > - rename gl_mthd_name to fu

Re: [Mesa-dev] [PATCH] i965/skl: Use 1 register for uniform pull constant payload

On Fri, Feb 20, 2015 at 03:34:21AM -0800, Kenneth Graunke wrote: > On Thursday, February 19, 2015 10:48:08 PM Ben Widawsky wrote: > > When under dispatch_width=16 the previous code would allocate 2 registers > > for > > the payload when only one is needed. This manifested itself through bugs on >

Re: [Mesa-dev] [PATCH] svga: add missing padding to SVGA3dSize

On Fri, Feb 20, 2015 at 09:22:20AM +, Van Der Wath, DanielX J wrote: > From: Daniel van der Wath > > The kernel side equivalent of struct SVGA3dSize (struct drm_vmw_size) has an > extra padding word that SVGA3dSize lacks. This was causing data to be written > past the end of "size" in vmw_drm

Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().

Jason Ekstrand writes: > On Fri, Feb 20, 2015 at 4:11 AM, Francisco Jerez > wrote: > >> Jason Ekstrand writes: >> >> > I'm still a little pensive. But >> > >> > Reviewed-by: Jason Ekstrand >> > >> Thanks. >> >> > Now for a little aside. I have come to the conclusion that I made a >> grave >>

Re: [Mesa-dev] [PATCH 11/23] main: Refactor ClearBuffer[Sub]Data.

This naming convention tries to match the corresponding DD table entry. There's a thread discussing the naming convention for external software fallback functions. Feel free to add your input to the discussion there :) On Fri, Feb 20, 2015 at 6:18 AM, Martin Peres wrote: > On 12/02/2015 04:05,

Re: [Mesa-dev] [PATCH] nir: Copy-propagate vecN operations that are actually moves

On Feb 20, 2015 9:27 AM, "Matt Turner" wrote: > > On Fri, Feb 20, 2015 at 9:23 AM, Jason Ekstrand wrote: > > > > > > On Thu, Feb 19, 2015 at 11:03 PM, Matt Turner wrote: > >> > >> On Thu, Feb 19, 2015 at 11:01 PM, Connor Abbott > >> wrote: > >> > I agree with Ken that the regressions are small

Re: [Mesa-dev] [PATCH 23/23] main: Cosmetic changes to GetBufferSubData.

Ian has asked that this not be squashed. In fact, they were the same commit last time around on the ML. On Fri, Feb 20, 2015 at 12:29 AM, Martin Peres wrote: > Please squash this commit with the one introducing GetBufferSubData. > > It should be pretty easy to do with git rebase -i :) > > > On

Re: [Mesa-dev] [PATCH] nir: Copy-propagate vecN operations that are actually moves

On Fri, Feb 20, 2015 at 9:23 AM, Jason Ekstrand wrote: > > > On Thu, Feb 19, 2015 at 11:03 PM, Matt Turner wrote: >> >> On Thu, Feb 19, 2015 at 11:01 PM, Connor Abbott >> wrote: >> > I agree with Ken that the regressions are small enough, and it seems >> > they're mostly stuff we can prevent by

Re: [Mesa-dev] [PATCH] nir: Copy-propagate vecN operations that are actually moves

On Thu, Feb 19, 2015 at 11:03 PM, Matt Turner wrote: > On Thu, Feb 19, 2015 at 11:01 PM, Connor Abbott > wrote: > > I agree with Ken that the regressions are small enough, and it seems > > they're mostly stuff we can prevent by being smarter when doing the > > sel peephole, so it seems like the

Re: [Mesa-dev] [PATCH 10/32] i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().

On Fri, Feb 20, 2015 at 4:11 AM, Francisco Jerez wrote: > Jason Ekstrand writes: > > > I'm still a little pensive. But > > > > Reviewed-by: Jason Ekstrand > > > Thanks. > > > Now for a little aside. I have come to the conclusion that I made a > grave > > mistake when I did the LOAD_PAYLOAD st

Re: [Mesa-dev] glCompressedTex(Sub)Image(2,3) on mapped PBOs

On Fri, Feb 20, 2015 at 8:13 AM, Eduardo Lima Mitev wrote: > Hello, > > While working on the following dEQP failing tests I ran into an issue > that I think deserves clarification from more experienced people: > > > dEQP-GLES3.functional.negative_api.texture.compressedteximage2d_invalid_buffer_ta

Re: [Mesa-dev] [PATCH 1/7] mesa: Add gallium include dirs to more parts of the tree.

On 13/02/15 00:49, Eric Anholt wrote: Jose Fonseca writes: Thanks for doing this. I appreciate it. I have no objection with the series. I'm happy to see more reuse. We can always move things around later, and it will be much easier when then are less entangled/duplicated. We'll need to upd

Re: [Mesa-dev] [PATCH 4/7] mesa: Make bitset.h not rely on Mesa-specific types and functions.

On 12/02/15 00:48, Eric Anholt wrote: Note that we can't use u_math.h's align() because it's a function instead of a macro, while BITSET_DECLARE needs a constant expression for nouveau's usage in global declarations. --- src/mesa/main/bitset.h | 7 +++ 1 file changed, 3 insertions(+), 4 de

[Mesa-dev] glCompressedTex(Sub)Image(2,3) on mapped PBOs

Hello, While working on the following dEQP failing tests I ran into an issue that I think deserves clarification from more experienced people: dEQP-GLES3.functional.negative_api.texture.compressedteximage2d_invalid_buffer_target dEQP-GLES3.functional.negative_api.texture.compressedtexsubimage2d_i

Re: [Mesa-dev] [PATCH v5] mesa: use fi_type in vertex attribute code

On 02/19/2015 11:42 AM, marius.pre...@intel.com wrote: From: Marius Predut For 32-bit builds, floating point operations use x86 FPU registers, not SSE registers. If we're actually storing an integer in a float variable, the value might get modified when written to memory. This patch changes t

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