As a heads-up, with this patch piglit fails the test for current Mesa.
But I'm about to send another series of patches for dEQP tests which
include a fix in Mesa for this issue.
The piglit test in question is:
bin/arb_occlusion_query2-api -auto -fbo
Eduardo
On 02/10/2015 08:48 AM, Eduardo Lima
From: Chris Forbes
This should cover all platforms prior to Skylake.
Signed-off-by: Chris Forbes
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_context.c | 4
src/mesa/drivers/dri/i965/brw_context.h | 4
src/mesa/drivers/dri/i965/brw_device_info.c | 36 ++
From the OpenGL ES 3.0.0 spec, section "2.13. ASYNCHRONOUS QUERIES",
page 82:
"BeginQuery generates an INVALID_OPERATION error if any of the
following conditions hold: [...]; id is the name of an existing
query object whose type does not match target; [...]
OpenGL 3.3 spec has simil
This is mostly thanks to Connor. The idea is to do a depth-first search
that computes pre and post indices for all the blocks. We can then figure
out if one block dominates another in constant time by two simple
comparison operations.
Reviewed-by: Connor Abbott
---
src/glsl/nir/nir.h
Previously, if you remved a CF node that still had instructions in it, none
of the use/def information from those instructions would get cleaned up.
Also, we weren't removing if statements from the if_uses of the
corresponding register or SSA def. This commit fixes both of these
problems
---
src/
v2: Do GCM after dead code elimination
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index da81b61..a0e6b1d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cp
This lets us be slightly more efficient by not walking the CFG extra times.
Also, it may make it easier to ensure that GVN happens on only unpinned
instructions.
---
src/glsl/nir/nir_opt_gcm.c | 62 +++---
1 file changed, 25 insertions(+), 37 deletions(-)
d
---
src/glsl/nir/nir_from_ssa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/nir/nir_from_ssa.c b/src/glsl/nir/nir_from_ssa.c
index 3625237..7c50095 100644
--- a/src/glsl/nir/nir_from_ssa.c
+++ b/src/glsl/nir/nir_from_ssa.c
@@ -272,7 +272,7 @@ get_parallel_copy_at_e
Being able to find the least common anscestor in the dominance tree is a
useful thing that we may want to do in other passes. In particular, we
need it for GCM.
v2: Handle NULL inputs by returning the other block
---
src/glsl/nir/nir.h | 2 ++
src/glsl/nir/nir_dominance.c | 22 +++
Reviewed-by: Connor Abbott
---
src/glsl/nir/nir_from_ssa.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/src/glsl/nir/nir_from_ssa.c b/src/glsl/nir/nir_from_ssa.c
index 2e7add3..3625237 100644
--- a/src/glsl/nir/nir_from_ssa.c
+++ b/src/glsl/nir/nir_from_ssa.c
@@ -5
Reviewed-by: Connor Abbott
---
src/glsl/nir/nir_validate.c | 87 -
1 file changed, 79 insertions(+), 8 deletions(-)
diff --git a/src/glsl/nir/nir_validate.c b/src/glsl/nir/nir_validate.c
index 13010ae..a3fe9d6 100644
--- a/src/glsl/nir/nir_validate.c
+
Reviewed-by: Connor Abbott
---
src/glsl/nir/nir_validate.c | 62 -
1 file changed, 44 insertions(+), 18 deletions(-)
diff --git a/src/glsl/nir/nir_validate.c b/src/glsl/nir/nir_validate.c
index a34a017..13010ae 100644
--- a/src/glsl/nir/nir_validate.c
---
src/glsl/nir/nir_opt_gcm.c | 95 --
1 file changed, 49 insertions(+), 46 deletions(-)
diff --git a/src/glsl/nir/nir_opt_gcm.c b/src/glsl/nir/nir_opt_gcm.c
index d48518b..57328be 100644
--- a/src/glsl/nir/nir_opt_gcm.c
+++ b/src/glsl/nir/nir_opt_gcm.
v2 Jason Ekstrand :
- Use nir_dominance_lca for computing least common anscestors
- Use the block index for comparing dominance tree depths
- Pin things that do partial derivatives
---
src/glsl/Makefile.sources | 1 +
src/glsl/nir/nir.h | 2 +
src/glsl/nir/nir_opt_gcm.c | 501 +
---
This replaces the original patch 10 even though they are very different.
src/glsl/nir/nir.h | 6 --
src/glsl/nir/nir_opt_dce.c | 14 +-
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index f4056f4..6ac1bfd 10064
This is both simpler and more correct. The old code didn't properly index
load_const instructions.
Reviewed-by: Connor Abbott
---
src/glsl/nir/nir.c | 26 --
1 file changed, 4 insertions(+), 22 deletions(-)
diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c
index 10e6
---
src/glsl/nir/nir.h | 28 ++--
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 5d84343..f4056f4 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -416,15 +416,23 @@ typedef struct {
} nir_instr;
s
On Mon, Feb 9, 2015 at 3:31 PM, Connor Abbott wrote:
> On Mon, Feb 9, 2015 at 6:11 PM, Jason Ekstrand
> wrote:
> >
> >
> > On Mon, Feb 9, 2015 at 12:01 PM, Connor Abbott
> wrote:
> >>
> >> So last time you posted this, I had some suggestions but I realized
> >> that in light of the fact that we
On Mon, Feb 9, 2015 at 2:31 PM, Connor Abbott wrote:
> On Mon, Feb 9, 2015 at 5:04 PM, Jason Ekstrand
> wrote:
> >
> >
> > On Mon, Feb 9, 2015 at 3:01 PM, Connor Abbott
> wrote:
> >>
> >> So last time you posted this, I had some suggestions but I realized
> >> that in light of the fact that we
Right, the function isn't even defined in that scope, tired me shouldn't
even try to write code ;-)
On 10.02.2015 04:48, Jan Vesely wrote:
On Tue, 2015-02-10 at 04:43 +0100, Tobias Klausmann wrote:
Signed-off-by: Tobias Klausmann
---
src/gallium/state_trackers/nine/nine_pipe.h | 2 +-
1 fi
On Tue, 2015-02-10 at 04:43 +0100, Tobias Klausmann wrote:
> Signed-off-by: Tobias Klausmann
> ---
> src/gallium/state_trackers/nine/nine_pipe.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/state_trackers/nine/nine_pipe.h
> b/src/gallium/state_trackers/ni
On Mon, Feb 9, 2015 at 10:43 PM, Tobias Klausmann
wrote:
> Signed-off-by: Tobias Klausmann
> ---
> src/gallium/state_trackers/nine/nine_pipe.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/state_trackers/nine/nine_pipe.h
> b/src/gallium/state_trackers/nine
Signed-off-by: Tobias Klausmann
---
src/gallium/state_trackers/nine/nine_pipe.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/state_trackers/nine/nine_pipe.h
b/src/gallium/state_trackers/nine/nine_pipe.h
index 17844d5..3480aad 100644
--- a/src/gallium/state_trac
On Mon, Feb 9, 2015 at 7:29 PM, Marek Olšák wrote:
> Hi Christian,
>
> What hardware is this supported on? SI and later? Or even r600? r300?
Theoretically r300 and newer hardware, however, the kernel currently
only allows it on r600 and newer since we never tested it on r300
class hardware.
Alex
On Mon, Feb 9, 2015 at 6:00 PM, Kenneth Graunke wrote:
> On Wednesday, February 04, 2015 08:21:27 PM Matt Turner wrote:
>> total instructions in shared programs: 5764176 -> 5763808 (-0.01%)
>> instructions in affected programs: 25121 -> 24753 (-1.46%)
>> helped:
On Mon, Feb 9, 2015 at 5:54 PM, Kenneth Graunke wrote:
> On Wednesday, February 04, 2015 08:21:21 PM Matt Turner wrote:
>> ---
>> src/mesa/drivers/dri/i965/brw_cfg.cpp | 10 ++
>> src/mesa/drivers/dri/i965/brw_cfg.h | 1 +
>> 2 files changed, 11 insertions(+)
>>
>> diff --git a/src/mes
On Wednesday, February 04, 2015 08:21:27 PM Matt Turner wrote:
> total instructions in shared programs: 5764176 -> 5763808 (-0.01%)
> instructions in affected programs: 25121 -> 24753 (-1.46%)
> helped:164
> HURT: 2
> ---
> src/m
On Wednesday, February 04, 2015 08:21:21 PM Matt Turner wrote:
> ---
> src/mesa/drivers/dri/i965/brw_cfg.cpp | 10 ++
> src/mesa/drivers/dri/i965/brw_cfg.h | 1 +
> 2 files changed, 11 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_cfg.cpp
> b/src/mesa/drivers/dri/i965/b
On Mon, Feb 9, 2015 at 5:50 PM, Kenneth Graunke wrote:
> On Wednesday, February 04, 2015 08:21:19 PM Matt Turner wrote:
>> ---
>> src/mesa/drivers/dri/i965/brw_cfg.cpp | 68
>> +-
>> src/mesa/drivers/dri/i965/brw_cfg.h| 7 ++-
>> .../drivers/dri/
On Wednesday, February 04, 2015 08:21:19 PM Matt Turner wrote:
> ---
> src/mesa/drivers/dri/i965/brw_cfg.cpp | 68
> +-
> src/mesa/drivers/dri/i965/brw_cfg.h| 7 ++-
> .../drivers/dri/i965/brw_dead_control_flow.cpp | 5 +-
> 3 files changed,
This code provides for an on-disk cache of objects. Objects are stored
and retrieved via names that are arbitrary 20-byte sequences,
(intended to be SHA-1 hashes of something identifying for the
content). The directory used for the cache can be specified by means
of environment variables in the fol
https://bugs.freedesktop.org/show_bug.cgi?id=88962
Park, Jeongmin changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
On Mon, Feb 9, 2015 at 6:44 PM, Emil Velikov wrote:
> Hi Sedat,
>
> On 07/02/15 22:42, Sedat Dilek wrote:
>> [ Please CC me I am not subscribed to mesa-dev and llvmdev MLs ]
>>
>> Hi,
>>
>> I already reported this when playing 1st time with my llvm-toolchain
>> v3.6.0rc2 and mesa v10.3.7 [1].
>> T
On Mon, Feb 9, 2015 at 9:51 PM, Jose Fonseca wrote:
> On 09/02/15 17:44, Emil Velikov wrote:
>>
>> Hi Sedat,
>>
>> On 07/02/15 22:42, Sedat Dilek wrote:
>>>
>>> [ Please CC me I am not subscribed to mesa-dev and llvmdev MLs ]
>>>
>>> Hi,
>>>
>>> I already reported this when playing 1st time with m
On Mon, Feb 9, 2015 at 6:30 PM, Emil Velikov wrote:
> On 07/02/15 21:44, Sedat Dilek wrote:
>> Hi,
>>
>> I was building mesa v10.4.4 with my llvm-toolchain v3.6.0rc2.
>>
>> My build breaks like this...
>>
>> ...
>>
>> Please cherry-pick...
>>
>> commit ef7e0b39a24966526b102643523feac765771842
>> "
On Friday, January 30, 2015 06:33:28 PM Matt Turner wrote:
> Same as commit 3654b6d4 to the fs backend.
>
> total instructions in shared programs: 5945788 -> 5945787 (-0.00%)
> instructions in affected programs: 36 -> 35 (-2.78%)
> helped:1
> ---
> src/mesa/dri
Hi Christian,
What hardware is this supported on? SI and later? Or even r600? r300?
Thanks,
Marek
On Thu, Feb 5, 2015 at 6:34 PM, Christian König wrote:
> From: Christian König
>
> Signed-off-by: Christian König
> ---
> src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 102
>
For some reason, the v2 version of this disappeared from my inbox, so I'll say
Reviewed-by: Connor Abbott
I'm not convinced this is enough for when we optimize constant
if-statement conditions, but I'll leave that be for now.
On Thu, Feb 5, 2015 at 5:28 PM, Jason Ekstrand wrote:
> Previously,
https://bugs.freedesktop.org/show_bug.cgi?id=89043
--- Comment #3 from Brian Paul ---
Try reconfiguring with --enable-glx-tls and rebuilding.
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the bug.
___
On Mon, Feb 9, 2015 at 6:11 PM, Jason Ekstrand wrote:
>
>
> On Mon, Feb 9, 2015 at 12:01 PM, Connor Abbott wrote:
>>
>> So last time you posted this, I had some suggestions but I realized
>> that in light of the fact that we want to do value numbering, it
>> didn't seem like my suggestions were a
On Mon, Feb 9, 2015 at 12:01 PM, Connor Abbott wrote:
> So last time you posted this, I had some suggestions but I realized
> that in light of the fact that we want to do value numbering, it
> didn't seem like my suggestions were any good. But now that I've
> thought about it a little bit, it see
On Mon, Feb 9, 2015 at 5:04 PM, Jason Ekstrand wrote:
>
>
> On Mon, Feb 9, 2015 at 3:01 PM, Connor Abbott wrote:
>>
>> So last time you posted this, I had some suggestions but I realized
>> that in light of the fact that we want to do value numbering, it
>> didn't seem like my suggestions were an
---
src/glsl/nir/nir_lower_phis_to_scalar.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/glsl/nir/nir_lower_phis_to_scalar.c
b/src/glsl/nir/nir_lower_phis_to_scalar.c
index 3bb5cc7..7cd93ea 100644
--- a/src/glsl/nir/nir_lower_phis_to_scalar.c
+++ b/src/glsl/nir/ni
https://bugs.freedesktop.org/show_bug.cgi?id=89043
--- Comment #2 from Aditya Atluri ---
It came back!
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the bug.
___
mesa-dev mailing list
mesa-dev@lis
https://bugs.freedesktop.org/show_bug.cgi?id=89043
Aditya Atluri changed:
What|Removed |Added
Status|RESOLVED|REOPENED
Resolution|NOTABUG
On Mon, Feb 9, 2015 at 7:05 AM, Eero Tamminen wrote:
> Hi,
>
> On 02/05/2015 06:21 AM, Matt Turner wrote:
>>
>> total instructions in shared programs: 5895414 -> 5747578 (-2.51%)
>> instructions in affected programs: 3618111 -> 3470275 (-4.09%)
>> helped:20492
>
https://bugs.freedesktop.org/show_bug.cgi?id=89043
Aditya Atluri changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=89043
--- Comment #1 from Aditya Atluri ---
Hi,
I re-installed Ubuntu 14.04.1 and did not check "install updates" during
installation.
Install and Upgrade all the packages.
sudo apt-get install freeglut3-dev build-essential libx11-dev libxmu-dev
li
On Mon, Feb 9, 2015 at 2:06 PM, Jason Ekstrand wrote:
> Wow... I need to learn to read... I think we actually want || and ==.
Feel free to take it over.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listin
On Mon, Feb 9, 2015 at 4:54 PM, Matt Turner wrote:
> On Mon, Feb 9, 2015 at 1:45 PM, Jason Ekstrand
> wrote:
> > Sorry I didn't get to this earlier. It got lost in the backlog.
> >
> > Reviewed-by: Jason Ekstrand
> >
> > Out of curiosity, are there any shader-db results for this? If not,
> th
On Mon, Feb 9, 2015 at 3:01 PM, Connor Abbott wrote:
> So last time you posted this, I had some suggestions but I realized
> that in light of the fact that we want to do value numbering, it
> didn't seem like my suggestions were any good. But now that I've
> thought about it a little bit, it seem
On Mon, Feb 9, 2015 at 1:45 PM, Jason Ekstrand wrote:
> Sorry I didn't get to this earlier. It got lost in the backlog.
>
> Reviewed-by: Jason Ekstrand
>
> Out of curiosity, are there any shader-db results for this? If not, that's
> ok.
I didn't even know if this the correct fix, so no shader-
Sorry I didn't get to this earlier. It got lost in the backlog.
Reviewed-by: Jason Ekstrand
Out of curiosity, are there any shader-db results for this? If not, that's
ok.
--Jason
On Wed, Feb 4, 2015 at 3:19 PM, Matt Turner wrote:
> ---
> I don't know if this is right, but what we had befor
Reviewed-by: Jason Ekstrand
On Mon, Feb 9, 2015 at 4:42 PM, Kenneth Graunke
wrote:
> Printing instructions doesn't modify them, so we can mark the parameter
> const.
> ---
> src/glsl/nir/nir.h | 2 +-
> src/glsl/nir/nir_print.c | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
Printing instructions doesn't modify them, so we can mark the parameter
const.
---
src/glsl/nir/nir.h | 2 +-
src/glsl/nir/nir_print.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 4cb2e92..ceda977 100644
--- a/src/glsl
On Mon, Feb 9, 2015 at 12:26 PM, Francisco Jerez wrote:
> Some instruction bits don't have a mapping defined to any compacted
> instruction field. If they're ever set and we end up compacting the
> instruction they will be forced to zero. Avoid using compaction in such
> cases.
>
> v2: Align mul
On Monday, February 09, 2015 05:57:20 PM Neil Roberts wrote:
> Skylake+ doesn't support setting a depth buffer to a 1D surface but it
> does allow pretending it's a 2D texture with a height of 1 instead.
>
> This fixes the GL_DEPTH_COMPONENT_* tests of the copyteximage piglit
> test (and also seem
On Monday, February 09, 2015 07:15:28 PM Francisco Jerez wrote:
> It doesn't really improve locality of texture fetches, quite the
> opposite it's a waste of memory bandwidth and space due to tile
> alignment.
>
> v2: Check mt->logical_height0 instead of mt->target (Ken). Add short
> comment
On Monday, February 09, 2015 06:37:45 PM Francisco Jerez wrote:
> So the i965 driver can expose 32 image uniforms per shader stage.
> ---
> src/mesa/main/config.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/main/config.h b/src/mesa/main/config.h
> index 4ec4b
On 09/02/15 17:44, Emil Velikov wrote:
Hi Sedat,
On 07/02/15 22:42, Sedat Dilek wrote:
[ Please CC me I am not subscribed to mesa-dev and llvmdev MLs ]
Hi,
I already reported this when playing 1st time with my llvm-toolchain
v3.6.0rc2 and mesa v10.3.7 [1].
The issue still remains in mesa v10.
Some instruction bits don't have a mapping defined to any compacted
instruction field. If they're ever set and we end up compacting the
instruction they will be forced to zero. Avoid using compaction in such
cases.
v2: Align multiple lines of an expression to the same column. Change
conditi
So last time you posted this, I had some suggestions but I realized
that in light of the fact that we want to do value numbering, it
didn't seem like my suggestions were any good. But now that I've
thought about it a little bit, it seems to me like a better plan might
be to pull instructions out of
Matt Turner writes:
> On Mon, Feb 9, 2015 at 6:08 AM, Francisco Jerez wrote:
>> Some instruction bits don't have a mapping defined to any compacted
>> instruction field. If they're ever set and we end up compacting the
>> instruction they will be forced to zero. Avoid using compaction in such
On Fri, Feb 6, 2015 at 2:40 PM, Matt Turner wrote:
> 8 - Sent a question
> 9 - Like mine better?
> 10 - Looks wrong to me
> 11-13 - Asked Jason to review
> 14 - Asked for an example showing the problem
> 15-16 - R-b
> 17-18 - R-b - but wow, did we really hit these in practice?
> 19-20 - R-b
> 21 -
On 09/02/15 16:59, Jon TURNEY wrote:
On 06/02/2015 19:58, Matt Turner wrote:
On Fri, Feb 6, 2015 at 3:38 AM, Jonathan Gray wrote:
OpenBSD has ffs in libc but does not have ffsll so use the compiler
builtin. PIPE_OS_BSD isn't suitable here as FreeBSD has ffsll in libc.
Signed-off-by: Jonathan
Sounds well reasoned to me.
Reviewed-by: Matt Turner
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
v2: Store early fragment test mode in brw_wm_prog_data instead of
getting it from core mesa data structures (Ken).
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/brw_defines.h | 3 +++
src/mesa/drivers/dri/i965/brw_wm.c | 2 ++
src/mesa/drivers
On Mon, Feb 9, 2015 at 6:08 AM, Francisco Jerez wrote:
> Some instruction bits don't have a mapping defined to any compacted
> instruction field. If they're ever set and we end up compacting the
> instruction they will be forced to zero. Avoid using compaction in such
> cases.
>
> v2: Align mult
v2: Set the PS UAV-only bit on HSW (Ken).
---
src/mesa/drivers/dri/i965/brw_defines.h | 4
src/mesa/drivers/dri/i965/gen7_gs_state.c | 4 +++-
src/mesa/drivers/dri/i965/gen7_vs_state.c | 13 -
src/mesa/drivers/dri/i965/gen7_wm_state.c | 9 +
src/mesa/drivers/dri/i965/
On 02/07/2015 06:25 PM, Ilia Mirkin wrote:
> On Fri, Feb 6, 2015 at 3:02 AM, Ian Romanick wrote:
>>> @@ -708,6 +763,9 @@ ir_expression::constant_expression_value(struct
>>> hash_table *variable_context)
>>>case GLSL_TYPE_FLOAT:
>>> data.f[c] = op[0]->value.f[c] - floor(op[0]->va
Shaders with image uniforms may have side effects. Make sure that
fragment shader threads are dispatched if the shader has any image
uniforms.
v2: Use brw_stage_state::nr_image_params to find out if the shader has
image uniforms instead of checking core mesa data structures (Ken).
---
src/me
On 02/07/2015 05:25 PM, Matt Turner wrote:
> On Sat, Feb 7, 2015 at 5:16 PM, Ilia Mirkin wrote:
>> On Sat, Feb 7, 2015 at 8:10 PM, Ilia Mirkin wrote:
> diff --git a/src/glsl/ir.h b/src/glsl/ir.h
> index a0f48b2..6e7c654 100644
> --- a/src/glsl/ir.h
> +++ b/src/glsl/ir.h
> @@ -
On 02/08/2015 04:10 PM, Matt Turner wrote:
> The GLSL IR ir_binop_logic_* operations match the source language
> operators in that they only operate on scalars.
>
> In talking to Ilia, I realized that the vectorizer pass doesn't know
> about that, and so it will happily vectorize the vertex shader
Reviewed-by: Matt Turner
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Reviewed-by: Matt Turner
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
On Mon, Feb 09 2015, Jose Fonseca wrote:
> Just one more tweak to InterlockedExchangeAdd64 as per patch attached.
..
> With that u_test_atomic builds and passes for me both on 32 and
> 64bits.
Excellent. Thanks for the fix and for the testing report.
> Sorry for the delay. And thanks for your he
Skylake+ doesn't support setting a depth buffer to a 1D surface but it
does allow pretending it's a 2D texture with a height of 1 instead.
This fixes the GL_DEPTH_COMPONENT_* tests of the copyteximage piglit
test (and also seems to avoid a subsequent GPU hang).
Bugzilla: https://bugs.freedesktop.
Looks good to me.
Reviewed-by: Neil Roberts
- Neil
Francisco Jerez writes:
> It doesn't really improve locality of texture fetches, quite the
> opposite it's a waste of memory bandwidth and space due to tile
> alignment.
>
> v2: Check mt->logical_height0 instead of mt->target (Ken). Add shor
Kenneth Graunke writes:
> On Friday, February 06, 2015 07:23:25 PM Francisco Jerez wrote:
>> Shaders with image uniforms may have side effects. Make sure that
>> fragment shader threads are dispatched if the shader has any image
>> uniforms.
>> ---
>> src/mesa/drivers/dri/i965/gen7_wm_state.c |
Hi Sedat,
On 07/02/15 22:42, Sedat Dilek wrote:
> [ Please CC me I am not subscribed to mesa-dev and llvmdev MLs ]
>
> Hi,
>
> I already reported this when playing 1st time with my llvm-toolchain
> v3.6.0rc2 and mesa v10.3.7 [1].
> The issue still remains in mesa v10.4.4.
>
> So, this is a fiel
On 07/02/15 21:44, Sedat Dilek wrote:
> Hi,
>
> I was building mesa v10.4.4 with my llvm-toolchain v3.6.0rc2.
>
> My build breaks like this...
>
> ...
>
> Please cherry-pick...
>
> commit ef7e0b39a24966526b102643523feac765771842
> "gallivm: Update for RTDyldMemoryManager becoming an unique_ptr
Kristian Høgsberg writes:
> On Fri, Feb 6, 2015 at 9:23 AM, Francisco Jerez wrote:
>> ---
>> src/mesa/drivers/dri/i965/brw_program.c | 40
>> +
>> src/mesa/drivers/dri/i965/intel_reg.h | 1 +
>> 2 files changed, 41 insertions(+)
>>
>> diff --git a/src/mesa/dr
It doesn't really improve locality of texture fetches, quite the
opposite it's a waste of memory bandwidth and space due to tile
alignment.
v2: Check mt->logical_height0 instead of mt->target (Ken). Add short
comment explaining why they shouldn't be tiled.
---
src/mesa/drivers/dri/i965/intel
FWIW using a different name for such helpers in src/util looks good to
me (and I'm pretty indifferent to the actual name). We already have
imports from mesa/main crept in there which need fixing and we certainly
don't want to make the same mistake with gallium includes.
Roland
Am 08.02.2015 um 21
On 06/02/2015 19:58, Matt Turner wrote:
On Fri, Feb 6, 2015 at 3:38 AM, Jonathan Gray wrote:
OpenBSD has ffs in libc but does not have ffsll so use the compiler
builtin. PIPE_OS_BSD isn't suitable here as FreeBSD has ffsll in libc.
Signed-off-by: Jonathan Gray
---
src/gallium/auxiliary/uti
Kenneth Graunke writes:
> On Saturday, February 07, 2015 03:03:44 AM Francisco Jerez wrote:
>> Kenneth Graunke writes:
>>
>> > On Friday, February 06, 2015 07:23:16 PM Francisco Jerez wrote:
>> >> Reviewed-by: Paul Berry
>> >> ---
>> >> src/mesa/drivers/dri/i965/brw_context.h | 5 +
>> >>
So the i965 driver can expose 32 image uniforms per shader stage.
---
src/mesa/main/config.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/config.h b/src/mesa/main/config.h
index 4ec4b75..08e1a14 100644
--- a/src/mesa/main/config.h
+++ b/src/mesa/main/config.h
@
On 06/02/15 22:39, Carl Worth wrote:
On Fri, Feb 06 2015, Aaron Watry wrote:
Ignore me if this is a stupid question, but should those both be
sizeof(short)? I'd expect the first to be sizeof(char).
Not a stupid question. That was a copy-and-paste (kill-and-yank ?) bug
of mine.
Thanks for you
https://bugs.freedesktop.org/show_bug.cgi?id=89043
Bug ID: 89043
Summary: undefined symbol: _glapi_tls_Dispatch
Product: Mesa
Version: git
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity: nor
Scalar registers are required to have zero stride, fix the
regs_written calculation not to assume that the instruction writes
zero registers in that case.
v2: Rename CEILING() to DIV_ROUND_UP(). (Matt, Ken)
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 3 ++-
1 file ch
Some people have complained that code using the CEILING() macro is
difficult to understand because it's not immediately obvious what it
is supposed to do until you go and look up its definition. Use a more
descriptive name that matches the similar utility macro in the Linux
kernel.
---
src/mesa/d
On Mon, Feb 9, 2015 at 12:35 PM, Roland Scheidegger wrote:
> Am 09.02.2015 um 09:53 schrieb Iago Toral:
>> On Fri, 2015-02-06 at 21:27 +0100, Roland Scheidegger wrote:
>>> Am 06.02.2015 um 13:11 schrieb Iago Toral:
Hi,
Eduardo and I have been looking into a few dEQP test failures th
Hi,
On 02/05/2015 06:21 AM, Matt Turner wrote:
total instructions in shared programs: 5895414 -> 5747578 (-2.51%)
instructions in affected programs: 3618111 -> 3470275 (-4.09%)
helped:20492
HURT: 4449
GAINED:
https://bugs.freedesktop.org/show_bug.cgi?id=84570
Kai changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=77449
Bug 77449 depends on bug 84570, which changed state.
Bug 84570 Summary: Borderlands 2/Pre-Sequel: Constant frame rate drops while
playing; really bad with additionl lighting
https://bugs.freedesktop.org/show_bug.cgi?id=84570
What|
Right now virtual GRF book-keeping and allocation is performed in each
visitor class separately (among other hundred different things),
leading to duplicated logic in each visitor and preventing layering as
it forces any code that manipulates i965 IR and needs to allocate
virtual registers to depen
Some instruction bits don't have a mapping defined to any compacted
instruction field. If they're ever set and we end up compacting the
instruction they will be forced to zero. Avoid using compaction in such
cases.
v2: Align multiple lines of an expression to the same column. Change
conditi
I made a similar patch in my local tree because it will be necessary for
Skylake which doesn't support tiling for 1D textures. I made a little
test to time rendering a large (4096) 1D texture here:
https://github.com/bpeel/glthing/tree/time-1d-texture
It gives about an 11% increase in FPS with th
Matt Turner writes:
> On Fri, Feb 6, 2015 at 6:43 AM, Francisco Jerez wrote:
>> ---
>> src/mesa/drivers/dri/i965/brw_ir_vec4.h | 1 +
>> src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 15 ++-
>> src/mesa/drivers/dri/i965/brw_vec4.cpp | 17
Matt Turner writes:
> On Fri, Feb 6, 2015 at 6:42 AM, Francisco Jerez wrote:
>> So regs_written gets initialized with a sensible value.
>> ---
>> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 11 +--
>> 1 file changed, 5 insertions(+), 6 deletions(-)
>>
>> diff --git a/src/mesa/drive
1 - 100 of 137 matches
Mail list logo
