@@ -322,4 +322,36 @@ define <2 x i16>
@upgrade_amdgcn_global_atomic_fadd_v2bf16_p1(ptr addrspace(1) %
ret <2 x i16> %result
}
+declare <2 x half> @llvm.amdgcn.flat.atomic.fadd.v2f16.p0.v2f16(ptr nocapture,
<2 x half>) #0
Pierre-vh wrote:
nit: could we aut
@@ -75,6 +75,11 @@ Changes to the AArch64 Backend
Changes to the AMDGPU Backend
-
+* Removed ``llvm.amdgcn.flat.atomic.fadd`` and
+ ``llvm.amdgcn.global.atomic.fadd`` intrinsics. Users should use the
+ :ref:`atomicrmw ` instruction with `fadd` and
@@ -1017,29 +1015,6 @@ main_body:
ret void
}
-define amdgpu_kernel void @global_atomic_fadd_f64_noret(ptr addrspace(1) %ptr,
double %data) {
Pierre-vh wrote:
Why are some tests deleted, and some others changed to use atomicrmw?
https://github.com/llvm/llv
https://github.com/Pierre-vh approved this pull request.
https://github.com/llvm/llvm-project/pull/97051
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@@ -19273,9 +19269,14 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
ProcessOrderScopeAMDGCN(EmitScalarExpr(E->getArg(2)),
EmitScalarExpr(E->getArg(3)), AO, SSID);
} else {
- // The ds_atomic_fadd_* builtins do
https://github.com/Pierre-vh approved this pull request.
Add [NFC] tag?
https://github.com/llvm/llvm-project/pull/102806
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@@ -28,8 +36,51 @@ AMDGPUCodeGenPassBuilder::AMDGPUCodeGenPassBuilder(
}
void AMDGPUCodeGenPassBuilder::addPreISel(AddIRPass &addPass) const {
- // TODO: Add passes pre instruction selection.
- // Test only, convert to real IR passes in future.
+ const bool LateCFGStructuri
@@ -28,8 +36,51 @@ AMDGPUCodeGenPassBuilder::AMDGPUCodeGenPassBuilder(
}
void AMDGPUCodeGenPassBuilder::addPreISel(AddIRPass &addPass) const {
- // TODO: Add passes pre instruction selection.
- // Test only, convert to real IR passes in future.
+ const bool LateCFGStructuri
https://github.com/Pierre-vh approved this pull request.
https://github.com/llvm/llvm-project/pull/80695
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Pierre-vh wrote:
We don't use RTTI of that class before #89736 so unless that's also being
backported for some reason it's not needed.
https://github.com/llvm/llvm-project/pull/89790
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@@ -4371,8 +4375,10 @@ define amdgpu_kernel void
@global_sextload_v64i16_to_v64i32(ptr addrspace(1) %ou
; GCN-NOHSA-SI-NEXT:buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:48
; GCN-NOHSA-SI-NEXT:buffer_store_dwordx4 v[4:7], off, s[0:3], 0
; GCN-NOHSA-SI-NEXT:bu
@@ -754,13 +754,21 @@ define amdgpu_kernel void
@constant_load_v16i16_align2(ptr addrspace(4) %ptr0) #
; GFX12-NEXT:global_load_u16 v6, v8, s[0:1] offset:8
; GFX12-NEXT:global_load_u16 v5, v8, s[0:1] offset:4
; GFX12-NEXT:global_load_u16 v4, v8, s[0:1]
+; GFX12-NEX
@@ -953,6 +953,12 @@ def FeatureRequiredExportPriority :
SubtargetFeature<"required-export-priority",
"Export priority must be explicitly manipulated on GFX11.5"
>;
+def FeatureVmemWriteVgprInOrder : SubtargetFeature<"vmem-write-vgpr-in-order",
Pierre-vh wr
@@ -953,6 +953,12 @@ def FeatureRequiredExportPriority :
SubtargetFeature<"required-export-priority",
"Export priority must be explicitly manipulated on GFX11.5"
>;
+def FeatureVmemWriteVgprInOrder : SubtargetFeature<"vmem-write-vgpr-in-order",
Pierre-vh wr
https://github.com/Pierre-vh approved this pull request.
https://github.com/llvm/llvm-project/pull/105549
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Author: Pierre van Houtryve
Date: 2022-10-19T10:16:08Z
New Revision: edaf6a07a4aafd963ea958703890d03ab58ff2dd
URL:
https://github.com/llvm/llvm-project/commit/edaf6a07a4aafd963ea958703890d03ab58ff2dd
DIFF:
https://github.com/llvm/llvm-project/commit/edaf6a07a4aafd963ea958703890d03ab58ff2dd.diff
Author: Pierre van Houtryve
Date: 2022-10-19T10:16:08Z
New Revision: 007ef6fa4d89f7e60a82af8c7cc004a6204fd72b
URL:
https://github.com/llvm/llvm-project/commit/007ef6fa4d89f7e60a82af8c7cc004a6204fd72b
DIFF:
https://github.com/llvm/llvm-project/commit/007ef6fa4d89f7e60a82af8c7cc004a6204fd72b.diff
Author: Pierre van Houtryve
Date: 2022-11-30T06:14:35-05:00
New Revision: e07c05bc91ae1dfb625b7b0d93a83e5c6039fcb2
URL:
https://github.com/llvm/llvm-project/commit/e07c05bc91ae1dfb625b7b0d93a83e5c6039fcb2
DIFF:
https://github.com/llvm/llvm-project/commit/e07c05bc91ae1dfb625b7b0d93a83e5c6039fcb2
@@ -43,7 +43,7 @@ define i64 @test_flat_atomicrmw_sub_0_i64_agent(ptr %ptr) {
; ALL: [[ATOMICRMW_PRIVATE]]:
; ALL-NEXT:[[TMP1:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(5)
; ALL-NEXT:[[LOADED_PRIVATE:%.*]] = load i64, ptr addrspace(5) [[TMP1]],
align 8
-;
https://github.com/Pierre-vh approved this pull request.
https://github.com/llvm/llvm-project/pull/109410
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Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/131310?utm_source=stack-comment-downstack-mergeability-warning
Pierre-vh wrote:
> We can fold the clamp of the shift amount into the shift instruction during
> selection as we know the instruction ignores the high bits. We do that in the
> DAG path already. I think it special cases the and & (bitwidth - 1) pattern,
> which should form canonically. In prin
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131309
>From 16cbcc2c44bfe74ba54f00c5be634c54ff43a5cf Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 12 Mar 2025 09:43:15 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Allow forming s16 U/SBFX
pre-regbankselect
M
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131309
>From 16cbcc2c44bfe74ba54f00c5be634c54ff43a5cf Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 12 Mar 2025 09:43:15 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Allow forming s16 U/SBFX
pre-regbankselect
M
Pierre-vh wrote:
> > Where and how should that be implemented ? I struggled with that. I tried
> > adding a new special case in TableGen but I just couldn't find the right
> > way to do it. Do I just add it in C++ InstructionSelector before it checks
> > the patterns? Or should it be some kind
Pierre-vh wrote:
Ah, this doesn't do anything at this stage. It's only helpful once we disable
widening of i16 ops to i32 in CGP. Then this pattern can appear and it'll fold
it.
This combine is tested in AArch64. Should I copy over a few simple test cases
in the AMDGPU folder just to show the
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/131309
Make s16 G_U/SBFX legal and widen them in RegBankSelect.
This allows the set of BFX formation combines to work on s16 types.
>From ee917df6c6e996135d1b08f924b6645649eafa0d Mon Sep 17 00:00:00 2001
From: pvanho
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/131308
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https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131623
>From 4feac2fc42257cac9a1ca0070ec199f93a901b0d Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Mon, 17 Mar 2025 13:22:25 +0100
Subject: [PATCH] [AMDGPU] Add sext_trunc in RegBankCombiner
---
llvm/lib/Target/AM
Pierre-vh wrote:
Test changes were in the previous diff in the stack, it should be fixed now.
https://github.com/llvm/llvm-project/pull/131623
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https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131309
>From 8aa7f8b8f1c73d8fec55a229ea8dff020fc4c906 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 12 Mar 2025 09:43:15 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Allow forming s16 U/SBFX
pre-regbankselect
M
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131309
>From 8aa7f8b8f1c73d8fec55a229ea8dff020fc4c906 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 12 Mar 2025 09:43:15 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Allow forming s16 U/SBFX
pre-regbankselect
M
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131623
>From 4feac2fc42257cac9a1ca0070ec199f93a901b0d Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Mon, 17 Mar 2025 13:22:25 +0100
Subject: [PATCH] [AMDGPU] Add sext_trunc in RegBankCombiner
---
llvm/lib/Target/AM
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131308
>From cdfba0ea7ab0fcb60d632a25433b18b421022c25 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 5 Mar 2025 13:41:04 +0100
Subject: [PATCH 1/2] [AMDGPU][Legalizer] Widen i16 G_SEXT_INREG
It's better to widen
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131309
>From 2dc7126ab1abb6aa49aaf263a0591759130ddca5 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 12 Mar 2025 09:43:15 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Allow forming s16 U/SBFX
pre-regbankselect
M
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131310
>From d4b257d1b34b51018f51546974bffdc2ea56433d Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:00:21 +0100
Subject: [PATCH] [AMDGPU] Precommit si-fold-bitmask.mir
---
llvm/test/CodeGen/AMDG
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131311
>From 17e13825f173be8fd67494f13f002f35d93e357f Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:05:19 +0100
Subject: [PATCH 1/2] [AMDGPU][SIFoldOperands] Fold some redundant bitmasks
Instruct
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131312
>From 9fabf931105e1cf86cf69f90bd5c62068846c3e1 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:34:51 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Combine (sext (trunc (sext_in_reg x)))
This i
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131311
>From 520757cf40d285b58eb0539840be2bf282c0a0af Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:05:19 +0100
Subject: [PATCH 1/2] [AMDGPU][SIFoldOperands] Fold some redundant bitmasks
Instruct
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131312
>From 4751d38d86886106c00e9140bf0bb3a3459950cb Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:34:51 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Combine (sext (trunc (sext_in_reg x)))
This i
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131306
>From 1af83464f02df212384bd97848b0073d41053234 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 5 Mar 2025 10:46:01 +0100
Subject: [PATCH 1/2] [AMDGPU][RegBankInfo] Promote scalar i16 and/or/xor to
i32
See
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131310
>From 6db5fe8cc5ff82cc7dc8751ac584870ddbf1b537 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:00:21 +0100
Subject: [PATCH] [AMDGPU] Precommit si-fold-bitmask.mir
---
llvm/test/CodeGen/AMDG
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131309
>From 090fa3eb8b5ebb595a6ec4b78ec337af71466a73 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 12 Mar 2025 09:43:15 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Allow forming s16 U/SBFX
pre-regbankselect
M
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131310
>From 6db5fe8cc5ff82cc7dc8751ac584870ddbf1b537 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:00:21 +0100
Subject: [PATCH] [AMDGPU] Precommit si-fold-bitmask.mir
---
llvm/test/CodeGen/AMDG
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131309
>From 090fa3eb8b5ebb595a6ec4b78ec337af71466a73 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 12 Mar 2025 09:43:15 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Allow forming s16 U/SBFX
pre-regbankselect
M
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131312
>From 4751d38d86886106c00e9140bf0bb3a3459950cb Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:34:51 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Combine (sext (trunc (sext_in_reg x)))
This i
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131308
>From be5c76eeb981e94017cc2a504f35079d47d7ce5c Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 5 Mar 2025 13:41:04 +0100
Subject: [PATCH 1/2] [AMDGPU][Legalizer] Widen i16 G_SEXT_INREG
It's better to widen
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131311
>From 520757cf40d285b58eb0539840be2bf282c0a0af Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:05:19 +0100
Subject: [PATCH 1/2] [AMDGPU][SIFoldOperands] Fold some redundant bitmasks
Instruct
Pierre-vh wrote:
### Merge activity
* **Mar 17, 4:51 AM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/131307).
https://github.com/llvm/llvm-project/pull/131307
__
Pierre-vh wrote:
### Merge activity
* **Mar 17, 4:51 AM EDT**: A user started a stack merge that includes this pull
request via
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/131306).
https://github.com/llvm/llvm-project/pull/131306
__
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131308
>From be5c76eeb981e94017cc2a504f35079d47d7ce5c Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 5 Mar 2025 13:41:04 +0100
Subject: [PATCH 1/2] [AMDGPU][Legalizer] Widen i16 G_SEXT_INREG
It's better to widen
@@ -2432,6 +2433,29 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
return;
}
+// 16-bit operations are VALU only, but can be promoted to 32-bit SALU.
+// Packed 16-bit operations need to be scalarized and promoted.
Pierre-vh wrote:
It was
https://github.com/Pierre-vh closed
https://github.com/llvm/llvm-project/pull/131312
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https://github.com/Pierre-vh closed
https://github.com/llvm/llvm-project/pull/131311
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https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131309
>From d65db023bfae0c9a5eaeb5bebac39d75723c27d6 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 12 Mar 2025 09:43:15 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Allow forming s16 U/SBFX
pre-regbankselect
M
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131311
>From f3fddad8dca1e8ed327d7cc7cfee7a465032dcc4 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:05:19 +0100
Subject: [PATCH 1/2] [AMDGPU][SIFoldOperands] Fold some redundant bitmasks
Instruct
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131310
>From 65d5012c30366cc713b793a30ab5119ddf8a77af Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:00:21 +0100
Subject: [PATCH] [AMDGPU] Precommit si-fold-bitmask.mir
---
llvm/test/CodeGen/AMDG
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131312
>From 782153a9a47d4a0fdb897e811033179fa67c5060 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:34:51 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Combine (sext (trunc (sext_in_reg x)))
This i
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131624
>From 3f3c67934d0c9ea34c11cbd24becc24541baf567 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Mon, 17 Mar 2025 13:54:59 +0100
Subject: [PATCH 1/3] [GlobalISel] Combine redundant sext_inreg
---
.../llvm/CodeGe
@@ -489,22 +489,61 @@ RegBankLegalizeRules::RegBankLegalizeRules(const
GCNSubtarget &_ST,
.Uni(B32, {{SgprB32}, {Sgpr32AExtBoolInReg, SgprB32, SgprB32}});
addRulesForGOpcs({G_ANYEXT})
+ .Any({{UniS16, S1}, {{None}, {None}}}) // should be combined away
.Any
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131624
>From 3f3c67934d0c9ea34c11cbd24becc24541baf567 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Mon, 17 Mar 2025 13:54:59 +0100
Subject: [PATCH 1/2] [GlobalISel] Combine redundant sext_inreg
---
.../llvm/CodeGe
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131624
>From 3f3c67934d0c9ea34c11cbd24becc24541baf567 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Mon, 17 Mar 2025 13:54:59 +0100
Subject: [PATCH 1/2] [GlobalISel] Combine redundant sext_inreg
---
.../llvm/CodeGe
https://github.com/Pierre-vh closed
https://github.com/llvm/llvm-project/pull/131310
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https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131624
>From f4c801437460aef9b9c2e5f49d1e98ec90fadb16 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Mon, 17 Mar 2025 13:54:59 +0100
Subject: [PATCH 1/4] [GlobalISel] Combine redundant sext_inreg
---
.../llvm/CodeGe
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/131312
This is a bit of an akward pattern that can come up as a result
of legalization and then widening of i16 operations to i32 in RegBankSelect
on AMDGPU.
This quick combine avoids redundant patterns like
```
s_se
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/131308
It's better to widen them to avoid it being lowered into a G_ASHR + G_SHL. With
this change we just extend to i32 then trunc the result.
>From 815595b1ca20b613b5b4b08cafedda93e397cf92 Mon Sep 17 00:00:00 2001
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/131310
None
>From b87a9db3b8ab29db3f1bb668a4d3bf312add817b Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:00:21 +0100
Subject: [PATCH] [AMDGPU] Precommit si-fold-bitmask.mir
---
llvm/test/CodeGe
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/131307?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/131311
Instructions like shifts only read some of the bits of the shift amount
operand, between 4 and 6 bits.
If the source operand is being masked, we can just ignore the mask.
Effects are minimal right now but thi
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/131306?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/131310
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https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131312
>From b9bf3f2f53fcf7cbd133e57d4c7f64a8f06763b2 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:34:51 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Combine (sext (trunc (sext_in_reg x)))
This i
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131306
>From 1af83464f02df212384bd97848b0073d41053234 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 5 Mar 2025 10:46:01 +0100
Subject: [PATCH] [AMDGPU][RegBankInfo] Promote scalar i16 and/or/xor to i32
See #645
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131311
>From d6e5dc03ae8bb46972b7bcffd35e60babbfbc678 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:05:19 +0100
Subject: [PATCH 1/2] [AMDGPU][SIFoldOperands] Fold some redundant bitmasks
Instruct
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131308
>From e6862b4528d1ed48bbca9e742dd9a96d8777545b Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 5 Mar 2025 13:41:04 +0100
Subject: [PATCH 1/2] [AMDGPU][Legalizer] Widen i16 G_SEXT_INREG
It's better to widen
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131310
>From fcd5623ccd18100197817f7f4d5a500ca433f8dc Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:00:21 +0100
Subject: [PATCH] [AMDGPU] Precommit si-fold-bitmask.mir
---
llvm/test/CodeGen/AMDG
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131309
>From c30cc50e3650137bdb8acc9674c312f6c088983f Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 12 Mar 2025 09:43:15 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Allow forming s16 U/SBFX
pre-regbankselect
M
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131309
>From c30cc50e3650137bdb8acc9674c312f6c088983f Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 12 Mar 2025 09:43:15 +0100
Subject: [PATCH] [AMDGPU][GlobalISel] Allow forming s16 U/SBFX
pre-regbankselect
M
Pierre-vh wrote:
> > GlobalISel unfortunately needs it. We can end up with things like a
> > `G_LSHR` with the shift amount being zext'd, and they're both lowered
> > independently so we have a `s_and_b32` of the shift amount.
>
> It should always be post legalize / post regbankselect combinab
@@ -258,6 +258,14 @@ def sext_trunc_sextload : GICombineRule<
[{ return Helper.matchSextTruncSextLoad(*${d}); }]),
(apply [{ Helper.applySextTruncSextLoad(*${d}); }])>;
+def sext_trunc_sextinreg : GICombineRule<
+ (defs root:$dst),
+ (match (G_SEXT_INREG $sir, $sr
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/131312
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https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131310
>From fcd5623ccd18100197817f7f4d5a500ca433f8dc Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Fri, 14 Mar 2025 10:00:21 +0100
Subject: [PATCH] [AMDGPU] Precommit si-fold-bitmask.mir
---
llvm/test/CodeGen/AMDG
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/131309?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/131311
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Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/131308?utm_source=stack-comment-downstack-mergeability-warning
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/131312?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/131306
See #64591
>From a9f0563665a6d2b69fdee0d826cb52d6651c3dc4 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 5 Mar 2025 10:46:01 +0100
Subject: [PATCH] [AMDGPU][RegBankInfo] Promote scalar i16 and/or/xor to i
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/131311?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/131308
>From e6862b4528d1ed48bbca9e742dd9a96d8777545b Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Wed, 5 Mar 2025 13:41:04 +0100
Subject: [PATCH 1/2] [AMDGPU][Legalizer] Widen i16 G_SEXT_INREG
It's better to widen
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/131624
None
>From e36f66595a582b6ba926186674b6da6b41236ff5 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Mon, 17 Mar 2025 13:54:59 +0100
Subject: [PATCH] [GlobalISel] Combine redundant sext_inreg
---
.../llvm/Code
https://github.com/Pierre-vh created
https://github.com/llvm/llvm-project/pull/131623
None
>From 3f2cbbd6addf4844c7c861a6de55be59a8c96c35 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Mon, 17 Mar 2025 13:22:25 +0100
Subject: [PATCH] [AMDGPU] Add sext_trunc in RegBankCombiner
---
llvm/lib/Tar
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/131623
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https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/131624
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Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/131623?utm_source=stack-comment-downstack-mergeability-warning
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/131624?utm_source=stack-comment-downstack-mergeability-warning
Pierre-vh wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/135340?utm_source=stack-comment-downstack-mergeability-warning
https://github.com/Pierre-vh ready_for_review
https://github.com/llvm/llvm-project/pull/135340
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