Author: Pierre van Houtryve Date: 2022-10-19T10:16:08Z New Revision: 007ef6fa4d89f7e60a82af8c7cc004a6204fd72b
URL: https://github.com/llvm/llvm-project/commit/007ef6fa4d89f7e60a82af8c7cc004a6204fd72b DIFF: https://github.com/llvm/llvm-project/commit/007ef6fa4d89f7e60a82af8c7cc004a6204fd72b.diff LOG: [AMDGPU][GISel] Constrain selected operands in selectG_BUILD_VECTOR Small bugfix. Currently harmless but a case in D134354 triggers it. Differential Revision: https://reviews.llvm.org/D136235 Added: Modified: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 7f41e8593692..0a6896693510 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -686,13 +686,19 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR(MachineInstr &MI) const { // TODO: Can be improved? if (IsVector) { Register TmpReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); - BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_AND_B32_e32), TmpReg) - .addImm(0xFFFF) - .addReg(Src0); - BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), Dst) - .addReg(Src1) - .addImm(16) - .addReg(TmpReg); + auto MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_AND_B32_e32), TmpReg) + .addImm(0xFFFF) + .addReg(Src0); + if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) + return false; + + MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), Dst) + .addReg(Src1) + .addImm(16) + .addReg(TmpReg); + if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) + return false; + MI.eraseFromParent(); return true; } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
