HerrCai0907 wrote:
dump-ast-matchers has some bug. I will fix it after
https://github.com/llvm/llvm-project/pull/130726 merging
https://github.com/llvm/llvm-project/pull/130416
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https://github.com/ylzsx updated
https://github.com/llvm/llvm-project/pull/123680
>From 0f580567169ffbf1546a5389ab4b9f7d1fc07c71 Mon Sep 17 00:00:00 2001
From: yangzhaoxin
Date: Thu, 2 Jan 2025 20:58:56 +0800
Subject: [PATCH 1/5] Convert TLS IE to LE in the normal or medium code model.
Origina
https://github.com/perlfu approved this pull request.
LGTM
nit: can you note somewhere (in a comment) that
`ScratchReservedForDynamicVGPRs` is in bytes -- the magic divide by 4 to set
`dynamic_vgpr_saved_count` was not entirely obvious.
https://github.com/llvm/llvm-project/pull/130055
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optimisan wrote:
Perhaps best to avoid large stacks like this to reduce upstack rebasing on
mid-stack updates.
https://github.com/llvm/llvm-project/pull/130060
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130061
>From 0818ab4b709c83d80a149d7ce41d0cf796de7497 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 04:41:08 +
Subject: [PATCH 1/2] [AMDGPU][NPM] Port SIInsertWaitcnts to NPM
---
llvm/lib/Targ
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/129857
>From b15d39cf6236a02212e5b802153d1614d2c8884e Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 5 Mar 2025 09:19:08 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port FEntryInserter to NPM
---
llvm/include/l
llvmbot wrote:
@llvm/pr-subscribers-backend-x86
Author: Akshat Oke (optimisan)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/129857.diff
8 Files Affected:
- (added) llvm/include/llvm/CodeGen/FEntryInserter.h (+25)
- (modified) llvm/include/llvm/InitializePasses.h (
optimisan wrote:
There were no existing tests, added one.
https://github.com/llvm/llvm-project/pull/129857
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https://github.com/llvm/llvm-project/pull/129857
>From b15d39cf6236a02212e5b802153d1614d2c8884e Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 5 Mar 2025 09:19:08 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port FEntryInserter to NPM
---
llvm/include/l
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/129857
>From b15d39cf6236a02212e5b802153d1614d2c8884e Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 5 Mar 2025 09:19:08 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port FEntryInserter to NPM
---
llvm/include/l
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: Akshat Oke (optimisan)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/129866.diff
8 Files Affected:
- (added) llvm/include/llvm/CodeGen/PatchableFunction.h (+30)
- (modified) llvm/include/llvm/InitializePas
@@ -143,11 +170,43 @@ void XRayInstrumentation::prependRetWithPatchableExit(
}
}
-bool XRayInstrumentation::runOnMachineFunction(MachineFunction &MF) {
+PreservedAnalyses
+XRayInstrumentationPass::run(MachineFunction &MF,
+ MachineFunctionAnalys
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130065
>From 8e8a5ace64ed51ba5466af56a642efdb8f9c8a38 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 06:20:13 +
Subject: [PATCH 1/2] [AMDGPU][NPM] Port SIPreEmitPeephole to NPM
---
llvm/lib/Tar
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130065
>From 8e8a5ace64ed51ba5466af56a642efdb8f9c8a38 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 06:20:13 +
Subject: [PATCH 1/2] [AMDGPU][NPM] Port SIPreEmitPeephole to NPM
---
llvm/lib/Tar
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130068
>From 88b0e7fda861484572721c3fda7c020afa1b456b Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 09:30:37 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port RemoveLoadsIntoFakeUses to NPM
---
.../l
https://github.com/skatrak created
https://github.com/llvm/llvm-project/pull/130789
This patch introduces a use for the new `getBlockArgsPairs` to avoid having to
manually list each applicable clause.
Also, the `numClauseBlockArgs()` function is introduced, which simplifies the
implementation
llvmbot wrote:
@llvm/pr-subscribers-mlir-openmp
Author: Sergio Afonso (skatrak)
Changes
This patch introduces a use for the new `getBlockArgsPairs` to avoid having to
manually list each applicable clause.
Also, the `numClauseBlockArgs()` function is introduced, which simplifies the
impl
llvmbot wrote:
@llvm/pr-subscribers-flang-openmp
@llvm/pr-subscribers-mlir
Author: Sergio Afonso (skatrak)
Changes
This patch introduces a use for the new `getBlockArgsPairs` to avoid having to
manually list each applicable clause.
Also, the `numClauseBlockArgs()` function is introduced,
llvmbot wrote:
@llvm/pr-subscribers-mlir-llvm
Author: Sergio Afonso (skatrak)
Changes
This patch introduces a use for the new `getBlockArgsPairs` to avoid having to
manually list each applicable clause.
Also, the `numClauseBlockArgs()` function is introduced, which simplifies the
implem
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
@llvm/pr-subscribers-llvm-transforms
Author: Fabian Ritter (ritter-x2a)
Changes
If we know that the initial GEP was inbounds, and we change it to a
sequence of GEPs from the same base pointer where every offset is
non-negative, then the ne
@@ -180,13 +178,16 @@ void DataAggregator::start() {
if (opts::ArmSPE) {
if (!opts::BasicAggregation) {
- errs() << "PERF2BOLT-ERROR: Arm SPE mode is combined only with "
-"BasicAggregation.\n";
- exit(1);
+ // pidfrom_ip to_ip
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130066
>From cd2a7ff03443f983ac247c41d697d2c85fb8b821 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 06:42:54 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port PostRAHazardRecognizer to NPM
---
.../ll
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130062
>From 4edbd96b9a5599e8e315ce90393e91d29539f81c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 04:52:38 +
Subject: [PATCH 1/2] [AMDGPU][NPM] Port SIInsertHardClauses to NPM
---
llvm/lib/T
https://github.com/arsenm deleted
https://github.com/llvm/llvm-project/pull/130617
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https://github.com/RKSimon approved this pull request.
https://github.com/llvm/llvm-project/pull/130774
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130063
>From c7ec8bbf224754fcddbf8dc26aba07d655e69869 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 05:26:49 +
Subject: [PATCH 1/2] [AMDGPU][NPM] Port SILateBranchLowering to NPM
---
llvm/lib/
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130064
>From 0793691bb216221b7010ae8ce4ef26ba3d678be7 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 06:07:23 +
Subject: [PATCH 1/2] [AMDGPU][NPM] Port AMDGPUSetWavePriority to NPM
---
llvm/lib
llvmbot wrote:
@llvm/pr-subscribers-backend-x86
Author: None (llvmbot)
Changes
Backport fcce3084cb43a12f2e6e19b8e5b655f3df8739d6
Requested by: @phoebewang
---
Full diff: https://github.com/llvm/llvm-project/pull/130774.diff
2 Files Affected:
- (modified) llvm/lib/Target/X86/X86InstrSS
https://github.com/kaadam edited
https://github.com/llvm/llvm-project/pull/129231
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https://github.com/tblah approved this pull request.
LGTM, thanks
https://github.com/llvm/llvm-project/pull/130789
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yxsamliu wrote:
@tstellar Is this PR the right procedure for c-p a fix to LLVM release branch?
Thanks.
https://github.com/llvm/llvm-project/pull/130126
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https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/124298
>From 31f4387623100e815d478245ca78b6dcc52f869e Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 28 Feb 2025 15:56:04 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Temporal divergence lowering (non i
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/128702
>From 8e33358f5f3ca6167cc585acb7661d7a5f4a8568 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 28 Feb 2025 15:54:55 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Update divergence lowering tests
I
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/128702
>From 8e33358f5f3ca6167cc585acb7661d7a5f4a8568 Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 28 Feb 2025 15:54:55 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Update divergence lowering tests
I
https://github.com/petar-avramovic updated
https://github.com/llvm/llvm-project/pull/124298
>From 31f4387623100e815d478245ca78b6dcc52f869e Mon Sep 17 00:00:00 2001
From: Petar Avramovic
Date: Fri, 28 Feb 2025 15:56:04 +0100
Subject: [PATCH] AMDGPU/GlobalISel: Temporal divergence lowering (non i
https://github.com/optimisan ready_for_review
https://github.com/llvm/llvm-project/pull/129865
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@@ -116,14 +117,56 @@ static void splitBlock(MachineBasicBlock &MBB,
MachineInstr &MI,
MDT->applyUpdates(DTUpdates);
}
-void SILateBranchLowering::expandChainCall(MachineInstr &MI) {
+static void addRegOrCopyOp(MachineInstrBuilder &MIB, MachineOperand &Op) {
+ if (Op.isReg
@@ -736,6 +742,26 @@ multiclass si_cs_chain_tc_patterns<
defm : si_cs_chain_tc_patterns;
defm : si_cs_chain_tc_patterns;
+// Match dynamic VGPR case. This is always indirect since we choose the callee
+// dynamically based on the result of the VGPR reallocation, so make sure t
@@ -182,6 +182,53 @@ struct CastOpInterface
}
};
+struct CopyOpInterface
+: public RuntimeVerifiableOpInterface::ExternalModel {
+ void generateRuntimeVerification(Operation *op, OpBuilder &builder,
+ Location loc) const {
+auto cop
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130564
>From b1194b992d8aa79a000766e441af31f17aa05c07 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 10 Mar 2025 06:14:27 +
Subject: [PATCH 1/3] [CodeGen][NPM] Port VirtRegRewriter to NPM
Not sure why this
https://github.com/optimisan ready_for_review
https://github.com/llvm/llvm-project/pull/130059
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130548
>From 0ab8c65820460ee4654337d5374a6e5e944159b6 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 10 Mar 2025 04:31:20 +
Subject: [PATCH] [AMDGPU][NFC] Format GCNCreateVOPD.cpp
---
llvm/lib/Target/AMDG
llvmbot wrote:
@llvm/pr-subscribers-backend-x86
Author: Akshat Oke (optimisan)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/129865.diff
9 Files Affected:
- (added) llvm/include/llvm/CodeGen/XRayInstrumentation.h (+25)
- (modified) llvm/include/llvm/InitializePasse
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130059
>From 6f2706299060e3d17750a6fdcee0e46d961933d3 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 5 Mar 2025 10:52:00 +
Subject: [PATCH 1/2] [AMDGPU][NPM] Port GCNCreateVOPD to NPM
---
llvm/lib/Target/
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/129866
>From d2af6dc817ed482666b6c1816bcf7afc9f29eafe Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 5 Mar 2025 10:34:25 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port PatchableFunction to NPM
---
llvm/includ
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/129865
>From 103b199cbf6ce84a49067b1a6065efee7254fbcc Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 5 Mar 2025 10:11:27 +
Subject: [PATCH] [CodeGen][NPM] Port XRayInstrumentation to NPM
---
.../llvm/Code
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/129865
>From c00160bd9726b68d0b1a9d026f9cd24898784126 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 5 Mar 2025 10:11:27 +
Subject: [PATCH] [CodeGen][NPM] Port XRayInstrumentation to NPM
---
.../llvm/Code
@@ -143,11 +170,43 @@ void XRayInstrumentation::prependRetWithPatchableExit(
}
}
-bool XRayInstrumentation::runOnMachineFunction(MachineFunction &MF) {
+PreservedAnalyses
+XRayInstrumentationPass::run(MachineFunction &MF,
+ MachineFunctionAnalys
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/130548
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https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121831
>From 71eee0d4ef36e13b0f62a4b9ca92614ed7f7a750 Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 6 Jan 2025 10:05:08 -0800
Subject: [PATCH] [RISCV] Integrate RISCV target in baremetal toolchain object
https://github.com/quic-garvgupt updated
https://github.com/llvm/llvm-project/pull/121830
>From b6dac4bc46c17ff561929b202de4b2914e80f0dd Mon Sep 17 00:00:00 2001
From: Garvit Gupta
Date: Mon, 6 Jan 2025 09:21:11 -0800
Subject: [PATCH] [RISCV] Change linker job in Baremetal toolchain object to
@@ -1200,34 +1225,78 @@ bool AMDGPUCallLowering::lowerTailCall(
if (!IsSibCall)
CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP);
- unsigned Opc =
- getCallOpcode(MF, Info.Callee.isReg(), true, ST.isWave32(), CalleeCC);
+ bool IsChainCall = AMDGPU::isC
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130063
>From 70a3b5827ef2a8579ea6218cf9f797ffd3d79404 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 05:26:49 +
Subject: [PATCH] [AMDGPU][NPM] Port SILateBranchLowering to NPM
---
llvm/lib/Targ
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130059
>From 6f2706299060e3d17750a6fdcee0e46d961933d3 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 5 Mar 2025 10:52:00 +
Subject: [PATCH 1/3] [AMDGPU][NPM] Port GCNCreateVOPD to NPM
---
llvm/lib/Target/
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Akshat Oke (optimisan)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/130059.diff
5 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPU.h (+7-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.
@@ -104,6 +104,7 @@ MACHINE_FUNCTION_PASS("amdgpu-rewrite-partial-reg-uses",
GCNRewritePartialRegUse
MACHINE_FUNCTION_PASS("amdgpu-pre-ra-optimizations",
GCNPreRAOptimizationsPass())
MACHINE_FUNCTION_PASS("amdgpu-nsa-reassign", GCNNSAReassignPass())
MACHINE_FUNCTION_PASS("gcn
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130060
>From 8a70796b25b7d308f5fbdd38999a6f841637d76d Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Wed, 5 Mar 2025 11:06:40 +
Subject: [PATCH 1/2] [AMDGPU][NPM] Port SIMemoryLegalizer to NPM
---
llvm/lib/Tar
optimisan wrote:
> No tests?
Couldn't find a standalone test, `CodeGen/X86/stack-frame-layout-remarks.ll`
will need the complete pipeline till this pass.
https://github.com/llvm/llvm-project/pull/130070
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130069
>From b5c636f7bc6d46ee6e7798a5c91d2eecb54b8122 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 10:20:36 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port MachineSanitizerBinaryMetadata to NPM
---
https://github.com/zyn0217 milestoned
https://github.com/llvm/llvm-project/pull/128845
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https://github.com/llvm/llvm-project/pull/130067
>From 7861e458d4e695275be8738ee75e65a7981dc752 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 06:56:04 +
Subject: [PATCH 1/2] [CodeGen][NPM] Port BranchRelaxation to NPM
This completes th
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130564
>From b1194b992d8aa79a000766e441af31f17aa05c07 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 10 Mar 2025 06:14:27 +
Subject: [PATCH 1/3] [CodeGen][NPM] Port VirtRegRewriter to NPM
Not sure why this
Author: Benjamin Maxwell
Date: 2025-03-11T12:10:13Z
New Revision: 00e5b6d7e46ef55325676ed4fd95a2f6929cb0c7
URL:
https://github.com/llvm/llvm-project/commit/00e5b6d7e46ef55325676ed4fd95a2f6929cb0c7
DIFF:
https://github.com/llvm/llvm-project/commit/00e5b6d7e46ef55325676ed4fd95a2f6929cb0c7.diff
L
https://github.com/rovka updated
https://github.com/llvm/llvm-project/pull/130055
>From 3e20edfc6f3b1bfa60f5d778ce98c1fb984b1aee Mon Sep 17 00:00:00 2001
From: Diana Picus
Date: Tue, 24 Sep 2024 09:57:25 +0200
Subject: [PATCH 1/8] [AMDGPU] Allocate scratch space for dVGPRs for CWSR
The CWSR tr
llvmbot wrote:
@RKSimon What do you think about merging this PR to the release branch?
https://github.com/llvm/llvm-project/pull/130774
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https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/130774
Backport fcce3084cb43a12f2e6e19b8e5b655f3df8739d6
Requested by: @phoebewang
>From 39addf851df56f44f1d3ef79fbce7a03bd17ec82 Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Tue, 11 Mar 2025 21:20:27 +0800
Subje
https://github.com/llvmbot milestoned
https://github.com/llvm/llvm-project/pull/130774
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@@ -113,6 +153,37 @@ TEST_F(PerfSpeEventsTestHelper, SpeBranches) {
EXPECT_TRUE(checkEvents(1234, 10, {"branches-spe:"}));
}
+TEST_F(PerfSpeEventsTestHelper, SpeBranchesWithBrstack) {
+ // Check perf input with SPE branch events as brstack format.
+ // Example collection c
@@ -88,6 +89,45 @@ struct PerfSpeEventsTestHelper : public testing::Test {
return SampleSize == DA.BasicSamples.size();
}
+
+ /// Compare LBREntries
+ bool checkLBREntry(const LBREntry &Lhs, const LBREntry &Rhs) {
+return Lhs.From == Rhs.From && Lhs.To == Rhs.To &&
@@ -0,0 +1,45 @@
+! Tests that if `do concurrent` is not perfectly nested in its parent loop,
that
+! we skip converting the not-perfectly nested `do concurrent` loop.
+
+! RUN: %flang_fc1 -emit-hlfir -fopenmp -fdo-concurrent-to-openmp=host %s -o - \
+! RUN: | FileCheck %s
+
+p
https://github.com/optimisan edited
https://github.com/llvm/llvm-project/pull/130069
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https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/130067
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llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Akshat Oke (optimisan)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/130063.diff
6 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPU.h (+9-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.
@@ -116,14 +117,56 @@ static void splitBlock(MachineBasicBlock &MBB,
MachineInstr &MI,
MDT->applyUpdates(DTUpdates);
}
-void SILateBranchLowering::expandChainCall(MachineInstr &MI) {
+static void addRegOrCopyOp(MachineInstrBuilder &MIB, MachineOperand &Op) {
+ if (Op.isReg
@@ -180,13 +178,16 @@ void DataAggregator::start() {
if (opts::ArmSPE) {
if (!opts::BasicAggregation) {
- errs() << "PERF2BOLT-ERROR: Arm SPE mode is combined only with "
-"BasicAggregation.\n";
- exit(1);
+ // pidfrom_ip to_ip
llvmbot wrote:
@llvm/pr-subscribers-backend-hexagon
Author: None (llvmbot)
Changes
Backport 29d3fc3f11d272a72ac255af9277c740f26c3dfc
Requested by: @androm3da
---
Patch is 38.60 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/130215.diff
4 Fi
llvmbot wrote:
@llvm/pr-subscribers-llvm-regalloc
Author: Akshat Oke (optimisan)
Changes
Not sure why this is squished into VirtRegMap.h
---
Full diff: https://github.com/llvm/llvm-project/pull/130564.diff
12 Files Affected:
- (modified) llvm/include/llvm/CodeGen/VirtRegMap.h (+15)
-
https://github.com/optimisan created
https://github.com/llvm/llvm-project/pull/130064
None
>From f7988c3f991966d71339aebe4223d64e30038eb9 Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 06:07:23 +
Subject: [PATCH] [AMDGPU][NPM] Port AMDGPUSetWavePriority to NPM
---
llvm/l
https://github.com/optimisan ready_for_review
https://github.com/llvm/llvm-project/pull/130061
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https://github.com/inbelic edited
https://github.com/llvm/llvm-project/pull/129797
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@@ -726,6 +771,14 @@ void VirtRegRewriter::rewrite() {
RewriteRegs.clear();
}
+void VirtRegRewriterPass::printPipeline(
+raw_ostream &OS, function_ref) const {
+ OS << "virt-reg-rewriter<";
+ if (!ClearVirtRegs)
+OS << "no-";
+ OS << "clear-vregs>";
--
https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/130065
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https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130070
>From 9aaee4f8ac21bc46d25d33e666deb491a36c Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Thu, 6 Mar 2025 10:45:25 +
Subject: [PATCH] [CodeGen][NPM] Port StackFrameLayoutAnalysisPass to NPM
---
.../
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Yaxun (Sam) Liu (yxsamliu)
Changes
When inferring host device attr of virtual dtor of explicit template class
instantiation, clang should be conservative. This guarantees dtors that may
call host functions not to have implicit device attr
https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/130065
>From 78bcc3a3576cc1f0dba5c9feb5ed781a62877ffe Mon Sep 17 00:00:00 2001
From: Akshat Oke
Date: Mon, 10 Mar 2025 04:31:20 +
Subject: [PATCH 1/9] [AMDGPU][NFC] Format GCNCreateVOPD.cpp
---
llvm/lib/Target/
https://github.com/paschalis-mpeis edited
https://github.com/llvm/llvm-project/pull/129231
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https://github.com/cdevadas approved this pull request.
https://github.com/llvm/llvm-project/pull/129866
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https://github.com/chapuni updated
https://github.com/llvm/llvm-project/pull/129473
>From e2dd98690a0f43b35ee22d59efeb04d2c7fead68 Mon Sep 17 00:00:00 2001
From: NAKAMURA Takumi
Date: Mon, 3 Mar 2025 12:26:08 +0900
Subject: [PATCH] detailed
---
llvm/include/llvm/ObjectYAML/CovMap.h | 9
@@ -20,34 +20,53 @@
#include "llvm/IR/MDBuilder.h"
#include "llvm/InitializePasses.h"
#include "llvm/Pass.h"
+#include "llvm/Transforms/Instrumentation/SanitizerBinaryMetadata.h"
#include
using namespace llvm;
namespace {
-class MachineSanitizerBinaryMetadata : public M
@@ -180,13 +178,16 @@ void DataAggregator::start() {
if (opts::ArmSPE) {
if (!opts::BasicAggregation) {
- errs() << "PERF2BOLT-ERROR: Arm SPE mode is combined only with "
-"BasicAggregation.\n";
- exit(1);
+ // pidfrom_ip to_ip
frasercrmck wrote:
> Given the release is already out, I don't think it makes sense to pull this
> from the install in the release branch
True. You could argue that anyone using the (broken) headers in LLVM 20 is well
aware of how broken they are, so pulling them from the release doesn't help
arsenm wrote:
> > Started a llvm-compile-time-tracker run to check for compile time impact.
>
> all within +/-0.02% (but I'm not sure if SeparateConstOffsetFromGEP even runs
> as part of these benchmarks).
It doesn't run amdgpu anything so no
https://github.com/llvm/llvm-project/pull/130617
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/130069
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@@ -2,6 +2,10 @@
# RUN: -start-before=greedy,0 -stop-after=virtregrewriter,0
-pass-remarks='.*' -pass-remarks-output=%t.yaml -o /dev/null %s
# RUN: FileCheck %s < %t.yaml
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 \
+# RUN: -passes='greedy,virt-reg-rewriter'
-pa
@@ -1079,6 +1081,8 @@ bool
SeparateConstOffsetFromGEP::splitGEP(GetElementPtrInst *GEP) {
// and the old index if they are not used.
RecursivelyDeleteTriviallyDeadInstructions(UserChainTail);
RecursivelyDeleteTriviallyDeadInstructions(OldIdx);
+
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/130564
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@@ -88,6 +89,45 @@ struct PerfSpeEventsTestHelper : public testing::Test {
return SampleSize == DA.BasicSamples.size();
}
+
+ /// Compare LBREntries
+ bool checkLBREntry(const LBREntry &Lhs, const LBREntry &Rhs) {
+return Lhs.From == Rhs.From && Lhs.To == Rhs.To &&
@@ -0,0 +1,19 @@
+# RUN: llc -mtriple=x86_64-- -passes=fentry-insert %s -o - | FileCheck %s
+
+--- |
+ target triple = "x86_64--"
+ define i32 @with_fentry() #1 {
+ entry:
+ret i32 0
+ }
+
+ attributes #1 = { "fentry-call"="true" }
arsenm wrote:
```sugge
https://github.com/arsenm approved this pull request.
https://github.com/llvm/llvm-project/pull/129857
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https://github.com/ritter-x2a updated
https://github.com/llvm/llvm-project/pull/130617
>From 23384f4b38b721125650577cae440caa20203bc8 Mon Sep 17 00:00:00 2001
From: Fabian Ritter
Date: Mon, 10 Mar 2025 06:55:10 -0400
Subject: [PATCH 1/2] [SeparateConstOffsetFromGEP] Preserve inbounds flag based
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