llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-x86 Author: None (llvmbot) <details> <summary>Changes</summary> Backport fcce3084cb43a12f2e6e19b8e5b655f3df8739d6 Requested by: @<!-- -->phoebewang --- Full diff: https://github.com/llvm/llvm-project/pull/130774.diff 2 Files Affected: - (modified) llvm/lib/Target/X86/X86InstrSSE.td (+2-2) - (modified) llvm/test/CodeGen/X86/avx10_2_512ni-intrinsics.ll (+11) ``````````diff diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 6aadb788c851e..2a7ab1e310618 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -6121,8 +6121,9 @@ let Predicates = [HasAVX, NoAVX10_2] in { v8i16, VR128, load, i128mem, 0, SchedWriteMPSAD.XMM>, VEX, VVVV, WIG; } +} -let Uses = [MXCSR], mayRaiseFPException = 1 in { +let Predicates = [HasAVX], Uses = [MXCSR], mayRaiseFPException = 1 in { let ExeDomain = SSEPackedSingle in defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps, VR128, load, f128mem, 0, @@ -6136,7 +6137,6 @@ let Uses = [MXCSR], mayRaiseFPException = 1 in { VR256, load, i256mem, 0, SchedWriteDPPS.YMM>, VEX, VVVV, VEX_L, WIG; } -} let Predicates = [HasAVX2, NoAVX10_2] in { let isCommutable = 0 in { diff --git a/llvm/test/CodeGen/X86/avx10_2_512ni-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2_512ni-intrinsics.ll index 07e86cb01e133..b2e7caa15944c 100644 --- a/llvm/test/CodeGen/X86/avx10_2_512ni-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2_512ni-intrinsics.ll @@ -422,3 +422,14 @@ define { <32 x i16>, <32 x i16>, <32 x i16> } @test_mm512_mask_mpsadbw(<64 x i8> } declare <32 x i16> @llvm.x86.avx10.vmpsadbw.512(<64 x i8>, <64 x i8>, i8) + +; Regression test + +define <8 x float> @avx_dp_ps(<8 x float> %a, <8 x float> %b) { +; CHECK-LABEL: avx_dp_ps: +; CHECK: # %bb.0: +; CHECK-NEXT: vdpps $255, %ymm1, %ymm0, %ymm0 # encoding: [0xc4,0xe3,0x7d,0x40,0xc1,0xff] +; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] + %r = tail call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> %a, <8 x float> %b, i8 -1) + ret <8 x float> %r +} `````````` </details> https://github.com/llvm/llvm-project/pull/130774 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
