[llvm-branch-commits] [llvm] [RISCV] Support non-power-of-2 types when expanding memcmp (PR #114971)

@@ -2954,20 +2954,12 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { } if (IsZeroCmp && ST->hasVInstructions()) { -unsigned RealMinVLen = ST->getRealMinVLen(); -// Support Fractional LMULs if the lengths are larger than XLen. -// T

[llvm-branch-commits] [llvm] release/20.x: [RISCV] Fix assertion failure when using -fstack-clash-protection (#135248) (PR #139388)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/139388 >From ff4132ec328ed80be247856939dbf7345106cc55 Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Fri, 18 Apr 2025 09:12:52 -0700 Subject: [PATCH 1/2] [RISCV] Fix assertion failure when using -fstack-clash-protect

[llvm-branch-commits] [llvm] [RISCV] Support memcmp expansion for vectors (PR #114517)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/114517 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support memcmp expansion for vectors (PR #114517)

topperc wrote: Please don't @ me in the commit message. Sometimes when this commit gets pulled into some other fork of llvm I'll get an email that I don't want. https://github.com/llvm/llvm-project/pull/114517 ___ llvm-branch-commits mailing list llvm

[llvm-branch-commits] [llvm] release/20.x: [RISCV] Fix assertion failure when using -fstack-clash-protection (#135248) (PR #139388)

topperc wrote: @tstellar This is the fix. Can I push to this PR or do I need to make a new PR from my fork? ``` diff --git a/llvm/test/CodeGen/RISCV/pr135206.ll b/llvm/test/CodeGen/RISCV/pr135206.ll index 196e78d8ed8b..859179f62d70 100644 --- a/llvm/test/CodeGen/RISCV/pr135206.ll +++ b/llvm/te

[llvm-branch-commits] [llvm] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -2512,9 +2512,11 @@ bool RISCVTTIImpl::isProfitableToSinkOperands( RISCVTTIImpl::TTI::MemCmpExpansionOptions RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { TTI::MemCmpExpansionOptions Options; + // Here we assume that a core that has implemented

[llvm-branch-commits] [llvm] DAG: Move soft float predicate management into RuntimeLibcalls (PR #142905)

@@ -11,12 +11,48 @@ using namespace llvm; using namespace RTLIB; +void RuntimeLibcallsInfo::initSoftFloatCmpLibcallPredicates() { + std::fill(SoftFloatCompareLibcallPredicates, topperc wrote: Should we be using `std::begin(SoftFloatCompareLibcallPredicates)`

[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/139495 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)

@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt]; //===--===// let Predicates = [HasStdExtQ] in { - let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in - def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$r

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/139508 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] release/20.x: [RISCV] Allow `Zicsr`/`Zifencei` to duplicate with `g` (#136842) (PR #137490)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/137490 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV, test] Replace -riscv-no-aliases with -M no-aliases (PR #134879)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/134879 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: [Hexagon] Explicitly truncate constant in UAddSubO (#127360) (PR #127527)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/127527 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: [CG][RISCV]Fix shuffling of odd number of input vectors (PR #125910)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/125910 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: [Mips] Use getSignedConstant() in or combine (PR #126083)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/126083 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/20.x: [X86] Do not combine LRINT and TRUNC (#125848) (PR #125995)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/125995 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] DAG: Avoid stack usage in bitcast operand promotion to legal vector (PR #125637)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/125637 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [Driver] Change linker job in Baremetal toolchain object accomodate GCCInstallation.(2/3) (PR #121830)

@@ -36,6 +36,7 @@ class LLVM_LIBRARY_VISIBILITY BareMetal : public Generic_ELF { Tool *buildStaticLibTool() const override; public: + virtual bool isUsingLD() const { return UseLD || GCCInstallation.isValid(); } topperc wrote: Does this need to be virtual?

[llvm-branch-commits] [llvm] [TRI] Remove reserved registers in getRegPressureSetLimit (PR #118787)

topperc wrote: Do you know what caused the X86 changes? I don't see any uses of getRegPressureSetLimit in the X86 directory. https://github.com/llvm/llvm-project/pull/118787 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https

[llvm-branch-commits] [llvm] [TRI] Remove reserved registers in getRegPressureSetLimit (PR #118787)

@@ -1198,6 +1198,14 @@ define <32 x i8> @out_v32i8(ptr%px, ptr%py, ptr%pmask) nounwind { ; CHECK-BASELINE-NEXT:movq %rdx, %r8 ; CHECK-BASELINE-NEXT:movq %rsi, %r9 ; CHECK-BASELINE-NEXT:movq %rdi, %r11 +; CHECK-BASELINE-NEXT:movzbl 19(%rdx), %eax ---

[llvm-branch-commits] [llvm] [TRI] Remove reserved registers in getRegPressureSetLimit (PR #118787)

topperc wrote: Description needs to be updated if MachineLICM, MachineSink, MachinePipeliner have been migrated to RegisterClassInfo. https://github.com/llvm/llvm-project/pull/118787 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.

[llvm-branch-commits] [llvm] release/19.x: [RISCV] Don't create BuildPairF64 or SplitF64 nodes without D or Zdinx. (#116159) (PR #121501)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/121501 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [RISCV] Don't create BuildPairF64 or SplitF64 nodes without D or Zdinx. (#116159) (PR #121501)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/121501 The fix in ReplaceNodeResults is the only one really required for the known crash. I couldn't hit the case in LowerOperation because that requires (f64 (bitcast i64)), but the result type is softened before th

[llvm-branch-commits] [llvm] release/19.x: [RISCV] Don't create BuildPairF64 or SplitF64 nodes without D or Zdinx. (#116159) (PR #121501)

https://github.com/topperc milestoned https://github.com/llvm/llvm-project/pull/121501 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [RISCV] Don't create BuildPairF64 or SplitF64 nodes without D or Zdinx. (#116159) (PR #121175)

topperc wrote: Going to manually cherry-pick to fix the test checks. https://github.com/llvm/llvm-project/pull/121175 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-co

[llvm-branch-commits] [llvm] release/19.x: [RISCV] Don't create BuildPairF64 or SplitF64 nodes without D or Zdinx. (#116159) (PR #121175)

https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/121175 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [RISCV] Don't create BuildPairF64 or SplitF64 nodes without D or Zdinx. (#116159) (PR #121175)

topperc wrote: Looks like the lit test didn't cherry-pick cleanly https://github.com/llvm/llvm-project/pull/121175 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commi

[llvm-branch-commits] [llvm] [TRI] Remove reserved registers in getRegPressureSetLimit (PR #118787)

topperc wrote: Should we just rename the TRI function to discourage use and encourage everyone to use RegClassInfo? https://github.com/llvm/llvm-project/pull/118787 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.

[llvm-branch-commits] [CodeGen] Use cached version of getRegPressureSetLimit (PR #119194)

topperc wrote: Why do we need #118787 if we can just update the passes to use RegisterClassInfo? https://github.com/llvm/llvm-project/pull/119194 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/ma

[llvm-branch-commits] [llvm] [RISCV] Add TuneDisableLatencySchedHeuristic (PR #115858)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/115858 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Add FeatureDisableLatencySchedHeuristic (PR #115858)

@@ -1390,6 +1390,10 @@ def FeaturePredictableSelectIsExpensive : SubtargetFeature<"predictable-select-expensive", "PredictableSelectIsExpensive", "true", "Prefer likely predicted branches over selects">; +def FeatureDisableLatencySchedHeuristic

[llvm-branch-commits] [llvm] release/19.x: [SDAG][ISel][TableGen][LoongArch] Report error for trivial bitcasts when there are predicate calls (#116075) (PR #116797)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/116797 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/116231 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

@@ -22505,6 +22506,47 @@ Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID, return nullptr; } +Value *CodeGenFunction::EmitRISCVCpuIs(const CallExpr *E) { + const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts(); + StringRef CPUStr = cast(CPUExpr)->getStri

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

@@ -22505,6 +22506,47 @@ Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID, return nullptr; } +Value *CodeGenFunction::EmitRISCVCpuIs(const CallExpr *E) { + const Expr *CPUExpr = E->getArg(0)->IgnoreParenCasts(); + StringRef CPUStr = cast(CPUExpr)->getStri

[llvm-branch-commits] [clang] [llvm] [RISCV] Support __builtin_cpu_is (PR #116231)

@@ -508,3 +508,11 @@ bool RISCVTargetInfo::validateGlobalRegisterVariable( } return false; } + +bool RISCVTargetInfo::validateCpuIs(StringRef CPUName) const { + llvm::Triple Triple = getTriple(); topperc wrote: Unused variable in release build https://gi

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

https://github.com/topperc approved this pull request. LGTM, but wait for another review. https://github.com/llvm/llvm-project/pull/107548 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/li

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

topperc wrote: > > > Can we break the enabling down into more manageable pieces? I think > > > `enableUnalignedScalarMem() && (Subtarget->hasStdExtZbb() || > > > Subtarget->hasStdExtZbkb() || IsZeroCmp)` might be a good starting point. > > > > > > I'd be fine with this type of approach. > >

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -315,967 +3233,10985 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-RV32: # %bb.0: # %entry ; CHECK-RV32-NEXT:addi sp, sp, -16 ; CHECK-RV32-NEXT:sw ra, 12(sp) # 4-byte Folded Spill -; CHECK-RV32-NEXT:li a2, 31 +; CHECK-RV32-NEXT:

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -14474,17 +14475,116 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &D return true; } +/// Recursive helper for combineVectorSizedSetCCEquality() to see if we have a +/// recognizable memcmp expansion. +static bool isOrXorXorTree(SDValue

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -2504,5 +2504,10 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { Options.LoadSizes = {8, 4, 2, 1}; else Options.LoadSizes = {4, 2, 1}; + if (IsZeroCmp && ST->hasVInstructions()) { +unsigned RealMinVLen = ST->getRealMinVLen() / 8;

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -14474,17 +14475,116 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &D return true; } +/// Recursive helper for combineVectorSizedSetCCEquality() to see if we have a +/// recognizable memcmp expansion. +static bool isOrXorXorTree(SDValue

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -3186,190 +3186,24 @@ define i32 @bcmp_size_16(ptr %s1, ptr %s2) nounwind { ; ; CHECK-ALIGNED-RV32-V-LABEL: bcmp_size_16: ; CHECK-ALIGNED-RV32-V: # %bb.0: # %entry -; CHECK-ALIGNED-RV32-V-NEXT:lbu a2, 1(a0) -; CHECK-ALIGNED-RV32-V-NEXT:lbu a3, 0(a0) -; CHECK-AL

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -14474,17 +14475,116 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &D return true; } +/// Recursive helper for combineVectorSizedSetCCEquality() to see if we have a +/// recognizable memcmp expansion. +static bool isOrXorXorTree(SDValue

[llvm-branch-commits] [RISCV] Support memcmp expansion for vectors (PR #114517)

@@ -14474,17 +14475,116 @@ static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &D return true; } +/// Recursive helper for combineVectorSizedSetCCEquality() to see if we have a +/// recognizable memcmp expansion. +static bool isOrXorXorTree(SDValue

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -315,967 +3233,10985 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-RV32: # %bb.0: # %entry ; CHECK-RV32-NEXT:addi sp, sp, -16 ; CHECK-RV32-NEXT:sw ra, 12(sp) # 4-byte Folded Spill -; CHECK-RV32-NEXT:li a2, 31 +; CHECK-RV32-NEXT:

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -315,967 +3233,10985 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-RV32: # %bb.0: # %entry ; CHECK-RV32-NEXT:addi sp, sp, -16 ; CHECK-RV32-NEXT:sw ra, 12(sp) # 4-byte Folded Spill -; CHECK-RV32-NEXT:li a2, 31 +; CHECK-RV32-NEXT:

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -1144,42 +2872,116 @@ entry: define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV32-LABEL: memcmp_size_4: ; CHECK-ALIGNED-RV32: # %bb.0: # %entry -; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16 -; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte

[llvm-branch-commits] [llvm] [RISCV] fix RISCVPushPopOptimizer pass (PR #110813)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/110813 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -1144,42 +2872,116 @@ entry: define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV32-LABEL: memcmp_size_4: ; CHECK-ALIGNED-RV32: # %bb.0: # %entry -; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16 -; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -112,42 +104,46 @@ entry: define i32 @bcmp_size_2(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV32-LABEL: bcmp_size_2: ; CHECK-ALIGNED-RV32: # %bb.0: # %entry -; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16 -; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

topperc wrote: > Ping. > > And some updates on vector support: currently, `ExpandMemCmp` will only > generate integer types (`i128`, `i256` and so on). So, if we simply add > `128`, `256`, `vlen` to `LoadSizes`, the LLVM IR will use `i128`/`i256`/... > and then they are expanded to legal scal

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -1144,42 +2872,116 @@ entry: define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV32-LABEL: memcmp_size_4: ; CHECK-ALIGNED-RV32: # %bb.0: # %entry -; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16 -; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

topperc wrote: > The run just finished, I'm seeing a 0.75% improvement on 500.perlbench_r on > the BPI F3 (-O3 -mcpu=spacemit-x60), no regressions or improvements on the > other benchmarks as far as I can see. Seems to check out with the number of > memcmps inlined reported for perlbench! Doe

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -1144,42 +2872,116 @@ entry: define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV32-LABEL: memcmp_size_4: ; CHECK-ALIGNED-RV32: # %bb.0: # %entry -; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16 -; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/107548 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -2113,3 +2113,17 @@ bool RISCVTTIImpl::shouldConsiderAddressTypePromotion( } return Considerable; } + +RISCVTTIImpl::TTI::MemCmpExpansionOptions +RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { + TTI::MemCmpExpansionOptions Options; + // FIXME

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -112,42 +104,46 @@ entry: define i32 @bcmp_size_2(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV32-LABEL: bcmp_size_2: ; CHECK-ALIGNED-RV32: # %bb.0: # %entry -; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16 -; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte

[llvm-branch-commits] [llvm] [RISCV] Add initial support of memcmp expansion (PR #107548)

@@ -1144,42 +2872,116 @@ entry: define i32 @memcmp_size_4(ptr %s1, ptr %s2) nounwind { ; CHECK-ALIGNED-RV32-LABEL: memcmp_size_4: ; CHECK-ALIGNED-RV32: # %bb.0: # %entry -; CHECK-ALIGNED-RV32-NEXT:addi sp, sp, -16 -; CHECK-ALIGNED-RV32-NEXT:sw ra, 12(sp) # 4-byte

[llvm-branch-commits] [llvm] release/19.x: [RISCV] Use experimental.vp.splat to splat specific vector length elements. (#101329) (PR #101506)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/101506 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/19.x: [VP] Refactor VectorBuilder to avoid layering violation. NFC (#99276) (PR #101102)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/101102 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [compiler-rt] Revert "[compiler-rt][RISCV] Implement __init_riscv_feature_bits (#85… (PR #101320)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/101320 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -2155,6 +2155,17 @@ bool RISCVAsmParser::parseVTypeToken(const AsmToken &Tok, VTypeState &State, break; if (!RISCVVType::isValidLMUL(Lmul, Fractional)) break; + +if (Fractional) { + unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 :

[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -71,18 +73,21 @@ vsetvli a2, a0, e32, m8, ta, ma vsetvli a2, a0, e32, mf2, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma +# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 16 may not be compatible with all RVV implementations{{$}} # CHECK-ENCODING: [0x57,0x76,0x75

[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -71,18 +73,21 @@ vsetvli a2, a0, e32, m8, ta, ma vsetvli a2, a0, e32, mf2, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma +# CHECK-WARNING: :[[#@LINE-2]]:17: warning: SEW > 16 may not be compatible with all RVV implementations{{$}} # CHECK-ENCODING: [0x57,0x76,0x75

[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -2155,6 +2155,17 @@ bool RISCVAsmParser::parseVTypeToken(const AsmToken &Tok, VTypeState &State, break; if (!RISCVVType::isValidLMUL(Lmul, Fractional)) break; + +if (Fractional) { + unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 :

[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -2155,6 +2155,17 @@ bool RISCVAsmParser::parseVTypeToken(const AsmToken &Tok, VTypeState &State, break; if (!RISCVVType::isValidLMUL(Lmul, Fractional)) break; + +if (Fractional) { + unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 :

[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -2211,6 +2223,18 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector &Operands) { if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) { RISCVII::VLMUL VLMUL = RISCVVType::encodeLMUL(Lmul, Fractional); +if (Fractional) { + unsigned E

[llvm-branch-commits] [RISCV][MC] Warn if SEW/LMUL may not be compatible (PR #94313)

@@ -2155,6 +2155,17 @@ bool RISCVAsmParser::parseVTypeToken(const AsmToken &Tok, VTypeState &State, break; if (!RISCVVType::isValidLMUL(Lmul, Fractional)) break; + +if (Fractional) { + unsigned ELEN = STI->hasFeature(RISCV::FeatureStdExtZve64x) ? 64 :

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

topperc wrote: > @topperc (or anyone else). If you would like to add a note about this fix in > the release notes (completely optional). Please reply to this comment with a > one or two sentence description of the fix. When you are done, please add the > release:note label to this PR. `-Xclan

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

topperc wrote: > @topperc Can this be merged as is? There might not be time to get an updated > patch merged before the last release. I just pushed a modified patch. What is the timeline for the last release? https://github.com/llvm/llvm-project/pull/92143 _

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/92143 >From e18e442947da7801c915c04e34e397464eca5034 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 16 May 2024 12:27:05 -0700 Subject: [PATCH] [RISCV] Add a unaligned-scalar-mem feature like we had in clang 1

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

topperc wrote: > I'm not strongly opposed to this or anything, but it feels questionable to be > doing a backport to change the target-feature syntax. My understand is that > these are purely internal names. This isn't a documented public interface. It isn't documented, but some users were usi

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

topperc wrote: > I don't think we need to backport this at all. None of the in tree cpus fall > into the category where the distinction is important, and I don't feel we > have any obligation to backport support for our of tree forks. There's no out of tree fork involved here. The bug reporter

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

topperc wrote: Maybe I could make fast-unaligned-access only apply to scalar to avoid a name change. And give a new flag for vector? There's not a lot of RISC-V vector hardware available yet. One of the CPUs that is available only supports unaligned scalars and not vectors. https://github.com

[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)

topperc wrote: > @topperc Do you have any strong objections to backporting this? This looks > small to me and I think it's OK to fix long-standing bugs. No objection. https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing li

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

topperc wrote: > > Note that backporting this may require changes for LLVM users (I know that > > it will require rustc changes at least). This may not be a good candidate > > for the last 18.1 point release. > > Can you point me to the relevant rust code? I found this line which looks > like

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

topperc wrote: > Note that backporting this may require changes for LLVM users (I know that it > will require rustc changes at least). This may not be a good candidate for > the last 18.1 point release. Can you point me to the relevant rust code? I found this line which looks like it wasn't u

[llvm-branch-commits] [llvm] release/18.x: [X86][Driver] Do not add `-evex512` for `-march=native` when the target doesn't support AVX512 (#91694) (PR #91705)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/91705 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/92143 Backport 9067070d91e9d8cdd8509ffa56a076f08a3d7281 for #92134 >From 5c5c57534751621f775dca5776af10e1870e6eb8 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 16 Apr 2024 15:40:32 -0700 Subject: [PATCH] [RIS

[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)

https://github.com/topperc milestoned https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)

topperc wrote: > Can you briefly summarize why this is important to backport? At first glance, > this is only relevant for LTO with mixed architecture specifications, > which... I can see someone might want it, I guess, but it seems pretty easy > to work around not having it. It's not just mi

[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/91514 >From ee109e3627e5b93297bfc7908f684eedb5feb5ec Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 13 Feb 2024 16:17:50 -0800 Subject: [PATCH 1/3] [RISCV] Add canonical ISA string as Module metadata in IR. (#

[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/91514 Resolves #91513 >From f45df1cf1b74957e2f9609b982e964654f9af824 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 13 Feb 2024 16:17:50 -0800 Subject: [PATCH 1/3] [RISCV] Add canonical ISA string as Module me

[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)

https://github.com/topperc milestoned https://github.com/llvm/llvm-project/pull/91514 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)

topperc wrote: @AtariDreams This bug has existed since at least LLVM 10. What makes it a candidate for backporting? https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.l

[llvm-branch-commits] [llvm] release/18.x: [X86] Enable EVEX512 when host CPU has AVX512 (#90479) (PR #90545)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90545 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [RISCV][ISel] Fix types in `tryFoldSelectIntoOp` (#90659) (PR #90682)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90682 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

@@ -194,15 +194,12 @@ define void @vpmerge_vpload_store( %passthru, ptr %p, , i64 } @llvm.riscv.vleff.nxv2i32(, ptr, i64) define @vpmerge_vleff( %passthru, ptr %p, %m, i32 zeroext %vl) { ; CHECK-LABEL: vpmerge_vleff: ; CHECK: # %bb.0: -; CHECK-NEXT:vsetvli zero, a

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

@@ -47,6 +47,12 @@ include "RISCVSchedSiFiveP600.td" include "RISCVSchedSyntacoreSCR1.td" include "RISCVSchedXiangShanNanHu.td" +//===--===// +// RISC-V profiles supported. +//===--

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

topperc wrote: > For saturating instructions, they may write vxsat. This is like floating-point instructions that may write fflags, but we don't model floating-point instructions as hasSideEffects=1. That's because floating point instructions use mayRaiseFPExceptions=1. And STRICT_* nodes set d

[llvm-branch-commits] [llvm] release/18.x: [X86] Fix miscompile in combineShiftRightArithmetic (PR #86728)

topperc wrote: > > @phoebewang What do you think about backporting this? > > I didn't review on it. Maybe @topperc can evaluate it. I think this is ok to backport. https://github.com/llvm/llvm-project/pull/86728 ___ llvm-branch-commits mailing list l

[llvm-branch-commits] [llvm] Revert "[Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072)" (PR #88818)

topperc wrote: > > Hi @nikic (or anyone else). If you would like to add a note about this fix > > in the release notes (completely optional). Please reply to this comment > > with a one or two sentence description of the fix. > > I'm not sure if this description is accurate: Fix the issue wher

[llvm-branch-commits] [RISCV] Use the thread local stack protector for Android targets (PR #87672)

topperc wrote: > s/master/main/ in the url to get the current version. (master "works" but > it's frozen in time; main will track future changes.) > > otherwise lgtm... Probably someone should update AArch64 which has the same comment? https://github.com/llvm/llvm-project/pull/87672 _

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -212,19 +185,13 @@ body: | ; CHECK-NEXT: $v7 = VMV1R_V $v14 ; CHECK-NEXT: $v8 = VMV1R_V $v15 ; CHECK-NEXT: $v9 = VMV1R_V $v16 -; CHECK-NEXT: $v4 = VMV1R_V $v10 -; CHECK-NEXT: $v5 = VMV1R_V $v11 -; CHECK-NEXT: $v6 = VMV1R_V $v12 -; CHEC

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -212,19 +185,13 @@ body: | ; CHECK-NEXT: $v7 = VMV1R_V $v14 ; CHECK-NEXT: $v8 = VMV1R_V $v15 ; CHECK-NEXT: $v9 = VMV1R_V $v16 -; CHECK-NEXT: $v4 = VMV1R_V $v10 -; CHECK-NEXT: $v5 = VMV1R_V $v11 -; CHECK-NEXT: $v6 = VMV1R_V $v12 -; CHEC

[llvm-branch-commits] [llvm] release/18.x: [Mips] Restore wrong deletion of instruction 'and' in unsigned min/max processing. (#85902) (PR #86424)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/86424 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

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