https://github.com/vitalybuka updated
https://github.com/llvm/llvm-project/pull/137103
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https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87575
>From 1a8d810d352fbe84c0521c7614689b60ade693c8 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Tue, 19 Nov 2024 15:25:34 -0800
Subject: [PATCH 1/5] Fixed the tests and addressed most of the review
comm
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Vitaly Buka (vitalybuka)
Changes
It was introduced with original "minimal runtime"
patch without explanation:
https://reviews.llvm.org/D36810#:~:text=if%20(-,NonTrappingCfi,-)
The same commit contains `cfi_check_fail` handler,
which can no
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87575
>From 1a8d810d352fbe84c0521c7614689b60ade693c8 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Tue, 19 Nov 2024 15:25:34 -0800
Subject: [PATCH 1/5] Fixed the tests and addressed most of the review
comm
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87576
>From 6b67376bd5e1f21606017c83cc67f2186ba36a33 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Thu, 13 Mar 2025 01:41:04 +
Subject: [PATCH 1/4] Updated the test as reviewers suggested.
Created usin
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87574
>From 1d7ee612e408ee7e64e984eb08e6d7089a435d09 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Sun, 2 Feb 2025 00:58:49 +
Subject: [PATCH 1/5] Simplify MIR test.
Created using spr 1.3.6-beta.1
---
https://github.com/vitalybuka created
https://github.com/llvm/llvm-project/pull/137103
It was introduced with original "minimal runtime"
patch without explanation:
https://reviews.llvm.org/D36810#:~:text=if%20(-,NonTrappingCfi,-)
The same commit contains `cfi_check_fail` handler,
which can not
arsenm wrote:
> If the data layout doesn't match the target, the module is already broken to
> begin with, and any optimization that relies on data layout information can't
> be expected to work correctly.
This is not how the semantics of the datalayout works, particularly with the
alloca ad
@@ -95,14 +95,24 @@ static MachineInstr *FindDominatedInstruction(MachineInstr
&New,
return Old;
}
+static bool isCodeMotionBarrier(MachineInstr &MI) {
+ return MI.hasUnmodeledSideEffects() && !MI.isPseudoProbe();
+}
+
/// Builds Instruction to its dominating order number
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87574
>From 1d7ee612e408ee7e64e984eb08e6d7089a435d09 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Sun, 2 Feb 2025 00:58:49 +
Subject: [PATCH 1/4] Simplify MIR test.
Created using spr 1.3.6-beta.1
---
Author: Henrik G. Olsson
Date: 2025-04-23T16:48:29-07:00
New Revision: 30f38f86a765a24e368083ffbcac9f036e6fc221
URL:
https://github.com/llvm/llvm-project/commit/30f38f86a765a24e368083ffbcac9f036e6fc221
DIFF:
https://github.com/llvm/llvm-project/commit/30f38f86a765a24e368083ffbcac9f036e6fc221.di
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87575
>From 1a8d810d352fbe84c0521c7614689b60ade693c8 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Tue, 19 Nov 2024 15:25:34 -0800
Subject: [PATCH 1/5] Fixed the tests and addressed most of the review
comm
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/117037
>From 6a12be2c5b60a95a06875b0b2c4f14228d1fa882 Mon Sep 17 00:00:00 2001
From: prabhukr
Date: Wed, 12 Mar 2025 23:30:01 +
Subject: [PATCH] Fix EOF newlines.
Created using spr 1.3.6-beta.1
---
clang/test/Dri
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/117036
>From b7fbe09b32ff02d4f7c52d82fbf8b5cd28138852 Mon Sep 17 00:00:00 2001
From: prabhukr
Date: Wed, 23 Apr 2025 04:05:47 +
Subject: [PATCH] Address review comments.
Created using spr 1.3.6-beta.1
---
clang/l
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87576
>From 6b67376bd5e1f21606017c83cc67f2186ba36a33 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Thu, 13 Mar 2025 01:41:04 +
Subject: [PATCH 1/4] Updated the test as reviewers suggested.
Created usin
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/117036
>From b7fbe09b32ff02d4f7c52d82fbf8b5cd28138852 Mon Sep 17 00:00:00 2001
From: prabhukr
Date: Wed, 23 Apr 2025 04:05:47 +
Subject: [PATCH] Address review comments.
Created using spr 1.3.6-beta.1
---
clang/l
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/117037
>From 6a12be2c5b60a95a06875b0b2c4f14228d1fa882 Mon Sep 17 00:00:00 2001
From: prabhukr
Date: Wed, 12 Mar 2025 23:30:01 +
Subject: [PATCH] Fix EOF newlines.
Created using spr 1.3.6-beta.1
---
clang/test/Dri
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87576
>From 6b67376bd5e1f21606017c83cc67f2186ba36a33 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Thu, 13 Mar 2025 01:41:04 +
Subject: [PATCH 1/4] Updated the test as reviewers suggested.
Created usin
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87575
>From 1a8d810d352fbe84c0521c7614689b60ade693c8 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Tue, 19 Nov 2024 15:25:34 -0800
Subject: [PATCH 1/5] Fixed the tests and addressed most of the review
comm
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87574
>From 1d7ee612e408ee7e64e984eb08e6d7089a435d09 Mon Sep 17 00:00:00 2001
From: Necip Fazil Yildiran
Date: Sun, 2 Feb 2025 00:58:49 +
Subject: [PATCH 1/4] Simplify MIR test.
Created using spr 1.3.6-beta.1
---
https://github.com/Prabhuk updated
https://github.com/llvm/llvm-project/pull/87573
>From a8a5848885e12c771f12cfa33b4dbc6a0272e925 Mon Sep 17 00:00:00 2001
From: Prabhuk
Date: Mon, 22 Apr 2024 11:34:04 -0700
Subject: [PATCH 01/11] Update clang/lib/CodeGen/CodeGenModule.cpp
Cleaner if checks.
C
https://github.com/bogner approved this pull request.
LGTM!
https://github.com/llvm/llvm-project/pull/135287
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@@ -95,14 +95,24 @@ static MachineInstr *FindDominatedInstruction(MachineInstr
&New,
return Old;
}
+static bool isCodeMotionBarrier(MachineInstr &MI) {
+ return MI.hasUnmodeledSideEffects() && !MI.isPseudoProbe();
+}
pcc wrote:
Added a comment that descri
https://github.com/pcc updated https://github.com/llvm/llvm-project/pull/136806
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https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From 9d2612c4379eb827406642b508f2dce32fc13e59 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
@@ -594,6 +599,25 @@ struct RootConstants {
sys::swapByteOrder(Num32BitValues);
}
};
+struct RootDescriptor_V1_0 {
inbelic wrote:
Having poked a bit more in `DXContainer.h`, maybe it would be best to follow
how it is done for `RuntimeInfo`? Defining a n
@@ -4723,20 +4723,25 @@ def HLSLResourceBinding: InheritableAttr {
private:
RegisterType RegType;
- unsigned SlotNumber;
+ int SlotNumber; // -1 if the register slot was not specified
hekota wrote:
Good catch! DXC actually ignores the regist
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From 2d75ec2eb1a927513bb92bcb26e313a3831426ef Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From 9d2612c4379eb827406642b508f2dce32fc13e59 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/133627
>From bded004e4d4dbaf311de6d1bfbb2d443bad023cc Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 24 Mar 2025 14:33:36 +0700
Subject: [PATCH 1/2] llvm-reduce: Reduce with early return of arguments
Extend t
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From 2d75ec2eb1a927513bb92bcb26e313a3831426ef Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
https://github.com/bogner approved this pull request.
https://github.com/llvm/llvm-project/pull/136751
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https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/134794
>From 1fc34663dcfcc3225045758dedc5c3323d597005 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 8 Apr 2025 11:16:01 +0700
Subject: [PATCH] llvm-reduce: Support exotic terminators in
instructions-to-retur
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/134035
>From bcc2f289ed8fffb998693bce4931bb65f3ad165b Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 2 Apr 2025 11:45:24 +0700
Subject: [PATCH 1/4] llvm-reduce: Change function return types if function is
not
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/134035
>From bcc2f289ed8fffb998693bce4931bb65f3ad165b Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Wed, 2 Apr 2025 11:45:24 +0700
Subject: [PATCH 1/4] llvm-reduce: Change function return types if function is
not
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/133627
>From bded004e4d4dbaf311de6d1bfbb2d443bad023cc Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Mon, 24 Mar 2025 14:33:36 +0700
Subject: [PATCH 1/2] llvm-reduce: Reduce with early return of arguments
Extend t
https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/134794
>From 1fc34663dcfcc3225045758dedc5c3323d597005 Mon Sep 17 00:00:00 2001
From: Matt Arsenault
Date: Tue, 8 Apr 2025 11:16:01 +0700
Subject: [PATCH] llvm-reduce: Support exotic terminators in
instructions-to-retur
@@ -339,6 +369,198 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
}
}
+ std::optional>
+ getAuthCheckedReg(BinaryBasicBlock &BB) const override {
+// Match several possible hard-coded sequences of instructions which can be
+// emitted by LLVM backend to
@@ -701,6 +705,11 @@ class DwarfDebug : public DebugHandlerBase {
void findForceIsStmtInstrs(const MachineFunction *MF);
+ /// Find instructions which should get is_stmt applied because they implement
+ /// key functionality for a source atom, store results in
+ /// Dwar
https://github.com/jmorse edited
https://github.com/llvm/llvm-project/pull/133495
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https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From 8b975d26cd4540ad95bdaafb02a0f48154cb57f1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/136798
>From 8b975d26cd4540ad95bdaafb02a0f48154cb57f1 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 23 Apr 2025 09:17:46 -0400
Subject: [PATCH] [AMDGPU] Make `AllocaInst` return AS5 in
`getAssumedAddrSpace`
damyanp wrote:
Is this ready to retarget to main?
https://github.com/llvm/llvm-project/pull/136747
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@@ -0,0 +1,78 @@
+# RUN: llc %s --start-after=livedebugvalues --dwarf-use-key-instructions
--filetype=obj -o - \
+# RUN: | llvm-objdump -d - --no-show-raw-insn \
+# RUN: | FileCheck %s --check-prefix=OBJ
+
+# RUN: llc %s --start-after=livedebugvalues --dwarf-use-key-instructions
https://github.com/inbelic edited
https://github.com/llvm/llvm-project/pull/137038
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llvmbot wrote:
@llvm/pr-subscribers-hlsl
Author: Finn Plummer (inbelic)
Changes
- defines the special values for `DESCRIPTOR_RANGE_OFFSET_APPEND` and
`unbounded` for the `offset` and `numDescriptors` parameters
respectively
- adds these parmaters to the `DescriptorClause` struct and the p
https://github.com/inbelic created
https://github.com/llvm/llvm-project/pull/137038
- defines the special values for `DESCRIPTOR_RANGE_OFFSET_APPEND` and
`unbounded` for the `offset` and `numDescriptors` parameters
respectively
- adds these parmaters to the `DescriptorClause` struct and the par
shiltian wrote:
> In the real world, people emit address space 0 allocas all over the place and
> then report backend bugs when it fails in codegen
Technically we can avoid that by just hard error
https://github.com/llvm/llvm-project/pull/136865
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https://github.com/HazardyKnusperkeks approved this pull request.
https://github.com/llvm/llvm-project/pull/136808
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https://github.com/ilovepi approved this pull request.
LGTM once all the dependent patches are landed.
https://github.com/llvm/llvm-project/pull/117037
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@@ -73,24 +75,50 @@ struct ShaderHash {
std::vector Digest;
};
-#define ROOT_ELEMENT_FLAG(Num, Val) bool Val = false;
-
struct RootConstantsYaml {
uint32_t ShaderRegister;
uint32_t RegisterSpace;
uint32_t Num32BitValues;
};
+#define ROOT_DESCRIPTOR_FLAG(Num, Val
jmorse wrote:
It can't hurt, let's making things slightly more correct!
https://github.com/llvm/llvm-project/pull/133492
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@@ -12603,6 +12603,18 @@ struct AAAddressSpaceImpl : public AAAddressSpace {
auto CheckAddressSpace = [&](Value &Obj) {
if (isa(&Obj))
return true;
+ // Some targets relax the requirement for alloca to be in an exact
address
+ // space, allowing it
inbelic wrote:
Maybe this was covered in the first pr. But are there tests that cover both big
and little endian?
https://github.com/llvm/llvm-project/pull/136732
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OCHyams wrote:
> Seems fine; although why's it needed for key instructions, I have a vague
> recollection that LLVM doesn't actually care about the source locations
> attached to PHIs?
The motivation came from reviewing code duplication sites to update for Key
Instructions, finding this, tryi
@@ -2860,9 +2861,23 @@ static void setLinkageForGV(llvm::GlobalValue *GV, const
NamedDecl *ND) {
GV->setLinkage(llvm::GlobalValue::ExternalWeakLinkage);
}
-void CodeGenModule::CreateFunctionTypeMetadataForIcall(const FunctionDecl *FD,
+static bool hasExistingGeneralizedTy
shiltian wrote:
> The A field does not assert anything about the content of the module. It does
> not assert that any alloca with a non-A valued alloca can be replaced with an
> A address space alloca. An alloca that does not match this address space is
> not invalid, and you cannot say anythi
https://github.com/inbelic edited
https://github.com/llvm/llvm-project/pull/136732
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@@ -594,6 +599,25 @@ struct RootConstants {
sys::swapByteOrder(Num32BitValues);
}
};
+struct RootDescriptor_V1_0 {
inbelic wrote:
IIUC, this is how the structs were defined and planned to be extended in DXC.
And I believe it was also documented there th
@@ -89,6 +111,15 @@ DXContainerYAML::RootSignatureYamlDesc::create(
return RootSigDesc;
}
+uint32_t DXContainerYAML::RootDescriptorYaml::getEncodedFlags() const {
+ uint64_t Flag = 0;
+#define ROOT_DESCRIPTOR_FLAG(Num, Val)
\
+ if (
@@ -73,24 +75,50 @@ struct ShaderHash {
std::vector Digest;
};
-#define ROOT_ELEMENT_FLAG(Num, Val) bool Val = false;
-
struct RootConstantsYaml {
uint32_t ShaderRegister;
uint32_t RegisterSpace;
uint32_t Num32BitValues;
};
+#define ROOT_DESCRIPTOR_FLAG(Num, Val
@@ -2860,9 +2861,25 @@ static void setLinkageForGV(llvm::GlobalValue *GV, const
NamedDecl *ND) {
GV->setLinkage(llvm::GlobalValue::ExternalWeakLinkage);
}
+static bool HasExistingGeneralizedTypeMD(llvm::Function *F) {
+ llvm::MDNode *MD = F->getMetadata(llvm::LLVMContext
@@ -1619,9 +1619,12 @@ class CodeGenModule : public CodeGenTypeCache {
llvm::Metadata *CreateMetadataIdentifierGeneralized(QualType T);
/// Create and attach type metadata to the given function.
- void CreateFunctionTypeMetadataForIcall(const FunctionDecl *FD,
+ void cre
shiltian wrote:
> This looks like an attempt to fix up broken IR producers, but I guess that's
> not it?
Yeah, I initially thought that was broken IR too. At first, I was in favor of
not allowing alloca in AS0 at all and just making it a verifier error, like
what was done in
https://github.c
https://github.com/kbeyls commented:
Apologies for only reviewing piece-meal. I'm struggling a bit at the time to
reserve longer blocks of time to review this fully in one go.
I hope my comments still make sense though
https://github.com/llvm/llvm-project/pull/134146
___
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=infer-address-spaces %s -o -
| FileCheck %s
+
+declare void @bar(ptr)
+
+define i32 @static_alloca() {
+; CHECK-LAB
@@ -339,6 +369,183 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
}
}
+ std::optional>
+ getAuthCheckedReg(BinaryBasicBlock &BB) const override {
+// Match several possible hard-coded sequences of instructions which can be
+// emitted by LLVM backend to
shiltian wrote:
I've updated the PR to use `getAssumedAddrSpace`, which is same as what
`InferAddressSpacePass` does. @arsenm @nikic
https://github.com/llvm/llvm-project/pull/136865
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@@ -339,6 +369,183 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
}
}
+ std::optional>
+ getAuthCheckedReg(BinaryBasicBlock &BB) const override {
+// Match several possible hard-coded sequences of instructions which can be
+// emitted by LLVM backend to
@@ -0,0 +1,78 @@
+# RUN: llc %s --start-after=livedebugvalues --dwarf-use-key-instructions
--filetype=obj -o - \
+# RUN: | llvm-objdump -d - --no-show-raw-insn \
+# RUN: | FileCheck %s --check-prefix=OBJ
+
+# RUN: llc %s --start-after=livedebugvalues --dwarf-use-key-instructions
@@ -0,0 +1,117 @@
+; RUN: llc %s --filetype=obj -o - --dwarf-use-key-instructions \
+; RUN: | llvm-objdump -d - --no-show-raw-insn \
+; RUN: | FileCheck %s --check-prefix=OBJ
+
+; RUN: llc %s --filetype=obj -o - --dwarf-use-key-instructions \
+; RUN: | llvm-dwarfdump - --debug-lin
https://github.com/jmorse commented:
Tests: I'd personally prefer the input source and explanation at the top of the
file, although this is a style thing.
My understanding of this code is that within a basic block, it should be
possible for there to be two sequences of instructions of equal gr
https://github.com/kbeyls edited
https://github.com/llvm/llvm-project/pull/134146
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@@ -2333,6 +2352,170 @@ DwarfDebug::emitInitialLocDirective(const
MachineFunction &MF, unsigned CUID) {
return PrologEndLoc;
}
+void DwarfDebug::findKeyInstructions(const MachineFunction *MF) {
+ // New function - reset KeyInstructions.
+ KeyInstructions.clear();
+
+ //
@@ -0,0 +1,304 @@
+//===- LowerContractionToSMMLAPattern.cpp - Contract to SMMLA ---*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -2333,6 +2352,170 @@ DwarfDebug::emitInitialLocDirective(const
MachineFunction &MF, unsigned CUID) {
return PrologEndLoc;
}
+void DwarfDebug::findKeyInstructions(const MachineFunction *MF) {
+ // New function - reset KeyInstructions.
+ KeyInstructions.clear();
+
+ //
https://github.com/SamTebbs33 created
https://github.com/llvm/llvm-project/pull/136997
This PR adds support for extensions of different signedness to
VPMulAccumulateReductionRecipe and allows such partial reductions to be bundled
into that class.
>From 10c4727074a7f5b4502ad08dc655be8fa5ffa3d2
@@ -2333,6 +2352,170 @@ DwarfDebug::emitInitialLocDirective(const
MachineFunction &MF, unsigned CUID) {
return PrologEndLoc;
}
+void DwarfDebug::findKeyInstructions(const MachineFunction *MF) {
+ // New function - reset KeyInstructions.
+ KeyInstructions.clear();
+
+ //
https://github.com/jmorse commented:
I get the impression that `GroupCandidates` and `KeyInstructions` are being
kept strictly in sync; thus couldn't one instead just load KeyInstructions from
GroupCandidates once the scan is complete? This avoids filling up the dense map
with tombstones.
Am
@@ -2333,6 +2352,170 @@ DwarfDebug::emitInitialLocDirective(const
MachineFunction &MF, unsigned CUID) {
return PrologEndLoc;
}
+void DwarfDebug::findKeyInstructions(const MachineFunction *MF) {
+ // New function - reset KeyInstructions.
+ KeyInstructions.clear();
+
+ //
@@ -2087,13 +2095,18 @@ void DwarfDebug::beginInstruction(const MachineInstr
*MI) {
// If we have an ongoing unspecified location, nothing to do here.
if (!DL)
return;
-// We have an explicit location, same as the previous location.
-// But we might be co
@@ -2333,6 +2352,170 @@ DwarfDebug::emitInitialLocDirective(const
MachineFunction &MF, unsigned CUID) {
return PrologEndLoc;
}
+void DwarfDebug::findKeyInstructions(const MachineFunction *MF) {
+ // New function - reset KeyInstructions.
+ KeyInstructions.clear();
+
+ //
@@ -2333,6 +2352,170 @@ DwarfDebug::emitInitialLocDirective(const
MachineFunction &MF, unsigned CUID) {
return PrologEndLoc;
}
+void DwarfDebug::findKeyInstructions(const MachineFunction *MF) {
+ // New function - reset KeyInstructions.
+ KeyInstructions.clear();
+
+ //
@@ -2333,6 +2352,170 @@ DwarfDebug::emitInitialLocDirective(const
MachineFunction &MF, unsigned CUID) {
return PrologEndLoc;
}
+void DwarfDebug::findKeyInstructions(const MachineFunction *MF) {
+ // New function - reset KeyInstructions.
+ KeyInstructions.clear();
+
+ //
https://github.com/jmorse edited
https://github.com/llvm/llvm-project/pull/133495
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https://github.com/jdoerfert commented:
Looks reasonable to me. I left one comment and I believe you can verify what is
best yourself.
https://github.com/llvm/llvm-project/pull/118878
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https://github.com/jdoerfert edited
https://github.com/llvm/llvm-project/pull/118878
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@@ -9406,6 +9406,14 @@ StmtResult
TreeTransform::TransformOMPInformationalDirective(
D->getBeginLoc(), D->getEndLoc());
}
+template
+StmtResult TreeTransform::TransformOMPCompoundRootDirective(
+OMPCompoundRootDirective *D) {
+ // This function should never be fou
llvmbot wrote:
@llvm/pr-subscribers-llvm-transforms
Author: Sam Tebbs (SamTebbs33)
Changes
This PR adds support for extensions of different signedness to
VPMulAccumulateReductionRecipe and allows such partial reductions to be bundled
into that class.
---
Patch is 25.75 KiB, truncated t
nikic wrote:
@shiltian I'm not entirely sure what you're asking here. As @arsenm said, the
alloca address space in the data layout is merely a hint on the address space
to use when materializing allocas "out of thin air". There are targets that use
multiple alloca address spaces, this just spe
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=infer-address-spaces %s -o -
| FileCheck %s
+
+declare void @bar(ptr)
+
+define i32 @static_alloca() {
+; CHECK-LAB
arsenm wrote:
> My reading is, it has to match the ultimate code generator. Middle end
> optimization relies on it to improve the code.
The definition of "match" leaves room for interpretation, and it would be a
better system if we allowed more dynamic configuration for some fields. However
t
redstar wrote:
@uweigand I made all the suggested changes.
https://github.com/llvm/llvm-project/pull/133799
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@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 5
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=infer-address-spaces %s -o -
| FileCheck %s
+
+declare void @bar(ptr)
+
+define i32 @static_alloca() {
+; CHECK-LAB
https://github.com/shiltian edited
https://github.com/llvm/llvm-project/pull/136798
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