mbrkusanin wrote:
> > Why is so there so much special casing in the assembler/disassembler?
>
> I'm not an original author of these change, but from what I understand it is
> a workaround to handle VOP3 instructions which have a single source but
> require the use of two bits from OPSEL. `V_CV
mbrkusanin wrote:
> > > Why is so there so much special casing in the assembler/disassembler?
> >
> >
> > I'm not an original author of these change, but from what I understand it
> > is a workaround to handle VOP3 instructions which have a single source but
> > require the use of two bits fr
@@ -626,11 +629,82 @@ class Cvt_PK_F32_F8_Pat;
-foreach Index = [0, -1] in {
- def : Cvt_PK_F32_F8_Pat;
- def : Cvt_PK_F32_F8_Pat;
+let SubtargetPredicate = isGFX9Only in {
+ foreach Index = [0, -1] in {
+def : Cvt_PK_F32_F8_Pat;
+def : Cvt_PK_F32_F8_Pat;
+ }
+}
+
+
mbrkusanin wrote:
> > Correct, some of these instructions use opsel[1] which in LLVM in stored in
> > src1_modifiers so a dummy src1 is used.
>
> Why can't we just use `SRCMODS.OP_SEL_1` with src0?
That could work. We would have to make custom encoding classes then since
OP_SEL_1 would have d
@@ -305,6 +305,11 @@ class VOP3OpSel_gfx10 op, VOPProfile p> :
VOP3e_gfx10 {
class VOP3OpSel_gfx11_gfx12 op, VOPProfile p> : VOP3OpSel_gfx10;
+class VOP3FP8OpSel_gfx11_gfx12 op, VOPProfile p> : VOP3e_gfx10
{
+ let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0);
+ let Ins
@@ -305,6 +305,11 @@ class VOP3OpSel_gfx10 op, VOPProfile p> :
VOP3e_gfx10 {
class VOP3OpSel_gfx11_gfx12 op, VOPProfile p> : VOP3OpSel_gfx10;
+class VOP3FP8OpSel_gfx11_gfx12 op, VOPProfile p> : VOP3e_gfx10
{
+ let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0);
+ let Ins
@@ -305,6 +305,11 @@ class VOP3OpSel_gfx10 op, VOPProfile p> :
VOP3e_gfx10 {
class VOP3OpSel_gfx11_gfx12 op, VOPProfile p> : VOP3OpSel_gfx10;
+class VOP3FP8OpSel_gfx11_gfx12 op, VOPProfile p> : VOP3e_gfx10
{
+ let Inst{11} = !if(p.HasSrc0, src0_modifiers{2}, 0);
+ let Ins
