mbrkusanin wrote: > > > Why is so there so much special casing in the assembler/disassembler? > > > > > > I'm not an original author of these change, but from what I understand it > > is a workaround to handle VOP3 instructions which have a single source but > > require the use of two bits from OPSEL. `V_CVT_F32_FP8` has one source but > > is using two bits from OPSEL to specify which part from 32 bit register to > > convert ([7:0], [15:8], [23: 16] or 31 : 24]). And since OPSELs are > > correlated with sources/destination (one bit from OPSEL with one > > soruce/destination) these is required without any deeper changes to > > TableGen. > > I'm open to change TableGen, but I would prefer to create new ticket and do > > it with new PR. These change may take longer than one day and we would like > > to have these PR merged before LLVM branching. > > Correct, some of these instructions use opsel[1] which in LLVM in stored in > src1_modifiers so a dummy src1 is used. And as far as I know we can not have > src1_modfiers without src1 operand.
Similarly V_CVT_SR_BF8_F32 for example uses opsel[2] and opsel[3] so we need src2_modifiers and src2. https://github.com/llvm/llvm-project/pull/78414 _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
