[Lldb-commits] [lldb] [lldb] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

https://github.com/AlexeyMerzlyakov created https://github.com/llvm/llvm-project/pull/93297 The PR adds the support of CoreDump debugging for RISC-V 64. It implements new `RegisterContextCorePOSIX_riscv64` class. Also, the contribution fixes `GetRegisterCount()` -> `GetRegisterSetCount()` mis

[Lldb-commits] [lldb] [lldb] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

https://github.com/AlexeyMerzlyakov updated https://github.com/llvm/llvm-project/pull/93297 >From d30c3b7017bd9f4b9f442ee728d7e3d7847c60cf Mon Sep 17 00:00:00 2001 From: Alexey Merzlyakov Date: Fri, 24 May 2024 11:54:16 +0300 Subject: [PATCH] Add RegisterContextPOSIXCore for RISC-V 64 Fix GetR

[Lldb-commits] [lldb] [lldb] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

https://github.com/AlexeyMerzlyakov updated https://github.com/llvm/llvm-project/pull/93297 >From d30c3b7017bd9f4b9f442ee728d7e3d7847c60cf Mon Sep 17 00:00:00 2001 From: Alexey Merzlyakov Date: Fri, 24 May 2024 11:54:16 +0300 Subject: [PATCH 1/2] Add RegisterContextPOSIXCore for RISC-V 64 Fix

[Lldb-commits] [lldb] [lldb] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

@@ -0,0 +1,84 @@ +//===-- RegisterContextPOSIXCore_riscv64.cpp --===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[Lldb-commits] [lldb] [lldb] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

@@ -0,0 +1,84 @@ +//===-- RegisterContextPOSIXCore_riscv64.cpp --===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[Lldb-commits] [lldb] [lldb] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

@@ -0,0 +1,84 @@ +//===-- RegisterContextPOSIXCore_riscv64.cpp --===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[Lldb-commits] [lldb] [lldb] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

https://github.com/AlexeyMerzlyakov edited https://github.com/llvm/llvm-project/pull/93297 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [lldb] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

@@ -0,0 +1,84 @@ +//===-- RegisterContextPOSIXCore_riscv64.cpp --===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[Lldb-commits] [lldb] [lldb] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

https://github.com/AlexeyMerzlyakov edited https://github.com/llvm/llvm-project/pull/93297 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [lldb] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

https://github.com/AlexeyMerzlyakov edited https://github.com/llvm/llvm-project/pull/93297 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [lldb] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

AlexeyMerzlyakov wrote: No, I have no rights to do this https://github.com/llvm/llvm-project/pull/93297 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [lldb][RISCV] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

https://github.com/AlexeyMerzlyakov updated https://github.com/llvm/llvm-project/pull/93297 >From d30c3b7017bd9f4b9f442ee728d7e3d7847c60cf Mon Sep 17 00:00:00 2001 From: Alexey Merzlyakov Date: Fri, 24 May 2024 11:54:16 +0300 Subject: [PATCH 1/3] Add RegisterContextPOSIXCore for RISC-V 64 Fix

[Lldb-commits] [lldb] [lldb][RISCV] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

@@ -0,0 +1,84 @@ +//===-- RegisterContextPOSIXCore_riscv64.cpp --===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apa

[Lldb-commits] [lldb] [lldb][RISCV] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

https://github.com/AlexeyMerzlyakov updated https://github.com/llvm/llvm-project/pull/93297 >From d30c3b7017bd9f4b9f442ee728d7e3d7847c60cf Mon Sep 17 00:00:00 2001 From: Alexey Merzlyakov Date: Fri, 24 May 2024 11:54:16 +0300 Subject: [PATCH 1/3] Add RegisterContextPOSIXCore for RISC-V 64 Fix

[Lldb-commits] [lldb] [lldb][RISCV] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

https://github.com/AlexeyMerzlyakov edited https://github.com/llvm/llvm-project/pull/93297 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [lldb][RISCV] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

AlexeyMerzlyakov wrote: > Corefiles can be debugged anywhere, so you should add a test case to > `lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py`. I've added two testcases (one general and one checking main RISC-V registers) to `TestLinuxCore.py`. It was used the approach d

[Lldb-commits] [lldb] [lldb][RISCV] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

https://github.com/AlexeyMerzlyakov updated https://github.com/llvm/llvm-project/pull/93297 >From d30c3b7017bd9f4b9f442ee728d7e3d7847c60cf Mon Sep 17 00:00:00 2001 From: Alexey Merzlyakov Date: Fri, 24 May 2024 11:54:16 +0300 Subject: [PATCH 1/4] Add RegisterContextPOSIXCore for RISC-V 64 Fix

[Lldb-commits] [lldb] [lldb][RISCV] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

https://github.com/AlexeyMerzlyakov updated https://github.com/llvm/llvm-project/pull/93297 >From d30c3b7017bd9f4b9f442ee728d7e3d7847c60cf Mon Sep 17 00:00:00 2001 From: Alexey Merzlyakov Date: Fri, 24 May 2024 11:54:16 +0300 Subject: [PATCH 1/5] Add RegisterContextPOSIXCore for RISC-V 64 Fix

[Lldb-commits] [lldb] [lldb][RISCV] Add RegisterContextPOSIXCore for RISC-V 64 (PR #93297)

AlexeyMerzlyakov wrote: Oops, I've checked it with flake8, but did not have an idea about the darker tool. Fixed in [latest](https://github.com/llvm/llvm-project/pull/93297/commits/041f5729920ed5f1b22745970b488d12438af1ba) commit. Thank you! https://github.com/llvm/llvm-project/pull/93297 ___

[Lldb-commits] [lldb] [lldb][RISCV] Support optionally disabled FPR (PR #104547)

https://github.com/AlexeyMerzlyakov created https://github.com/llvm/llvm-project/pull/104547 The PR adds the support optionally enabled/disabled FP-registers to LLDB `RegisterInfoPOSIX_riscv64`. This situation might take place for RISC-V builds have no FP-registers, like RV64IMAC or RV64IMACV.

[Lldb-commits] [lldb] [lldb][RISCV] Support optionally disabled FPR (PR #104547)

AlexeyMerzlyakov wrote: The change - is a result of https://github.com/llvm/llvm-project/pull/93297 discussions about FP-register class refactoring https://github.com/llvm/llvm-project/pull/104547 ___ lldb-commits mailing list lldb-commits@lists.llvm

[Lldb-commits] [lldb] [lldb][RISCV] Support optionally disabled FPR (PR #104547)

https://github.com/AlexeyMerzlyakov updated https://github.com/llvm/llvm-project/pull/104547 >From f0dcd28876e3815454be3c9b2ae19cab26dede1e Mon Sep 17 00:00:00 2001 From: Alexey Merzlyakov Date: Thu, 15 Aug 2024 14:29:49 +0300 Subject: [PATCH 1/2] Support optionally disabled FPR --- .../RISCV

[Lldb-commits] [lldb] [lldb][RISCV] Support optionally disabled FPR (PR #104547)

https://github.com/AlexeyMerzlyakov edited https://github.com/llvm/llvm-project/pull/104547 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [lldb][RISCV] Support optionally disabled FPR (PR #104547)

AlexeyMerzlyakov wrote: @DavidSpickett, thank you for the review and sorry for late reply, I've just returned from the BT w/o an access to my main PC. Yes, the way to handle the register sets is pretty similar that ARM64 is using in dynamic model (if I understand it correctly), so all further

[Lldb-commits] [lldb] [lldb][RISCV] Support optionally disabled FPR for riscv64 (PR #104547)

https://github.com/AlexeyMerzlyakov edited https://github.com/llvm/llvm-project/pull/104547 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [lldb][RISCV] Support optionally disabled FPR for riscv64 (PR #104547)

@@ -760,6 +772,61 @@ def test_riscv64_regs(self): self.expect("register read --all") +@skipIfLLVMTargetMissing("RISCV") AlexeyMerzlyakov wrote: Just to be on the same page: Should I move `test_riscv64_regs_gpr`/`test_riscv64_regs_gpr_fpr` tests

[Lldb-commits] [lldb] [lldb][RISCV] Support optionally disabled FPR for riscv64 (PR #104547)

https://github.com/AlexeyMerzlyakov edited https://github.com/llvm/llvm-project/pull/104547 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [lldb][RISCV] Support optionally disabled FPR for riscv64 (PR #104547)

https://github.com/AlexeyMerzlyakov edited https://github.com/llvm/llvm-project/pull/104547 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [lldb][RISCV] Support optionally disabled FPR for riscv64 (PR #104547)

https://github.com/AlexeyMerzlyakov edited https://github.com/llvm/llvm-project/pull/104547 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [lldb][RISCV] Support optionally disabled FPR for riscv64 (PR #104547)

https://github.com/AlexeyMerzlyakov edited https://github.com/llvm/llvm-project/pull/104547 ___ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits

[Lldb-commits] [lldb] [lldb][RISCV] Support optionally disabled FPR for riscv64 (PR #104547)

AlexeyMerzlyakov wrote: Hi, @DavidSpickett. Sure, no problem, I'll make an update PR for ReleaseNotes with optionally enabled/disabled register sets soon. https://github.com/llvm/llvm-project/pull/104547 ___ lldb-commits mailing list lldb-commits@list