https://github.com/AlexeyMerzlyakov updated
https://github.com/llvm/llvm-project/pull/93297
>From d30c3b7017bd9f4b9f442ee728d7e3d7847c60cf Mon Sep 17 00:00:00 2001
From: Alexey Merzlyakov <alexey.merzlya...@samsung.com>
Date: Fri, 24 May 2024 11:54:16 +0300
Subject: [PATCH 1/3] Add RegisterContextPOSIXCore for RISC-V 64
Fix GetRegisterSetCount() method name misprint for RegisterContextPOSIX_riscv64
---
.../Utility/RegisterContextPOSIX_riscv64.cpp | 2 +-
.../Plugins/Process/elf-core/CMakeLists.txt | 1 +
.../RegisterContextPOSIXCore_riscv64.cpp | 84 +++++++++++++++++++
.../RegisterContextPOSIXCore_riscv64.h | 60 +++++++++++++
.../Process/elf-core/ThreadElfCore.cpp | 8 +-
5 files changed, 153 insertions(+), 2 deletions(-)
create mode 100644
lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
create mode 100644
lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
diff --git
a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
index 1834a94dc0260..035ce00e11626 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
@@ -58,7 +58,7 @@ RegisterContextPOSIX_riscv64::GetRegisterInfoAtIndex(size_t
reg) {
}
size_t RegisterContextPOSIX_riscv64::GetRegisterSetCount() {
- return m_register_info_up->GetRegisterCount();
+ return m_register_info_up->GetRegisterSetCount();
}
const lldb_private::RegisterSet *
diff --git a/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
b/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
index 8ddc671e3ae66..72925c835b5c8 100644
--- a/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
@@ -9,6 +9,7 @@ add_lldb_library(lldbPluginProcessElfCore PLUGIN
RegisterContextPOSIXCore_ppc64le.cpp
RegisterContextPOSIXCore_s390x.cpp
RegisterContextPOSIXCore_x86_64.cpp
+ RegisterContextPOSIXCore_riscv64.cpp
RegisterUtilities.cpp
LINK_LIBS
diff --git
a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
new file mode 100644
index 0000000000000..2202be4d38082
--- /dev/null
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
@@ -0,0 +1,84 @@
+//===-- RegisterContextPOSIXCore_riscv64.cpp
------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "RegisterContextPOSIXCore_riscv64.h"
+
+#include "lldb/Utility/DataBufferHeap.h"
+
+using namespace lldb_private;
+
+std::unique_ptr<RegisterContextCorePOSIX_riscv64>
+RegisterContextCorePOSIX_riscv64::Create(
+ lldb_private::Thread &thread, const lldb_private::ArchSpec &arch,
+ const lldb_private::DataExtractor &gpregset,
+ llvm::ArrayRef<lldb_private::CoreNote> notes) {
+ Flags flags = 0;
+
+ auto register_info_up =
+ std::make_unique<RegisterInfoPOSIX_riscv64>(arch, flags);
+ return std::unique_ptr<RegisterContextCorePOSIX_riscv64>(
+ new RegisterContextCorePOSIX_riscv64(thread, std::move(register_info_up),
+ gpregset, notes));
+}
+
+RegisterContextCorePOSIX_riscv64::RegisterContextCorePOSIX_riscv64(
+ Thread &thread, std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info,
+ const DataExtractor &gpregset, llvm::ArrayRef<CoreNote> notes)
+ : RegisterContextPOSIX_riscv64(thread, std::move(register_info)) {
+
+ m_gpr_buffer = std::make_shared<DataBufferHeap>(gpregset.GetDataStart(),
+ gpregset.GetByteSize());
+ m_gpr.SetData(m_gpr_buffer);
+ m_gpr.SetByteOrder(gpregset.GetByteOrder());
+
+ ArchSpec arch = m_register_info_up->GetTargetArchitecture();
+ DataExtractor fpregset = getRegset(notes, arch.GetTriple(), FPR_Desc);
+ m_fpr_buffer = std::make_shared<DataBufferHeap>(fpregset.GetDataStart(),
+ fpregset.GetByteSize());
+ m_fpr.SetData(m_fpr_buffer);
+ m_fpr.SetByteOrder(fpregset.GetByteOrder());
+}
+
+RegisterContextCorePOSIX_riscv64::~RegisterContextCorePOSIX_riscv64() =
default;
+
+bool RegisterContextCorePOSIX_riscv64::ReadGPR() { return true; }
+
+bool RegisterContextCorePOSIX_riscv64::ReadFPR() { return true; }
+
+bool RegisterContextCorePOSIX_riscv64::WriteGPR() {
+ assert(0);
+ return false;
+}
+
+bool RegisterContextCorePOSIX_riscv64::WriteFPR() {
+ assert(0);
+ return false;
+}
+
+bool RegisterContextCorePOSIX_riscv64::ReadRegister(
+ const RegisterInfo *reg_info, RegisterValue &value) {
+ const uint8_t *src = nullptr;
+ lldb::offset_t offset = reg_info->byte_offset;
+
+ if (IsGPR(reg_info->kinds[lldb::eRegisterKindLLDB])) {
+ src = m_gpr.GetDataStart();
+ } else { // IsFPR
+ src = m_fpr.GetDataStart();
+ offset -= GetGPRSize();
+ }
+
+ Status error;
+ value.SetFromMemoryData(*reg_info, src + offset, reg_info->byte_size,
+ lldb::eByteOrderLittle, error);
+ return error.Success();
+}
+
+bool RegisterContextCorePOSIX_riscv64::WriteRegister(
+ const RegisterInfo *reg_info, const RegisterValue &value) {
+ return false;
+}
diff --git
a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
new file mode 100644
index 0000000000000..3cf9531df2c1d
--- /dev/null
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
@@ -0,0 +1,60 @@
+//===-- RegisterContextPOSIXCore_riscv64.h ----------------------*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV64_H
+
+#include "Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
+
+#include "Plugins/Process/elf-core/RegisterUtilities.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/DataExtractor.h"
+#include "lldb/Utility/RegisterValue.h"
+
+#include <memory>
+
+class RegisterContextCorePOSIX_riscv64 : public RegisterContextPOSIX_riscv64 {
+public:
+ static std::unique_ptr<RegisterContextCorePOSIX_riscv64>
+ Create(lldb_private::Thread &thread, const lldb_private::ArchSpec &arch,
+ const lldb_private::DataExtractor &gpregset,
+ llvm::ArrayRef<lldb_private::CoreNote> notes);
+
+ ~RegisterContextCorePOSIX_riscv64() override;
+
+ bool ReadRegister(const lldb_private::RegisterInfo *reg_info,
+ lldb_private::RegisterValue &value) override;
+
+ bool WriteRegister(const lldb_private::RegisterInfo *reg_info,
+ const lldb_private::RegisterValue &value) override;
+
+protected:
+ RegisterContextCorePOSIX_riscv64(
+ lldb_private::Thread &thread,
+ std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info,
+ const lldb_private::DataExtractor &gpregset,
+ llvm::ArrayRef<lldb_private::CoreNote> notes);
+
+ bool ReadGPR() override;
+
+ bool ReadFPR() override;
+
+ bool WriteGPR() override;
+
+ bool WriteFPR() override;
+
+private:
+ lldb::DataBufferSP m_gpr_buffer;
+ lldb::DataBufferSP m_fpr_buffer;
+
+ lldb_private::DataExtractor m_gpr;
+ lldb_private::DataExtractor m_fpr;
+};
+
+#endif //
LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV64_H
diff --git a/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
b/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
index 3ce2a4a5c3fa4..2a83163884e16 100644
--- a/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
+++ b/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
@@ -35,6 +35,7 @@
#include "RegisterContextPOSIXCore_mips64.h"
#include "RegisterContextPOSIXCore_powerpc.h"
#include "RegisterContextPOSIXCore_ppc64le.h"
+#include "RegisterContextPOSIXCore_riscv64.h"
#include "RegisterContextPOSIXCore_s390x.h"
#include "RegisterContextPOSIXCore_x86_64.h"
#include "ThreadElfCore.h"
@@ -168,7 +169,8 @@ ThreadElfCore::CreateRegisterContextForFrame(StackFrame
*frame) {
}
if (!reg_interface && arch.GetMachine() != llvm::Triple::aarch64 &&
- arch.GetMachine() != llvm::Triple::arm) {
+ arch.GetMachine() != llvm::Triple::arm &&
+ arch.GetMachine() != llvm::Triple::riscv64) {
LLDB_LOGF(log, "elf-core::%s:: Architecture(%d) or OS(%d) not supported",
__FUNCTION__, arch.GetMachine(), arch.GetTriple().getOS());
assert(false && "Architecture or OS not supported");
@@ -184,6 +186,10 @@ ThreadElfCore::CreateRegisterContextForFrame(StackFrame
*frame) {
*this, std::make_unique<RegisterInfoPOSIX_arm>(arch),
m_gpregset_data,
m_notes);
break;
+ case llvm::Triple::riscv64:
+ m_thread_reg_ctx_sp = RegisterContextCorePOSIX_riscv64::Create(
+ *this, arch, m_gpregset_data, m_notes);
+ break;
case llvm::Triple::mipsel:
case llvm::Triple::mips:
m_thread_reg_ctx_sp = std::make_shared<RegisterContextCorePOSIX_mips64>(
>From 7239f6293ee088a7cde8fa2e6feee00aedf7ac9a Mon Sep 17 00:00:00 2001
From: Alexey Merzlyakov <alexey.merzlya...@samsung.com>
Date: Wed, 29 May 2024 12:29:38 +0300
Subject: [PATCH 2/3] Meet review items
---
.../RegisterContextPOSIXCore_riscv64.cpp | 22 +++++++++----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git
a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
index 2202be4d38082..6f188a9fad5ed 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
@@ -13,17 +13,15 @@
using namespace lldb_private;
std::unique_ptr<RegisterContextCorePOSIX_riscv64>
-RegisterContextCorePOSIX_riscv64::Create(
- lldb_private::Thread &thread, const lldb_private::ArchSpec &arch,
- const lldb_private::DataExtractor &gpregset,
- llvm::ArrayRef<lldb_private::CoreNote> notes) {
+RegisterContextCorePOSIX_riscv64::Create(Thread &thread, const ArchSpec &arch,
+ const DataExtractor &gpregset,
+ llvm::ArrayRef<CoreNote> notes) {
Flags flags = 0;
- auto register_info_up =
- std::make_unique<RegisterInfoPOSIX_riscv64>(arch, flags);
return std::unique_ptr<RegisterContextCorePOSIX_riscv64>(
- new RegisterContextCorePOSIX_riscv64(thread, std::move(register_info_up),
- gpregset, notes));
+ new RegisterContextCorePOSIX_riscv64(
+ thread, std::make_unique<RegisterInfoPOSIX_riscv64>(arch, flags),
+ gpregset, notes));
}
RegisterContextCorePOSIX_riscv64::RegisterContextCorePOSIX_riscv64(
@@ -51,12 +49,12 @@ bool RegisterContextCorePOSIX_riscv64::ReadGPR() { return
true; }
bool RegisterContextCorePOSIX_riscv64::ReadFPR() { return true; }
bool RegisterContextCorePOSIX_riscv64::WriteGPR() {
- assert(0);
+ assert(false && "Writing registers is not allowed for core dumps");
return false;
}
bool RegisterContextCorePOSIX_riscv64::WriteFPR() {
- assert(0);
+ assert(false && "Writing registers is not allowed for core dumps");
return false;
}
@@ -67,9 +65,11 @@ bool RegisterContextCorePOSIX_riscv64::ReadRegister(
if (IsGPR(reg_info->kinds[lldb::eRegisterKindLLDB])) {
src = m_gpr.GetDataStart();
- } else { // IsFPR
+ } else if (IsFPR(reg_info->kinds[lldb::eRegisterKindLLDB])) {
src = m_fpr.GetDataStart();
offset -= GetGPRSize();
+ } else {
+ return false;
}
Status error;
>From 73386d9dffcd902419e33af4ca375fee4998f856 Mon Sep 17 00:00:00 2001
From: Alexey Merzlyakov <alexey.merzlya...@samsung.com>
Date: Tue, 4 Jun 2024 14:51:32 +0300
Subject: [PATCH 3/3] Optimize flags initialization
Add RISC-V 64 testcases to TestLinuxCore.py
---
.../RegisterContextPOSIXCore_riscv64.cpp | 4 +-
.../postmortem/elf-core/TestLinuxCore.py | 57 ++++++++++++++++++
.../postmortem/elf-core/linux-riscv64.core | Bin 0 -> 20480 bytes
.../postmortem/elf-core/linux-riscv64.out | Bin 0 -> 3328 bytes
4 files changed, 58 insertions(+), 3 deletions(-)
create mode 100644
lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.core
create mode 100755
lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.out
diff --git
a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
index 6f188a9fad5ed..5ba18cdb9889a 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
@@ -16,11 +16,9 @@ std::unique_ptr<RegisterContextCorePOSIX_riscv64>
RegisterContextCorePOSIX_riscv64::Create(Thread &thread, const ArchSpec &arch,
const DataExtractor &gpregset,
llvm::ArrayRef<CoreNote> notes) {
- Flags flags = 0;
-
return std::unique_ptr<RegisterContextCorePOSIX_riscv64>(
new RegisterContextCorePOSIX_riscv64(
- thread, std::make_unique<RegisterInfoPOSIX_riscv64>(arch, flags),
+ thread, std::make_unique<RegisterInfoPOSIX_riscv64>(arch, Flags()),
gpregset, notes));
}
diff --git a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
index 8ec0cbdd0fdd1..4a5cc0819572b 100644
--- a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
+++ b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
@@ -21,12 +21,14 @@ class LinuxCoreTestCase(TestBase):
_x86_64_pid = 32259
_s390x_pid = 1045
_ppc64le_pid = 28147
+ _riscv64_pid = 89328
_aarch64_regions = 4
_i386_regions = 4
_x86_64_regions = 5
_s390x_regions = 2
_ppc64le_regions = 2
+ _riscv64_regions = 4
@skipIfLLVMTargetMissing("AArch64")
def test_aarch64(self):
@@ -58,6 +60,11 @@ def test_s390x(self):
"""Test that lldb can read the process information from an s390x linux
core file."""
self.do_test("linux-s390x", self._s390x_pid, self._s390x_regions,
"a.out")
+ @skipIfLLVMTargetMissing("RISCV")
+ def test_riscv64(self):
+ """Test that lldb can read the process information from an riscv64
linux core file."""
+ self.do_test("linux-riscv64", self._riscv64_pid,
self._riscv64_regions, "a.out")
+
@skipIfLLVMTargetMissing("X86")
def test_same_pid_running(self):
"""Test that we read the information from the core correctly even if
we have a running
@@ -629,6 +636,56 @@ def test_arm_core(self):
self.expect("register read --all")
+ @skipIfLLVMTargetMissing("RISCV")
+ def test_riscv64_regs(self):
+ # check basic registers using 64 bit RISC-V core file
+ target = self.dbg.CreateTarget(None)
+ self.assertTrue(target, VALID_TARGET)
+ process = target.LoadCore("linux-riscv64.core")
+
+ values = {}
+ values["pc"] = "0x000000000001015e"
+ values["ra"] = "0x000000000001018c"
+ values["sp"] = "0x0000003fffd132a0"
+ values["gp"] = "0x0000002ae919af50"
+ values["tp"] = "0x0000003fdceae3e0"
+ values["t0"] = "0x0"
+ values["t1"] = "0x0000002ae9187b1c"
+ values["t2"] = "0x0000000000000021"
+ values["fp"] = "0x0000003fffd132d0"
+ values["s1"] = "0x0000002ae919cd98"
+ values["a0"] = "0x0"
+ values["a1"] = "0x0000000000010144"
+ values["a2"] = "0x0000002ae919cdb0"
+ values["a3"] = "0x000000000000002f"
+ values["a4"] = "0x000000000000002f"
+ values["a5"] = "0x0"
+ values["a6"] = "0x7efefefefefefeff"
+ values["a7"] = "0x00000000000000dd"
+ values["s2"] = "0x0000002ae9196860"
+ values["s3"] = "0x0000002ae919cdb0"
+ values["s4"] = "0x0000003fffc63be8"
+ values["s5"] = "0x0000002ae919cb78"
+ values["s6"] = "0x0000002ae9196860"
+ values["s7"] = "0x0000002ae9196860"
+ values["s8"] = "0x0"
+ values["s9"] = "0x000000000000000f"
+ values["s10"] = "0x0000002ae919a8d0"
+ values["s11"] = "0x0000000000000008"
+ values["t3"] = "0x0000003fdce07df4"
+ values["t4"] = "0x0"
+ values["t5"] = "0x0000000000000020"
+ values["t6"] = "0x0000002ae919f1b0"
+ values["zero"] = "0x0"
+
+ for regname, value in values.items():
+ self.expect(
+ "register read {}".format(regname),
+ substrs=["{} = {}".format(regname, value)],
+ )
+
+ self.expect("register read --all")
+
def test_get_core_file_api(self):
"""
Test SBProcess::GetCoreFile() API can successfully get the core file.
diff --git
a/lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.core
b/lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.core
new file mode 100644
index
0000000000000000000000000000000000000000..0b159fcab931dca85bd5d09c282c2d6c217e2b83
GIT binary patch
literal 20480
zcmeHP4{#J$8Gm<yBu!fgL>dqrucZuaHFujogmCFWj^qf@Bgy2F7OK-@bGNxWxPRT<
zOG4UGAU1&g15O-aDq1_80#h7iL<c)sDN_rMwYHtswvMP(MCzYbsFeysiSK*+eYbm8
zQHH8BcJ_ta@6Y?*`@Zk@-tK-Ia(ho8xXkHrFlv+7UzsT})<PW?+QORHWRxc%U1=R;
zu{~dA5iBg2i#aMud65aIAL;wXt)6pi2~7dC$ev^vCt`Jh5pUT`A6E+Y5*&DQy*N?e
z&n2{6j}-kwZo}Lu_-*a#2|(|aaKL8eNq6eA4)#iogApbD`{=ns&7V&e%9Z1Wd^@h|
z{Ybx7XT;w9%~^lAiJQEB{Er3L&AD@?&|izwy@2*RpEK;qOB>F&AN3yWAWC)<7erhC
zOH{0m8}rb(H=2(KEQg;p^wdw3=9!Aj3wsT_a+Ke>`}KnOU8vuG+OPxcp}|^g;hz%z
zp|xN=T!2>EBFG!O6F!7JQQ4iz>B7P|xIIGSvZy`~3$bnBpN{s95XDA&gW~@{4lZM`
zh>1IgeNQpbo?v*s-B2{|jYTr-FKhdRRp9(5i{zRjnNH)HX)e(t&OzX?W17%17DWnc
z3#|pOUgBKma+A>FwTAPgFTO0%o<ehW1u|d4y-sTadj#551`&G(*sF`=DMfNM%0y-%
z^V0>!Ir(vvPc13BzMvk~q>X<9!H#9LCi(qAU}5g8GT$Rcd*Ydt;)yE#2|4Xik^?o7
zjH(#>SezT>+}z16X<jkNK8XE)JpjWuL$IT>Z>5cijew1Sjew1Sjew1SjlhQhfqROc
z|4Zok9}D6Z%yA1Az))Gj^Zz7%tYlL~#R;|P#aefT(L<E#cPOi%7T=EbbTO5%ge6M#
zIgEi%H;yZ&H}gJdM8OtX_X#};{8OkXrq>HA#)zVscxHrW0dNP;4Eg5}w5Qx5J{kkL
zfjv-21I9QiXH9EyFp2UO&mTXYy+5=~iqHAt{S&*NNL@SY(bn|MGmbtqe}BKihg`Ik
zunP7DIYTRW-kQ#T!!QLOT#lfAG3sAN{cWiK9H-OR=?N6`1mcBx7y?eX&p>?zDkkCj
ztVaFKxXwt#<2B4973o<xJQ&q7VO0-niI}SBIW<kXNHP;y8;&Wuo=7RAL@_fEmDiCj
zZ>TC7>9}1an<Hr;nbYFoL`06n6_!k-bHg>@*3JLb8nt}5!Ckw62hW?c;K$H8_{zc0
zBZuC)`XgL5hkxkz0Fb(q_vP+6Spj{}08ePJETDt+Z}045&z@N_`{D0K9|^uJ?Y(oU
zb~<wSD;Hot(DDT#HZI>$VeBM&ZX{o1=R&;yc3~pJ%^Cf^jrLy_HWqKRKX;-%t;aT_
zJO4YVnJ8cCb1>PTpD_H-#Pjbxl+isqg|Ywuef&3xV|GdN_1po3)4~sM-e)-|QBLpT
z6tIOxkH{q>Jt5|}%i)-PwG(uZ*Lfa1?Q@GAnTfGrH;K<jc!C}L4&yvuAkuNsZZ-n{
zR|t%k?=ROx#Qtg5{f?DC*&g}ro{Gus_r{v5_ptHJ3%8uzwsHOrepwkG+kN-XpRbx3
zV2wL>Ev<UDnk^plpPb5E&SOg-dsdrY`Bcf0EzZ$HV{F%&l1IlJqu)5<C|O+Y1dGwV
zrR?}M*SuF>_O9Pqb#_}-sKj|-bIf`0m4}+g$Id)_ZpVRFUv)$-oM8(al^;6Vt4d2(
ze{09&`N!WnbHQ2d825g4?*3;SyG~pebp-s5O&i9`E6X5iF3$t`z|k`2cMgsZm6dM%
zlmEWdOFOO+@owCDsH$upn_kwqgGYR(nqBc0L{k~r{+r6!_7lKwUwVA(=(*<(!VISm
z85kJZ9!ak{OnI(4Zshsm(~#%r55}A&BG1viV~!HY^FXP{vqa=s%JV$w-!${=w(-}>
zd7jlJl;;_q=h1(a=Xh1whQ;4|^`vvIq_9oZ8^`CIa0Ir#d0mvUeDdIU`SuFP-7)XY
zgFE=;dwlc!Xvv<kDLW63?rEQL?C^`21z*X(>~UIFax1Lly~nFKN;955SncB@%eFu8
z%-sEx*)HzI@BuT9p4^-|!Tq=jFm?pa9^&50Hwf>WHUKYGLL|Ub{pN=PLrrLrLFVY@
z>|}MYu^~~HmBJ}F$Z!~dLlh1XI1EbJh2fDwIh8S(q^2n`V2Aa%B1gf7l{+e~Y;SG#
zx^7sRlhb-asaYgRF5||&z+Ef38(gtuqCet_MIx@=OePtL%Zaq>mO6KnTXHR}sgvsJ
zYo*$z8(m=QmKbwuaZOisxu3aX>6|+*YjNg|u1jm{QU=vkqi0Z2wL~UeAcUjLozCcr
zu#{7Y2y-j(@PI0(lyE%C2a?3xx-zVDGg+6JTj1iBbzM#L=X74XxFeZVN=ehrp5t}7
z4gQY=Y5}?rQ@ud62`9$ecK&`x^#zpoXZXFF##4PkwB;h>QO%$}ggIzD)gMG(LqqTf
zHgvy*`zo}L@ejmC<Efq@O7#oaLc{XL5cqK(|4dlo&(|NA@N~4K{K*f|I^GYp49QgA
z5GDMI<Hu>4pEFQP(fEr!mykW-PI5bEpmwA9=zJnd&p|Yf@S}PK&NaY<{9o+(hMR~+
z^N@TyXRPDt`GRPa43Uz5Qpa&T<RBUuAYDd*VRy0rG}nWF%6~Z)RYYkz9G>4lq=!?8
zkIhm)QF`wD3@MO;FKZj)0_gaap`h)<I93#B4O>vrJl5E)rhmur|8D<U$NVq(+xDHi
z5@LVwmUnz#=WE2zA<<s>{=VJte^%?Jga;s=FEHmz6GuPFzWlcFgu>;4$JW!+3RqlP
zqxp7EY!gpkG~Z7?^&UK8{m15~cquAcr;Fvg@A1b)zGQ#7bQJM%oW8%V;}=Dn{&FX^
z$Jq$j2-pbN2-pbN2-pbN2-pbN2-pbN2-pbN2-pbN2-pbN2-pbN2-pbN2-pbN2-pbN
z2-pbN2-pbN2-paGcoFE&r&e!#Z<^jskk=P711_}tHh!<Wu$zUm_)ddUyN!1t(BF;x
z3csgK_P<B@ZKN|A4gWVHU5s=Y(mtdyq<12H5b18D$B<sJ(3o!~(l(@hNRvp1kbWNN
zkC6Tv=>?=yn~eExKzbE^&wLJ23F)ViCXkLIeFEtVNKYUoJgz0iem{Uf;(z^q00aKF
zM|zGPpT7S2MGqXT`q|d{`|xcQtS=Pk@fj}wV4=|RaBHw5(An#&l^Xfq&MtD-*746G
zS3~`x1(K_-js;u8y&Wq8J|!LQ3%UDxm(?_}m2K_eP#_fQ=;{pjuIdi>bbTEQEf3xj
z^wqKzUA=AL(DJTZJAGL>#g=#R!Pd79u&!WR_pNP(ItZk<ca@L7nPAY9)isX<j#qSb
z273KHs|uXAE$s{Cy#w!WYwO{`_;TsQus18~ai2%cr9C-KQ9ZSiBzgLC8jI_CRtsm<
z%<wuN@LrEc2yQhUb!&1;%cWy(HRo-Tnz-w(_D(+!8&LxLOC1{axjiX)ts>s5!2hne
z0ISxZAL8VJvED$>3g57<sHp;rjy7L??IPCg?_KWW8K@rqH7Ggh=})A+LKIA1GCE`Y
zFO4;$Td;r}VN$$mJ$;?9n&GyNo+6Z3(BIi!05q(8AQ<Rg&R3zZBNT4!3U>8`e5&S?
zywQYDs%@@s@FvrOY4oPzK1uRs6TSwixxU`3WrTi#H%d%@)aYuKYP}H)pHYRr7W64T
zt>o2mzWRmD4Ygh^=Bt;Q8|u9g8T9&)5bL}d&NMVP)Oj^sST=Z-Vd1XMdy`w2Rl(N+
z9~;T@vKq1QYx2A<n>NWfcf|98vB{AJ3(vF5>r<wYo-_yR!xnzTNLvK4(A1A4viXTj
zZPa8f0Vh>cZE=&dOl|Qv!m*$bb*s=nQkU=OH)qrfdDBKWZTPv6AF5_kd47!r;voyK
zSa{9Cs}^3iq#{R@{G1~h6R}7(VG0)XEPzC0Gqj<E8Jad^@=*(~XwkeYc`z{`gav$=
z*JNWBUNMD~wTBCqu9#(ff67=<m@C_FI2U}(!XtK|*JH-+0e;wGKWw$J%&#W~%wV%=
zGd^vwfHzhRW=&a)vJvCN5c<quKGT#X>y$OMRGr0Wt;r85mRPx9CY`Y)n#vmIjBwXr
zj^=t(7|a+;2S#@on-<t~&NLZHnY^r-`Ku<TYHHA&W*}*t+b|Db-F%t@Nh@#88B69(
zq9!{WF+B|r8T$ohTxW?aV#!uXnf95OIeR8%f-cKEGJZvDgvfGvb|7idryAh$X4s?>
z+^@;Q^$<JOT8y&wrao&r$i(=TKzr3RACh@&sLsIlBR-qs*K!oJEDsv_VJ*uuGlccP
zERwu8%_YX&FR#t>nWTsp4BQztA^Zy=E315MjiGK;;n!Q_wIRNDkk{elK|Y#Y8>@*X
z;4)^_SRLdd1BDi#NGn765g=O!@QaqUn~Mc8a#@oH`87y5<kd_d81%u7*V7MQ2jVwF
zQ4&~hs8FE<{Gq;{zzV3Kin==5xUyqeN2|Y=*GUDv#pO@_MNCFP*45b=XcdG0X;EfX
sHr8W}*4eir(9_Xc;D*Q7?eFH*o;9*STSsqKk8d!+zuJWFeWG&x9}1+^6951J
literal 0
HcmV?d00001
diff --git
a/lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.out
b/lldb/test/API/functionalities/postmortem/elf-core/linux-riscv64.out
new file mode 100755
index
0000000000000000000000000000000000000000..ae28aa9ba9aad9700b193281fa8045587c344187
GIT binary patch
literal 3328
zcmbtW-ESL35TCuv*-o4|P6KM93dK#+4-mQ7Zs-?nN!_GrB@{seQp-oLXZswx_<Zj9
zQZ-RgOKGJ%Af%`g6;OC+K?t6B0P%z<PayaskU$kkAT@}*pi;uj-fnWa#DLV5ZfEv4
zznR^e-PyZ~V^1GZ7z5c9_ycJ4mcT}YVWibpG!!GS2U@W2gaoJn^%lfzMG!+`GBlPm
zk)&8FEocEaD&k2ANuNn`(UTJNlvt;f10tZ5#HIG^9j_Si)&JFt>G)g^p$EPvj88ld
zjrV?9y7=O)UEfc9_r=Kz-&9|I^~+N;XZshSXUqN%{<;=TMQ%kG|9*Y<mHXY%1!c>n
zpD~;L-k5p$(#+Y&V*i5A+p^~~<enDXmiy`xSMFcF&fsQU;at`g`K|vKNM4IBXcX@{
zrs~?&JAbmVy9;04WANkYTv5ZAAkzZs>~UZh7~9mLKnmB|gHL&BX=xiu$R*ObIVIN~
zgO|Q-SJJrz0Oe;tK4*~gxZsSwrp&bv>(tk|Ag_q_8uE7dywo!91<p%Ryz#?__oa4>
zTKS4uOJ#QISv@^C>{{n$oJQtR0l=Z-7{RSH3g>_wMYScVx#xBbSF-htVQ1@U!z8Vg
zt!IrQbp^s^D}{#ZD<!K|u#k<QZBJJ-^)%4h{i712)xoGZ53_u<w)+(!4Hzf$v+)RV
zqWG-msTpWs9T8a#JOc#XI6?gp=p?DkI}l;95~|UX;{c0xoDs|5spSqI5|OGQx{<5%
zClvCH4t!3A`DZX#s|==+5+g$^aY6kAySBXP0%IL=oqT5zXE%6QCc|PN?oX=%HVkTP
z-)8n?eDCJAW8F#*&ZU8x@S(VmsGShs96Q#H8`8zLCc5Kl-=@AUwjr9_h{@8~Q@!XA
z#}M)Dy#$Z+T<B%UjtoFNelV`$_D6Mw^Q^;(J<PUqa;pY3L)%*7Y%jjWJNRf2gU9HN
z7`vC~AVEcr4=R0(_DErUN@w7v(HOKUG9leso61_-fN61*F_a8tJ1|w{BeEtD)dE&z
zqm_KfN<Kkr0w^9%kCmS~oY^hTaca;u^OXbD`mW(3>Xn8$*r;2D1KD(DZzh}BNp`nT
zKEThmZI+4!{}5yEpWxKs6yzPp=AGq&(eO;ygF+d1*fuLQy#PaH$F_!wyq<=vYH6_G
zxE5yM-<pcKN{NFP<f&L8GD)j(6>hJ~m$zn+O?RNS8W1BDB294Gv$ajdeO|ArAU-l7
zqYAhQ>ogVOYfw5dE%5tN*g!KXfjr3SY3IbX`I!*>a3RwTmZbPSG}B6>J2FXMiR5bh
zD&iY(-tZ0LHQ`@sg1^xOf42#Kvk5NG7hNU;=O6U;rQ6Ohrm9ZftQvKvQu8c#0FlYj
zL(d&Da%1DiCJY0|xyeamY+{t_`9?#Wcf(jsvx=r?f??G#nR;W!_RKs=&-G<lYBk5R
z^r_mko}aE%i-VOS=$>`n1KlbcCD*hq&<l=jTQ!9E$3{0j&#mOAJ*xpamell=VY+5*
zYGqidm7HZ$K9AomIjUA_7|(aY1xS@(d<z$|{9tVpy7QY&gpu_t|8E9D;lq`wqn%Ei
ztUy`kqv9Bbzk`9xlSdvF{t}n>!ENC`$5|^~xN;8)|MUulYx2KsYY3OsA>}yQ=^rvg
zTmGM<FJ`bwKZ%`0C5(~nws@iNy29LY6aNL_f0u#<TG*fJIE)ef2l`>e_OUOP`!M%1
zTEZBS=fp<8zwGHNVeXp<6Bd5YZQ`narHQ|c^L7*edEw80j{-5IUr@@k6QIGT!hb{<
oJJ6WKN1h-25#fz)e32@F_+mkPIzC#3uFX|f6aVXCqW{YOKOsPGG5`Po
literal 0
HcmV?d00001
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