https://github.com/rampitec approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/79218
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rampitec wrote:
> > > lgtm, but can still fix the -O0 thing
> >
> >
> > But where do I get TM in the getAnalysisUsage?
>
> MF.getTarget() (or maybe a pass parameter is necessary?)
There is no MF there of course.
https://github.com/llvm/llvm-project/pull/74537
https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/78492
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/78492
>From 01af6c9d8e80b810bbdec35dee38b1cf5d73cfe0 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Fri, 12 Jan 2024 15:07:53 -0800
Subject: [PATCH 1/3] [AMDGPU] Sign extend simm16 in setreg intrinsic
We
rampitec wrote:
> > lgtm, but can still fix the -O0 thing
>
> But where do I get TM in the getAnalysisUsage?
Found addUsedIfAvailable() which does the trick.
https://github.com/llvm/llvm-project/pull/74537
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 01/13] [AMDGPU] Use alias info to relax waitcounts for LDS
rampitec wrote:
> lgtm, but can still fix the -O0 thing
But where do I get TM in the getAnalysisUsage?
https://github.com/llvm/llvm-project/pull/74537
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@@ -707,7 +723,40 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
(TII->isDS(Inst) || TII->mayWriteLDSThroughDMA(Inst))) {
// MUBUF and FLAT LDS DMA operations need a wait on vmcnt before LDS
// written can be accessed. A load from LDS to VMEM
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 01/12] [AMDGPU] Use alias info to relax waitcounts for LDS
@@ -1183,9 +1228,21 @@ bool
SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI,
// No need to wait before load from VMEM to LDS.
if (TII->mayWriteLDSThroughDMA(MI))
continue;
-unsigned RegNo = SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS;
+
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 01/11] [AMDGPU] Use alias info to relax waitcounts for LDS
@@ -703,8 +713,37 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
setRegScore(RegNo, T, CurrScore);
}
}
-if (Inst.mayStore() && (TII->isDS(Inst) || mayWriteLDSThroughDMA(Inst))) {
- setRegScore(SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS, T, Curr
@@ -1183,9 +1228,21 @@ bool
SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI,
// No need to wait before load from VMEM to LDS.
if (TII->mayWriteLDSThroughDMA(MI))
continue;
-unsigned RegNo = SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS;
+
@@ -130,6 +130,8 @@
; GCN-O0-NEXT:MachineDominator Tree Construction
; GCN-O0-NEXT:Machine Natural Loop Construction
; GCN-O0-NEXT:MachinePostDominator Tree Construction
+; GCN-O0-NEXT:Basic Alias Analysis (stateless AA impl)
+; GCN-O0-NEXT:
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 01/10] [AMDGPU] Use alias info to relax waitcounts for LDS
rampitec wrote:
Ping
https://github.com/llvm/llvm-project/pull/74537
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@@ -703,8 +713,37 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
setRegScore(RegNo, T, CurrScore);
}
}
-if (Inst.mayStore() && (TII->isDS(Inst) || mayWriteLDSThroughDMA(Inst))) {
- setRegScore(SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS, T, Curr
@@ -703,8 +713,37 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
setRegScore(RegNo, T, CurrScore);
}
}
-if (Inst.mayStore() && (TII->isDS(Inst) || mayWriteLDSThroughDMA(Inst))) {
- setRegScore(SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS, T, Curr
@@ -703,8 +713,37 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
setRegScore(RegNo, T, CurrScore);
}
}
-if (Inst.mayStore() && (TII->isDS(Inst) || mayWriteLDSThroughDMA(Inst))) {
- setRegScore(SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS, T, Curr
rampitec wrote:
Ping
https://github.com/llvm/llvm-project/pull/75974
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rampitec wrote:
Ping
https://github.com/llvm/llvm-project/pull/74537
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rampitec wrote:
This is the place I am creating it: https://reviews.llvm.org/D108315
https://github.com/llvm/llvm-project/pull/75974
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rampitec wrote:
One thing to note: this alias.scope I am creating myself in the module LDS
lowering, so I do exactly know what to expect. And then since there is this
module LDS lowering even if any alias scope would be created before (which
never happens, much less for an intrinsic call) it i
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/75974
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 01/12] [AMDGPU] Use alias info to relax waitcounts for LDS
rampitec wrote:
Actually since I am only using alias scope I can avoid all alias analysis
altogether and only compare alias scope. This does not need an analysis pass,
calls to mayAlias, and in general simpler code. You can see an alternative PR
if you like it more: https://github.com/llvm/llv
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/75974
LDA DMA loads increase VMCNT and a load from the LDS stored must
wait on this counter to only read memory after it is written.
Wait count insertion pass does not track memory dependencies, it
tracks register depe
rampitec wrote:
> > This is still correct, pointer argument cannot alias module global. A
> > pointer argument to a kernel is an LDS external requested by the host side,
> > and host cannot see module LDS.
>
> I.e. that is really the point of the patch: if we are able to definitively
> identi
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 01/10] [AMDGPU] Use alias info to relax waitcounts for LDS
rampitec wrote:
> This is still correct, pointer argument cannot alias module global. A pointer
> argument to a kernel is an LDS external requested by the host side, and host
> cannot see module LDS.
I.e. that is really the point of the patch: if we are able to definitively
identify an LDS ob
rampitec wrote:
> Test case:
>
> ```
> @lds.0 = internal addrspace(3) global [64 x float] poison, align 16
> @lds.1 = internal addrspace(3) global [64 x float] poison, align 16
>
> declare void @llvm.amdgcn.raw.buffer.load.lds(<4 x i32> %rsrc, ptr
> addrspace(3) nocapture, i32 %size, i32 %voff
rampitec wrote:
> How does this work in a case like this?
>
> ```
> call void @llvm.amdgcn.raw.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3)
> @lds.3, i32 4, i32 0, i32 0, i32 0, i32 0)
> call void @llvm.amdgcn.raw.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3)
> %ptr, i32 4, i32 0, i32
rampitec wrote:
All split off parts were merged and this patch is merged with main. Only
waitcount insertion pass changes remained here.
https://github.com/llvm/llvm-project/pull/74537
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 1/9] [AMDGPU] Use alias info to relax waitcounts for LDS D
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 1/9] [AMDGPU] Use alias info to relax waitcounts for LDS D
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 1/8] [AMDGPU] Use alias info to relax waitcounts for LDS D
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 1/7] [AMDGPU] Use alias info to relax waitcounts for LDS D
rampitec wrote:
Yet another part to fix disjoint memory checks with LDS DMA:
https://github.com/llvm/llvm-project/pull/75249
https://github.com/llvm/llvm-project/pull/74537
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rampitec wrote:
Another part is improving memoperand info:
https://github.com/llvm/llvm-project/pull/75247. This is NFCI just by itself.
https://github.com/llvm/llvm-project/pull/74537
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rampitec wrote:
To make it easier I am splitting the patch. I have pre-comitted the test, and
there is a part which fixes lack of wait on GFX10 :
https://github.com/llvm/llvm-project/pull/75245
https://github.com/llvm/llvm-project/pull/74537
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/74537
>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 1/7] [AMDGPU] Use alias info to relax waitcounts for LDS D
rampitec wrote:
Ping
https://github.com/llvm/llvm-project/pull/74537
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https://github.com/rampitec updated
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>From 7e382620cdc5999c645ed0746f242595f0294c58 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Mon, 4 Dec 2023 16:11:53 -0800
Subject: [PATCH 1/7] [AMDGPU] Use alias info to relax waitcounts for LDS D
@@ -1209,6 +1209,15 @@ def G_FENCE : GenericInstruction {
let hasSideEffects = true;
}
+// Generic opcode equivalent to the llvm.prefetch intrinsic.
+def G_PREFETCH : GenericInstruction {
+ let OutOperandList = (outs);
+ let InOperandList = (ins ptype0:$address, i32imm:$rw
@@ -959,6 +967,32 @@ def : GCNPat <
}
} // let OtherPredicates = [HasShaderCyclesRegister]
+def SIMM24bitPtr : ImmLeaf (Imm);}]
+>;
+
+multiclass SMPrefetchPat {
+ def : GCNPat <
+(smrd_prefetch (SMRDImm i64:$sbase, i32:$offset), timm, timm, (i32
cache_type)),
+(!cas
@@ -959,6 +967,32 @@ def : GCNPat <
}
} // let OtherPredicates = [HasShaderCyclesRegister]
+def SIMM24bitPtr : ImmLeaf (Imm);}]
+>;
+
+multiclass SMPrefetchPat {
+ def : GCNPat <
+(smrd_prefetch (SMRDImm i64:$sbase, i32:$offset), timm, timm, (i32
cache_type)),
+(!cas
@@ -959,6 +967,32 @@ def : GCNPat <
}
} // let OtherPredicates = [HasShaderCyclesRegister]
+def SIMM24bitPtr : ImmLeaf (Imm);}]
+>;
+
+multiclass SMPrefetchPat {
+ def : GCNPat <
+(smrd_prefetch (SMRDImm i64:$sbase, i32:$offset), timm, timm, (i32
cache_type)),
+(!cas
https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/71989
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rampitec wrote:
Any tests?
https://github.com/llvm/llvm-project/pull/71989
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https://github.com/llvm/llvm-project/pull/70395
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rampitec wrote:
> I suppose left shift of negative values is undefined because if you shift out
> the sign bit you can overflow and get a positive value.
https://github.com/llvm/llvm-project/pull/68959
https://github.com/llvm/llvm-project/pull/68740
rampitec wrote:
> I suppose left shift of negative values is undefined because if you shift out
> the sign bit you can overflow and get a positive value.
Sounds like BS. It is defined. Unexpected maybe.
https://github.com/llvm/llvm-project/pull/68740
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/68740
>From cc9e065a9218eb36750a2c2a4a4d08fae3f329fa Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Oct 2023 13:36:25 -0700
Subject: [PATCH 1/6] [AMDGPU] Change the representation of double literals
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/68740
>From cc9e065a9218eb36750a2c2a4a4d08fae3f329fa Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Oct 2023 13:36:25 -0700
Subject: [PATCH 1/6] [AMDGPU] Change the representation of double literals
rampitec wrote:
> I've taken another look at this. The patch does not show any benefit from
> running another `SIFoldOperands` pass _after_ `SIShrinkInstructions` per se;
> you get exactly the same results (modulo a couple of add instructions that
> have their operands commuted differently) if
rampitec wrote:
I have measured compile time performance impact with timing
check-llvm-codegen-amdgpu on the release build:
```
before the patch: 11.06s
add folding:11.09s +0.2%
remove folding from shrink: 11.02s -0.4%
```
In general the impact smaller than run to run
rampitec wrote:
> I've just tested this on 1 graphics shaders and it seems to make no
> difference at all. I tried gfx900 and gfx1100. Can anyone else from the
> graphics team confirm this?
It seems the most impact is on the pre-gfx9 targets, very similar to
https://github.com/llvm/llvm-p
rampitec wrote:
> > I've just tested this on 1 graphics shaders and it seems to make no
> > difference at all. I tried gfx900 and gfx1100. Can anyone else from the
> > graphics team confirm this?
>
> I can confirm no difference on gfx1102
gfx11 is the same as gfx10, it just bails because
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