On 12/14/21 3:42 PM, Vladimir Isaev wrote:
> On Dec 14, 2021 3:18 PM, Barbaros Tokaoglu wrote:
>> For 16 kB data cache with 4 ways and 32 byte cache lines we have tag LSB
>> [(128 locations for each way: 7 bits) + byte offset (32 bytes: 5 bits)]
>> lower than page offset (1
each cacheline iteration.
Signed-off-by: Barbaros Tokaoglu
---
arch/arc/mm/cache.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 8aa1231..d0875a8 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
On 12/14/21 11:36 AM, Vladimir Isaev wrote:
> On Dec 11, 2021 3:12 AM Barbaros Tokaoglu wrote:
>> This patch is for a problem we observed on an ARC770D and MMUv3
>> implementation.
>> The problem was although __flush_dcache_page() returns there were some
>> cacheline
&
on each cacheline iteration.
Signed-off-by: Barbaros Tokaoglu
---
arch/arc/mm/cache.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 8aa1231..d0875a8 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
sical address helped flushing
cacheline entries to DDR.
This patch is open for your considerations.
Signed-off-by: Barbaros Tokaoglu
---
arch/arc/mm/cache.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 8aa1231..d0
