On 12/14/21 11:36 AM, Vladimir Isaev wrote: > On Dec 11, 2021 3:12 AM Barbaros Tokaoglu wrote: >> This patch is for a problem we observed on an ARC770D and MMUv3 >> implementation. >> The problem was although __flush_dcache_page() returns there were some >> cacheline >> entries that didn't flush to DDR. In our case updating ARC_REG_DC_PTAG >> register >> on each cacheline iteration with updated physical address helped flushing >> cacheline entries to DDR. > > Thank you for sending the patch, looks like it is really possible to have > this problem > for certain cache/MMU configurations for ARC700. > > It will be great to have configuration which causes the bug in the commit > message, > so it will explain for future reader why this change is needed. i.e. > something like > 'For X kB cache with X ways we have tag LSB (cache_size/num_ways) lower than > page offset (XX bits for X kB pages). So it is possible for PTAG to change > even for > single page loop.' > > Thank you, > Vladimir Isaev > Sent as v2 with updated commit message to include the cache configuration.
Best Regards, Barbaros _______________________________________________ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
