Re: [PATCH] crypto: marvell/cesa - Fix use of sg_pcopy on iomem pointer

On Fri, Jan 22, 2021 at 09:40:27PM +1100, Herbert Xu wrote: > On Fri, Jan 22, 2021 at 11:02:03AM +0100, Sven Auhagen wrote: > > > > Hi Herbert, > > > > sorry, no luck on my armfh system with this patch: > > > > [16.310405] INFO: task cryptomgr_test:7698

Re: [PATCH] crypto: marvell/cesa - Fix use of sg_pcopy on iomem pointer

On Thu, Jan 21, 2021 at 04:16:46PM +1100, Herbert Xu wrote: > The cesa driver mixes use of iomem pointers and normal kernel > pointers. Sometimes it uses memcpy_toio/memcpy_fromio on both > while other times it would use straight memcpy on both, through > the sg_pcopy_* helpers. > > This patch fi

Re: [PATCH] crypto: marvel/cesa - Fix tdma descriptor on 64-bit

o: marvell/cesa - Fix sparse warnings") > Reported-by: Sven Auhagen > Signed-off-by: Herbert Xu > > diff --git a/drivers/crypto/marvell/cesa/cesa.h > b/drivers/crypto/marvell/cesa/cesa.h > index fabfaaccca87..fa56b45620c7 100644 > --- a/drivers/crypto/marvell/cesa/cesa

Re: [BUG] marvell/cesa - Fix sparse warnings breaks driver

On Wed, Jan 20, 2021 at 04:26:29PM +1100, Herbert Xu wrote: > On Mon, Jan 18, 2021 at 10:18:08AM +0100, Sven Auhagen wrote: > > > > Also on my 5.10 Kernel the hash tests are failing now > > but this also happens when I remove your patch: > > > > [6.859791] al

[BUG] marvell/cesa - Fix sparse warnings breaks driver

Hi Herbert, your patch crypto: marvell/cesa - Fix sparse warnings unfortunately breaks the cesa driver. I am using it on my Armada 388 board and with that patch applied the self test stalls indefinitely. I tried to find out which part of the patch but it seems all of the different changes have b

[PATCH 1/1 v3] marvell cesa irq balance

off-by: Sven Auhagen --- v3: * use NUMA_NO_NODE constant v2: * use cpumask_local_spread and remove affinity on module remove drivers/crypto/marvell/cesa/cesa.c | 11 ++- drivers/crypto/marvell/cesa/cesa.h | 1 + 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/cry

[PATCH 1/1 v3] inside-secure irq balance

Balance the irqs of the inside secure driver over all available cpus. Currently all interrupts are handled by the first CPU. >From my testing with IPSec AES-GCM 256 on my MCbin with 4 Cores I get a 50% speed increase: Before the patch: 99.73 Kpps With the patch: 151.25 Kpps Signed-off-by: S

Re: [PATCH 1/1 v2] inside-secure irq balance

On Sat, Jul 18, 2020 at 04:25:29PM +0300, Ard Biesheuvel wrote: > On Sat, 18 Jul 2020 at 12:43, Sven Auhagen wrote: > > > > Balance the irqs of the inside secure driver over all > > available cpus. > > Currently all interrupts are handled by the first CPU. > > &

[PATCH 1/1 v2] marvell cesa irq balance

off-by: Sven Auhagen --- v2: * use cpumask_local_spread and remove affinity on module remove drivers/crypto/marvell/cesa/cesa.c | 11 ++- drivers/crypto/marvell/cesa/cesa.h | 1 + 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/marvell/cesa/cesa.c b/driv

[PATCH 1/1 v2] inside-secure irq balance

Balance the irqs of the inside secure driver over all available cpus. Currently all interrupts are handled by the first CPU. >From my testing with IPSec AES-GCM 256 on my MCbin with 4 Cores I get a 50% speed increase: Before the patch: 99.73 Kpps With the patch: 151.25 Kpps Signed-off-by: S

Re: [PATCH 1/1] inside-secure irq balance

On Fri, Jul 17, 2020 at 04:57:38PM +1000, Herbert Xu wrote: > On Fri, Jul 17, 2020 at 08:35:04AM +0200, Sven Auhagen wrote: > > > > I disagree as this is common practice among other kernel drivers > > like ethernet. > > Also this is also beeing done in other crypto driv

Re: [PATCH 1/1] inside-secure irq balance

On Fri, Jul 17, 2020 at 03:20:50PM +1000, Herbert Xu wrote: > On Fri, Jul 17, 2020 at 07:01:34AM +0200, Sven Auhagen wrote: > > > > Alright, that makes sense, thank you. > > > > As I said in my second email yesterday, it is just a hint and not binding. > >

Re: [PATCH 1/1] inside-secure irq balance

On Thu, Jul 16, 2020 at 10:04:20PM +1000, Herbert Xu wrote: > On Thu, Jul 16, 2020 at 11:21:36AM +0200, Sven Auhagen wrote: > > > > You are correct, let me have a look at how to get the cpu bit correctly. > > Well everything runs on the first CPU now, what do you do if that

Re: [PATCH 1/1] inside-secure irq balance

On Thu, Jul 16, 2020 at 08:44:23AM +, Van Leeuwen, Pascal wrote: > > -Original Message- > > From: linux-crypto-ow...@vger.kernel.org > > On Behalf Of Herbert Xu > > Sent: Thursday, July 16, 2020 9:22 AM > > To: Sven Auhagen > > Cc: linux-cr

Re: [PATCH 1/1] inside-secure irq balance

On Thu, Jul 16, 2020 at 08:44:23AM +, Van Leeuwen, Pascal wrote: > > -Original Message- > > From: linux-crypto-ow...@vger.kernel.org > > On Behalf Of Herbert Xu > > Sent: Thursday, July 16, 2020 9:22 AM > > To: Sven Auhagen > > Cc: linux-cr

[PATCH 1/1] marvell cesa irq balance

off-by: Sven Auhagen --- drivers/crypto/marvell/cesa/cesa.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/marvell/cesa/cesa.c b/drivers/crypto/marvell/cesa/cesa.c index 8a5f0b0bdf77..bf1bda2e904a 100644 --- a/drivers/crypto/marvell/cesa/cesa.c +++ b/driv

Re: [PATCH v1] fixes

Hi, I am sorry, please ignore this email. It was send by mistake. Best Sven On Wed, Jul 08, 2020 at 05:06:05PM +0200, sven.auha...@voleatech.de wrote: > From: Sven Auhagen > > --- > drivers/crypto/inside-secure/safexcel.h| 1 + > drivers/crypto/inside-secure/safexc

[PATCH 1/1] inside-secure irq balance

Balance the irqs of the inside secure driver over all available cpus. Currently all interrupts are handled by the first CPU. >From my testing with IPSec AES-GCM 256 on my MCbin with 4 Cores I get a 50% speed increase: Before the patch: 99.73 Kpps With the patch: 151.25 Kpps Signed-off-by: S

[PATCH v1] fixes

From: Sven Auhagen --- drivers/crypto/inside-secure/safexcel.h| 1 + drivers/crypto/inside-secure/safexcel_cipher.c | 6 +- drivers/crypto/inside-secure/safexcel_hash.c | 6 ++ 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/inside-secure