On Thu, Jul 16, 2020 at 08:44:23AM +0000, Van Leeuwen, Pascal wrote: > > -----Original Message----- > > From: linux-crypto-ow...@vger.kernel.org > > <linux-crypto-ow...@vger.kernel.org> On Behalf Of Herbert Xu > > Sent: Thursday, July 16, 2020 9:22 AM > > To: Sven Auhagen <sven.auha...@voleatech.de> > > Cc: linux-crypto@vger.kernel.org > > Subject: Re: [PATCH 1/1] inside-secure irq balance > > > > <<< External Email >>> > > Sven Auhagen <sven.auha...@voleatech.de> wrote: > > > > > > + // Set affinity > > > + cpu = ring_id % num_online_cpus(); > > > + irq_set_affinity_hint(irq, get_cpu_mask(cpu)); > > > + > > > > This doesn't look right. There is no guarantee that the online > > CPUs are the lowest bits in the bitmask. Also, what are you going > > to do when the CPUs go down (or up)? > >
You are correct, let me have a look at how to get the cpu bit correctly. Well everything runs on the first CPU now, what do you do if that does down or up? I think there is no mechanism in general at the moment for the current or my implementation. > > Ok, I was just about to test this patch with my hardware, but I suppose I can > spare myself the > trouble if it doesn't make sense. I already had a hunch it was too simplistic > for general use. > However, he does get a very significant speed boost out of this, which makes > sense as having > the interrupts properly distributed AND pinned to a fixed CPU ensures proper > workload > distribution and cache locality. In fact, this was the whole idea behind > having multiple rings > and interrupts. > > So is there a better way to achieve the same goal from the driver? Or is this > really something > you cannot fix in the crypto driver itself? > > > Cheers, > > -- > > Email: Herbert Xu <herb...@gondor.apana.org.au> > > Home Page: > > https://eur03.safelinks.protection.outlook.com/?url=http:%2F%2Fgondor.apana.org.au%2F~herbert%2F&data=02%7C01%7Csven.auhagen%40voleatech.de%7C42783499b8fa4d11a9c608d8296474d2%7Cb82a99f679814a7295344d35298f847b%7C0%7C0%7C637304858734739951&sdata=GNleSUVRQe56P%2BkG6OQ3JH7AkXzKve6UP6ai5dKpN0M%3D&reserved=0 > > PGP Key: > > https://eur03.safelinks.protection.outlook.com/?url=http:%2F%2Fgondor.apana.org.au%2F~herbert%2Fpubkey.txt&data=02%7C01%7Csven.auhagen%40voleatech.de%7C42783499b8fa4d11a9c608d8296474d2%7Cb82a99f679814a7295344d35298f847b%7C0%7C0%7C637304858734739951&sdata=nqUVTBAMn1ifyR6lj9nyxBFQZNR9Au8r0aUJR44ziyc%3D&reserved=0 > > Regards, > Pascal van Leeuwen > Silicon IP Architect Multi-Protocol Engines, Rambus Security > Rambus ROTW Holding BV > +31-73 6581953 > > Note: The Inside Secure/Verimatrix Silicon IP team was recently acquired by > Rambus. > Please be so kind to update your e-mail address book with my new e-mail > address. > > > ** This message and any attachments are for the sole use of the intended > recipient(s). It may contain information that is confidential and privileged. > If you are not the intended recipient of this message, you are prohibited > from printing, copying, forwarding or saving it. Please delete the message > and attachments and notify the sender immediately. ** > > Rambus > Inc.<https://eur03.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.rambus.com%2F&data=02%7C01%7Csven.auhagen%40voleatech.de%7C42783499b8fa4d11a9c608d8296474d2%7Cb82a99f679814a7295344d35298f847b%7C0%7C0%7C637304858734739951&sdata=gCBXI0rNikA%2FG2ME7RxWwwmkuUNl9wRlyQqDGbFoGHk%3D&reserved=0>
