On Thu, Dec 17, 2020 at 11:11 AM Eric Biggers wrote:
>
> On Wed, Dec 16, 2020 at 09:41:38AM -0800, Chang S. Bae wrote:
> > [1] Intel Architecture Instruction Set Extensions Programming Reference:
> >
> > https://software.intel.com/content/dam/develop/external/us/en/documents/architecture-inst
/drivers/nvdimm/claim.c
> +++ b/drivers/nvdimm/claim.c
> @@ -200,11 +200,10 @@ ssize_t nd_namespace_store(struct device *dev,
> }
> break;
> default:
> len = -EBUSY;
> goto out_attach;
> - break;
> }
Acked-by: Dan Williams
On Wed, Sep 27, 2017 at 9:31 AM, Casey Leedom wrote:
> | From: Dan Williams
> | Sent: Tuesday, September 26, 2017 9:10 AM
> |
> | On Tue, Sep 26, 2017 at 9:06 AM, Casey Leedom wrote:
> | > | From: Robin Murphy
> | > | Sent: Tuesday, Se
On Tue, Sep 26, 2017 at 9:06 AM, Casey Leedom wrote:
> | From: Robin Murphy
> | Sent: Tuesday, September 26, 2017 7:22 AM
>
> |
> | On 26/09/17 13:21, Harsh Jain wrote:
> | > Find attached new set of log. After repeated tries it panics.
> |
> | Thanks, that makes things a bit clearer - looks like
On Mon, Sep 25, 2017 at 1:05 PM, Casey Leedom wrote:
> | From: Dan Williams
> | Sent: Monday, September 25, 2017 12:31 PM
> | ...
> | IIUC it looks like this has been broken ever since commit e1605495c716
> | "intel-iommu: Introduce domain_sg_mapping() to speed up
> | i
breaks on platforms where sizeof(phys_addr_t) > sizeof(unsigned
long). I.e. it's not always safe to assume that PAGE_MASK is the
correct width.
> | phys_pfn = pteval >> VTD_PAGE_SHIFT;
> | }
>
> Adding some likely people to the
Broadcom SBA RAID driver
> dt-bindings: Add DT bindings document for Broadcom SBA RAID driver
For the dmaengine and async_tx changes:
Acked-by: Dan Williams
The raid change should get an ack from Shaohua.
On Tue, Feb 14, 2017 at 11:03 PM, Anup Patel wrote:
> On Wed, Feb 15, 2017 at 12:13 PM, Dan Williams
> wrote:
>> On Tue, Feb 14, 2017 at 10:25 PM, Anup Patel wrote:
>>> On Tue, Feb 14, 2017 at 10:04 PM, Dan Williams
>>> wrote:
>>>> On Mon, Feb 13,
On Tue, Feb 14, 2017 at 10:25 PM, Anup Patel wrote:
> On Tue, Feb 14, 2017 at 10:04 PM, Dan Williams
> wrote:
>> On Mon, Feb 13, 2017 at 10:51 PM, Anup Patel wrote:
>>> The Broadcom stream buffer accelerator (SBA) provides offloading
>>> capabilities for RAI
On Mon, Feb 13, 2017 at 10:51 PM, Anup Patel wrote:
> The Broadcom stream buffer accelerator (SBA) provides offloading
> capabilities for RAID operations. This SBA offload engine is
> accessible via Broadcom SoC specific ring manager.
>
> This patch adds Broadcom SBA RAID driver which provides one
On Fri, Feb 10, 2017 at 1:07 AM, Anup Patel wrote:
> The Broadcom stream buffer accelerator (SBA) provides offloading
> capabilities for RAID operations. This SBA offload engine is
> accessible via Broadcom SoC specific ring manager.
>
> This patch adds Broadcom SBA RAID driver which provides one
On Thu, Feb 9, 2017 at 1:29 AM, Anup Patel wrote:
> On Wed, Feb 8, 2017 at 9:54 PM, Dan Williams wrote:
>> On Wed, Feb 8, 2017 at 12:57 AM, Anup Patel wrote:
>>> On Tue, Feb 7, 2017 at 11:46 PM, Dan Williams
>>> wrote:
>>>> On Tue, Feb 7, 2017 at 1:02 A
On Wed, Feb 8, 2017 at 12:57 AM, Anup Patel wrote:
> On Tue, Feb 7, 2017 at 11:46 PM, Dan Williams
> wrote:
>> On Tue, Feb 7, 2017 at 1:02 AM, Anup Patel wrote:
>>> On Tue, Feb 7, 2017 at 1:57 PM, Dan Williams
>>> wrote:
>>>> On Tue, Feb 7,
On Tue, Feb 7, 2017 at 1:02 AM, Anup Patel wrote:
> On Tue, Feb 7, 2017 at 1:57 PM, Dan Williams wrote:
>> On Tue, Feb 7, 2017 at 12:16 AM, Anup Patel wrote:
>>> The DMAENGINE framework assumes that if PQ offload is supported by a
>>> DMA device then all 256 PQ coeff
On Tue, Feb 7, 2017 at 12:16 AM, Anup Patel wrote:
> The DMAENGINE framework assumes that if PQ offload is supported by a
> DMA device then all 256 PQ coefficients are supported. This assumption
> does not hold anymore because we now have BCM-SBA-RAID offload engine
> which supports PQ offload wit
On Fri, Feb 3, 2017 at 2:59 AM, Anup Patel wrote:
>
>
> On Thu, Feb 2, 2017 at 11:31 AM, Dan Williams
> wrote:
>>
>> On Wed, Feb 1, 2017 at 8:47 PM, Anup Patel
>> wrote:
>> > The DMAENGINE framework assumes that if PQ offload is supported by a
>>
On Wed, Feb 1, 2017 at 8:47 PM, Anup Patel wrote:
> The DMAENGINE framework assumes that if PQ offload is supported by a
> DMA device then all 256 PQ coefficients are supported. This assumption
> does not hold anymore because we now have BCM-SBA-RAID offload engine
> which supports PQ offload with
e, and that no other
> driver does it.
>
> Fixes: 0f80830dd044 ("mm/page_ref: add tracepoint to track down page
> reference manipulation")
> Signed-off-by: Arnd Bergmann
Acked-by: Dan Williams
Vinod, will you take this one?
--
To unsubscribe from this list: sen
On Fri, Aug 7, 2015 at 9:15 AM, Christoph Hellwig wrote:
> From: Dan Williams
>
> Coccinelle cleanup to replace open coded sg to physical address
> translations. This is in preparation for introducing scatterlists that
> reference __pfn_t.
>
> // sg_phys.cocci: conve
[ adding Boaz as this discussion has implications for ore_raid ]
On Tue, May 26, 2015 at 2:45 AM, Maxime Ripard
wrote:
> On Mon, May 18, 2015 at 10:06:55AM -0700, Dan Williams wrote:
>> On Mon, May 18, 2015 at 2:14 AM, Maxime Ripard
>> wrote:
>> > Hi Dan,
>> >
&
On Mon, May 18, 2015 at 2:14 AM, Maxime Ripard
wrote:
> Hi Dan,
>
> On Wed, May 13, 2015 at 09:00:46AM -0700, Dan Williams wrote:
>> On Wed, May 13, 2015 at 2:17 AM, Maxime Ripard
>> wrote:
>> > Hi Dan,
>> >
>> > On Tue, May 12, 2015 at 09:05:41AM
On Tue, Sep 4, 2012 at 5:28 AM, Liu Qiang-B32616 wrote:
>> Will this engine be coordinating with another to handle memory copies?
>> The dma mapping code for async_tx/raid is broken when dma mapping
>> requests overlap or cross dma device boundaries [1].
>>
>> [1]: http://marc.info/?l=linux-arm-k
On Thu, Aug 9, 2012 at 1:23 AM, wrote:
> From: Qiang Liu
>
> The use of spin_lock_irqsave() is a stronger locking mechanism than is
> required throughout the driver. The minimum locking required should be
> used instead. Interrupts will be turned off and context will be saved,
> there is needles
On Thu, Aug 9, 2012 at 1:20 AM, wrote:
> From: Qiang Liu
>
> Expose Talitos's XOR functionality to be used for RAID parity
> calculation via the Async_tx layer.
>
> Cc: Herbert Xu
> Cc: David S. Miller
> Signed-off-by: Dipen Dudhat
> Signed-off-by: Maneesh Gupta
> Signed-off-by: Kim Phillips
On Thu, Aug 30, 2012 at 7:23 AM, Geanta Neag Horia Ioan-B05471
wrote:
>
> Besides these:
> 1. As Dan Williams mentioned, you should explain why you are using
> both spin_lock_bh and spin_lock_irqsave on the same lock.
It looks like talitos_process_pending() can be called from hardirq
On Wed, 2012-08-29 at 11:15 +, Liu Qiang-B32616 wrote:
> Hi Dan,
>
> Ping?
> Can you apply these patches? Thanks.
>
I'm working my way through them.
The first thing I notice is that xor_chan->desc_lock is taken
inconsistently. I.e. spin_lock_irqsave() in talitos_process_pending()
and spin_
On Tue, Aug 14, 2012 at 2:04 AM, Liu Qiang-B32616 wrote:
> Hi Vinod,
>
> Would you like to apply this series from patch 2/8 to 7/8) in your tree?
> The link as below,
> http://patchwork.ozlabs.org/patch/176023/
> http://patchwork.ozlabs.org/patch/176024/
> http://patchwork.ozlabs.org/patch/176025/
submitted just now, but async_tx must check whether this depend
> tx descriptor is acked, there are poison contents in the invalid address,
> then BUG_ON() is thrown, so this descriptor will be freed in the next time.
>
> Cc: Dan Williams
> Cc: Vinod Koul
> Cc: Li Yang
> Signed
[adding Boaz since he also made an attempt at fixing this]
http://marc.info/?l=linux-crypto-vger&m=13182924450&w=2
...I had meant to follow up on this, but was buried in 'isci' issues.
On Tue, Apr 3, 2012 at 4:56 PM, Jim Kukunas
wrote:
> On Tue, Apr 03, 2012 at 11:23:16AM +0100, John Robin
[ adding Greg ]
On Thu, Sep 30, 2010 at 5:16 PM, Tirumala Marri wrote:
>> Where iop_adma_alloc_slots() is implemented differently between
>> iop13xx and iop3xx. In this case why does ppc440spe-adma.h exist? If
>> it has code specific to ppe440spe it should just live in the ppe440spe
>> C file.
On Thu, Sep 30, 2010 at 12:08 PM, Wolfgang Denk wrote:
[snip other valid review comments]
>
> This is a header file, yet you add here literally thousands of lines of
> code.
Yes, these functions are entirely too large to be inlined. It looks
like you are trying to borrow too heavily from the iop
On 9/23/2010 3:44 PM, Tirumala Marri wrote:
Did you look at this changelog before sending? It just deletes 4000
lines of code??
[Marri] The reason I have to send it in different file is the size of the
patch.
There seem to be issue with patch sizes 200k or more.
Read the rest of what I wrote
On 9/23/2010 3:11 PM, tma...@apm.com wrote:
From: Tirumala Marri
This patch creates new file with SoC dependent functions.
Signed-off-by: Tirumala R Marri
---
V1:
* Remove all 440SPe specific references.
Maybe it renames ppc440spe to ppc4xx but it adds things like...
+#if defined(CONFIG_
On 9/23/2010 3:10 PM, tma...@apm.com wrote:
From: Tirumala Marri
This patch generalizes the existing drver/dma/ppc4xx/adma.c, so that
common code can be shared between different similar DMA engine
drivers in other SoCs. Also Makefile and Kconfig changed to accommodate
PPC4XX.
Signed-off-by: Tir
On Fri, Sep 17, 2010 at 6:42 PM, wrote:
> From: Tirumala Marri
> This patch combines drivers/dma/ppc4xx/xor.h and driver/dma/dma/ppc4xx/dma.h
> into drivers/dma/ppc4xx/ppx440spe-dma.h .
>
Is this just code churn, or do we gain anything by combining these
header files? Don't add "ppc440spe-" ba
On 9/17/2010 6:42 PM, tma...@apm.com wrote:
From: Tirumala Marri
This patch generalizes the existing drver/dma/ppc4xx/adma.c, so that
common code can be shared between different similar DMA engine
drivers in other SoCs.
Signed-off-by: Tirumala R Marri
---
drivers/dma/ppc4xx/adma.c| 43
On Thu, Jul 22, 2010 at 11:15 PM, Stefan Roese wrote:
> Hi Marri,
>
> On Friday 23 July 2010 02:57:18 tma...@amcc.com wrote:
>> From: Tirumala Marri
>>
>> This patch will add ADMA support for DMA engine and HW offload for
>> XOR/ADG (RAID-5/6) functionalities.
>> 1. It supports memcpy, xor,
On Fri, Dec 18, 2009 at 8:02 AM, Li Yang-R58472 wrote:
>
>>Subject: Re: [PATCH v2 2/2] Crypto: Talitos: Support for
>>Async_tx XOR offload
>>
>>Ira W. Snyder wrote:
>>> Yes, I have used the device_prep_dma_interrupt()
>>functionality quite a
>>> while back. However, I found it to be pretty much us
On Thu, Dec 17, 2009 at 11:45 AM, Kumar Gala wrote:
>> The specific case it is needed for Talitos/raid is a channel switch
>> interrupt. The interrupt causes the cleanup operation to be run which will
>> kick off any pending dependent operations on the xor channel. In the raid
>> case we only
Ira W. Snyder wrote:
Yes, I have used the device_prep_dma_interrupt() functionality quite a
while back. However, I found it to be pretty much useless.
The specific case it is needed for Talitos/raid is a channel switch
interrupt. The interrupt causes the cleanup operation to be run which
wil
Kumar Gala wrote:
Changes with respect to v1 as per comments received
o. Rebased to linux-next as of 20091216
o. The selection is based exclusive of fsldma
o. Intoduced a new Kernel Configuration variable
*. This enables selecting the Cryptographic functionality
of Talitos along with fsldm
Suresh Vishnu-B05022 wrote:
> On Mon, Dec 14, 2009 at 6:33 AM, Vishnu Suresh
wrote:
> > The async_tx descriptors contains dangling pointers.
> > Hence, re-initialize them to NULL before use.
> >
> > Signed-off-by: Vishnu Suresh
> > ---
> > o. Rebased to linux-next as of 20091214
> >
>
On Mon, Dec 14, 2009 at 6:33 AM, Vishnu Suresh wrote:
> The async_tx descriptors contains dangling pointers.
> Hence, re-initialize them to NULL before use.
>
> Signed-off-by: Vishnu Suresh
> ---
> o. Rebased to linux-next as of 20091214
>
> drivers/crypto/talitos.c | 3 +++
> 1 files changed
On Wed, Oct 14, 2009 at 11:41 PM, Vishnu Suresh wrote:
[..]
> diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
> index b08403d..343e578 100644
> --- a/drivers/crypto/Kconfig
> +++ b/drivers/crypto/Kconfig
> @@ -192,6 +192,8 @@ config CRYPTO_DEV_TALITOS
> select CRYPTO_ALGAPI
>
[ added Leo and Timur to the Cc ]
On Wed, Oct 14, 2009 at 11:41 PM, Vishnu Suresh wrote:
> This patch disables the use of DMA_INTERRUPT capability with Async_tx
>
> The fsldma produces a null transfer with DMA_INTERRUPT
> capability when used with Async_tx. When RAID devices queue
> a transaction
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