For example the Xscale datasheet defines:
" Both LDRD and STRD instructions will generate an alignment exception
when the address bits [2:0] = 0b100."
LDRD and STRD are load/store double instructions, and they are used when
using an u64 variable in C code, when compiling with the latest CSL
compil
On Sun, Jan 22, 2006 at 11:27:18AM +0200, Ronen Shitrit wrote:
> You are right in a 64 bit processor we should not find this issue.
> But on ARM926 (32 bit) we definitely have a problem.
Why does the ARM926 require 64-bit alignment?
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You are right in a 64 bit processor we should not find this issue.
But on ARM926 (32 bit) we definitely have a problem.
Regards,
Ronen Shitrit
-Original Message-
From: Herbert Xu [mailto:[EMAIL PROTECTED]
Sent: Friday, January 20, 2006 4:03 AM
To: Ronen Shitrit
Cc: linux-crypto@vger.kern
kernel 2.6.12.
I took a look on 2.6.15, and I think we have the same problem there.
Regards
Ronen Shitrit
-Original Message-
From: David S. Miller [mailto:[EMAIL PROTECTED]
Sent: Friday, January 20, 2006 7:49 AM
To: Ronen Shitrit
Cc: linux-crypto@vger.kernel.org
Subject: Re: alignment e
