For example the Xscale datasheet defines: " Both LDRD and STRD instructions will generate an alignment exception when the address bits [2:0] = 0b100."
LDRD and STRD are load/store double instructions, and they are used when using an u64 variable in C code, when compiling with the latest CSL compiler with the new ARM EABI. Regards Ronen Shitrit -----Original Message----- From: Herbert Xu [mailto:[EMAIL PROTECTED] Sent: Sunday, January 22, 2006 12:41 PM To: Ronen Shitrit Cc: [email protected] Subject: Re: alignment exception on MD5 code. On Sun, Jan 22, 2006 at 11:27:18AM +0200, Ronen Shitrit wrote: > You are right in a 64 bit processor we should not find this issue. > But on ARM926 (32 bit) we definitely have a problem. Why does the ARM926 require 64-bit alignment? Cheers, -- Visit Openswan at http://www.openswan.org/ Email: Herbert Xu ~{PmV>HI~} <[EMAIL PROTECTED]> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt - To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
