RE: [PATCHv4 4/7] drm/i915/histogram: histogram interrupt handling

> -Original Message- > From: dri-devel On Behalf Of > Arun R Murthy > Sent: Wednesday, September 25, 2024 8:38 PM > To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; dri- > de...@lists.freedesktop.org > Cc: Murthy, Arun R > Subject: [PATCHv4 4/7] drm/i915/histogram:

[PATCH 3/4] drm/i914/xe3lpd: Increase bigjoiner limitations

With 6k resolution support for a single crtc being added bigjoiner will only come into picture when hdisplay > 6144 Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dp.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_

[PATCH 4/4] drm/i915/xe3lpd: Prune modes for YUV420

We only support resolution up to 4k for single pipe when using YUV420 format so we prune these modes and restrict the plane size at src. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_dp.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display

[PATCH 2/4] drm/i915/xe3lpd: Increase max_h max_v for PSR

Spec states that PSR max active is same as max pipe active values. Now that each pipe supports 6k resolution increasing max_h and max_v for PSR too. Signed-off-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_psr.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/

[PATCH 1/4] drm/i915/xe3lpd: Increase resolution for plane to support 6k

DISPLAY_VER >= 30 onwards CRTC can now support 6k resolution. Increase pipe and plane max width and height to reflect this increase in resolution. --v2 -Take care of the subsampling scenario sooner rather than later [Matt] Signed-off-by: Arun R Murthy Signed-off-by: Suraj Kandpal --- drivers/g

[PATCH xe-i915-for-6.11 02/22] drm/i915: disable fbc due to Wa_16023588340

From: Matthew Auld commit c55f79f317ab428ae6d005965bc07e37496f209f upstream. On BMG-G21 we need to disable fbc due to complications around the WA. v2: - Try to handle with i915_drv.h and compat layer. (Rodrigo) v3: - For simplicity retreat back to the original design for now. - Drop the extr

[PATCH xe-i915-for-6.11 08/22] drm/i915/display/dp: Compute AS SDP when vrr is also enabled

From: Mitul Golani commit eb53e5b933b9ff315087305b3dc931af3067d19c upstream. AS SDP should be computed when VRR timing generator is also enabled. Correct the compute condition to compute params of Adaptive sync SDP when VRR timing genrator is enabled along with sink support indication. --v2: Mo

RE: [PATCH] drm/xe/hdcp: Add check to remove hdcp2 compatibility

> -Original Message- > From: Roper, Matthew D > Sent: Thursday, October 24, 2024 1:15 AM > To: Kandpal, Suraj > Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Nautiyal, > Ankit K ; Ghimiray, Himal Prasad > > Subject: Re: [PATCH] drm/xe/hdcp: Add check to remove h

RE: [PATCH v4 3/7] drm/i915/xe3lpd: Disable HDCP Line Rekeying for Xe3

> -Original Message- > From: Roper, Matthew D > Sent: Wednesday, October 23, 2024 11:22 PM > To: Atwood, Matthew S > Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Kandpal, > Suraj > Subject: Re: [PATCH v4 3/7] drm/i915/xe3lpd: Disable HDCP Line Rekeying for > Xe

RE: [PATCH 1/4] drm/i915/xe3lpd: Increase resolution for plane to support 6k

> -Original Message- > From: Roper, Matthew D > Sent: Thursday, October 24, 2024 3:11 AM > To: Kandpal, Suraj > Cc: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org; Shankar, > Uma ; Kulkarni, Vandita > ; Murthy, Arun R > Subject: Re: [PATCH 1/4] drm/i915/xe3lpd: Increa

[PATCH v2 11/12] drm/i915/xe3lpd: Skip disabling VRR during modeset disable

From: Ravi Kumar Vodapalli Spec does not request to disable VRR in the modeset disabling sequence for DP and HDMI for xe3_lpd. Bspec: 68848 Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Matt Atwood --- drivers/gpu/drm/i915/display/intel_display.c | 8 +--- 1 file changed, 5 insertion

[PATCH v2 04/12] drm/i915/display/ptl: Fill VRR crtc_state timings before other transcoder timings

From: Mitul Golani In progress to make VRR timing generator as the default timing generator, rest other timings will be derived based on vrr.vmin and vrr.vmax. Call intel_vrr_get_config before intel_get_transcoder_timings to accommodate values getting pre-filled. Signed-off-by: Mitul Golani Sig

[PATCH v2 12/12] drm/i915/xe3lpd: Power request asserting/deasserting

From: Mika Kahola There is a HW issue that arises when there are race conditions between TCSS entering/exiting TC7 or TC10 states while the driver is asserting/deasserting TCSS power request. As a workaround, Display driver will implement a mailbox sequence to ensure that the TCSS is in TC0 when

[PATCH v2 03/12] drm/i915/xe3lpd: Add check to see if edp over type c is allowed

From: Suraj Kandpal Read PICA register to see if edp over type C is possible and then add the appropriate tables for it. --v2 -remove bool from intel_encoder have it in runtime_info [Jani] -initialize the bool in runtime_info init [Jani] -dont abbreviate the bool [Jani] Bspec: 68846 Signed-off-

Re: [PATCH v2 10/12] drm/i915/display/xe3: disable x-tiled framebuffers

Quoting Clint Taylor (2024-10-23 18:46:59-03:00) >From: "Heikkila, Juha-pekka" > >Xe3 has no more support for x-tile on display. > >v2: Include up to display 29 for X-tiled support. (Gustavo) We usually do not define the changelog via git trailers, so I think a blank line is necessary here. With

[PATCH v2 06/12] drm/i915/cx0: Extend C10 check to PTL

From: Dnyaneshwar Bhadane When deciding the type of the phy, add PTL support to make sure the correct path is taken for selection of C10 PHY. Only port A is connected C10 PHY for Pantherlake. Bspec: 72571 Signed-off-by: Dnyaneshwar Bhadane Signed-off-by: Matt Atwood Signed-off-by: Clint Taylo

[PATCH v2 01/12] drm/i915/xe3lpd: Update pmdemand programming

From: Matt Roper There are some minor changes to pmdemand handling on Xe3: - Active scalers are no longer tracked. We can simply skip the readout and programming of this field. - Active dbuf slices are no longer tracked. We should skip the readout and programming of this field and also

Re: [PATCH v2 12/12] drm/i915/xe3lpd: Power request asserting/deasserting

Quoting Clint Taylor (2024-10-23 18:47:01-03:00) >From: Mika Kahola > >There is a HW issue that arises when there are race conditions >between TCSS entering/exiting TC7 or TC10 states while the >driver is asserting/deasserting TCSS power request. As a >workaround, Display driver will implement a m

Re: [PATCH 1/4] drm/i915/xe3lpd: Increase resolution for plane to support 6k

On Tue, Oct 15, 2024 at 11:40:08AM +0530, Suraj Kandpal wrote: > DISPLAY_VER >= 30 onwards CRTC can now support 6k resolution. > Increase pipe and plane max width and height to reflect this > increase in resolution. > > Signed-off-by: Arun R Murthy > Signed-off-by: Suraj Kandpal > --- > drivers

Re: [PATCH v2 01/12] drm/i915/xe3lpd: Update pmdemand programming

Quoting Clint Taylor (2024-10-23 18:46:50-03:00) >From: Matt Roper > >There are some minor changes to pmdemand handling on Xe3: > - Active scalers are no longer tracked. We can simply skip the readout > and programming of this field. > - Active dbuf slices are no longer tracked. We should skip

Re: ✗ Fi.CI.IGT: failure for Add xe3lpd edp enabling (rev4)

On Fri, Oct 18, 2024 at 10:25:29PM -, Patchwork wrote: > == Series Details == > > Series: Add xe3lpd edp enabling (rev4) > URL : https://patchwork.freedesktop.org/series/139731/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_15562_full -> Patchwork_139731v4_full >

[PATCH v2 02/12] drm/i915/xe3lpd: Disable HDCP Line Rekeying for Xe3

From: Suraj Kandpal We need to disable HDCP Line Rekeying for Xe3 when we are using an HDMI encoder. v2: add additional definition instead of function, commit message typo fix and update. v3: restore lost conditional from v2. v4: subject line and subject message updated, fix the if ladder order,

[PATCH v2 09/12] drm/i915/xe3: Underrun recovery does not exist post Xe2

From: Ravi Kumar Vodapalli >From platforms xe3 Underrun recovery does not exist v2: improve DISPLAY_VER checking BSpec: 68849 Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- 1 file changed, 1

[PATCH v2 08/12] drm/i915/xe3lpd: Move async flip bit to PLANE_SURF register

From: Dnyaneshwar Bhadane The async flip moved from PLANE_CTL to PLANE_SURF for Xe3_LPD. Bspec: 69853,69878 Signed-off-by: Dnyaneshwar Bhadane Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 13 + .../gpu/drm/i915/di

[PATCH v2 05/12] drm/i915/ptl: Define IS_PANTHERLAKE macro

From: Dnyaneshwar Bhadane Common display code requires IS_PANTHERLAKE macro. Define the macro and set 0 as PTL is no longer support for i915. Signed-off-by: Dnyaneshwar Bhadane Signed-off-by: Matt Atwood Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/i915_drv.h | 1 + 1 file changed, 1 ins

[PATCH v2 00/12] drm/i915/xe3lpd: ptl display patches

This series builds on the previous one, further enabling new features for the platform. 3 patches from the previous series have been brought forward to this series. Clint Taylor (1): drm/i915/cx0: Remove bus reset after every c10 transaction Dnyaneshwar Bhadane (3): drm/i915/ptl: Define IS_P

[PATCH v2 07/12] drm/i915/cx0: Remove bus reset after every c10 transaction

C10 phy timeouts occur on xe3lpd if the c10 bus is reset every transaction. Starting with xe3lpd this is bus reset not necessary Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/

[PATCH topic/core-for-CI 1/2] Revert "HAX suspend: Disable S3/S4 for fi-bdw-samus"

This reverts commit efeb42fe3b7c58abbe674515252cfdb71c09eba5. That machine is not in CI anymore, let's drop the hack. Signed-off-by: Lucas De Marchi --- drivers/acpi/sleep.c | 20 1 file changed, 20 deletions(-) diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c inde

[PATCH topic/core-for-CI 2/2] Revert "HAX sound: Disable probing snd_hda with DG1"

This reverts commit 852510ccd334063bec2c2c3e5a61a071599ac015. This should be solved already since commit e6d0c13e9f46 ("ALSA: hda: i915: Remove extra argument from snd_hdac_i915_init"). We can try to drop it and see if anything explodes on dg1 land. Signed-off-by: Lucas De Marchi --- sound/hda

✗ Fi.CI.BUILD: failure for Introduce drm sharpness property (rev4)

== Series Details == Series: Introduce drm sharpness property (rev4) URL : https://patchwork.freedesktop.org/series/138754/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/138754/revisions/4/mbox/ not applied Applying: drm: Introduce sharpness stre

Re: [core-for-CI] Revert "ICL HACK: usb/icl: Work around ACPI boottime crash"

On Fri, Oct 11, 2024 at 05:49:45PM +0300, Imre Deak wrote: On Fri, Oct 11, 2024 at 03:17:29PM +0300, Jani Nikula wrote: This reverts commit 8d16a118950c ("ICL HACK: usb/icl: Work around ACPI boottime crash"). There shouldn't be any ICL RVP's in CI anymore. Cc: Imre Deak Signed-off-by: Jani Ni

Re: [PATCH v4 3/7] drm/i915/xe3lpd: Disable HDCP Line Rekeying for Xe3

On Fri, Oct 18, 2024 at 01:03:07PM -0700, Matt Atwood wrote: > From: Suraj Kandpal > > We need to disable HDCP Line Rekeying for Xe3 when we are using an HDMI > encoder. This is still missing the "why" for this change. Is there a bspec reference that gives the details? From the description of

Re: [PATCH 11/11] drm/i915/de: remove unnecessary generic wrappers

On Tue, Oct 22, 2024 at 06:57:28PM +0300, Jani Nikula wrote: > With many of the intel_de_* callers switched over to struct > intel_display, we can remove some of the unnecessary generic wrappers. > > Signed-off-by: Jani Nikula trusting more your compiler then my tired eyes, Reviewed-by: Rodrigo

Re: [PATCH] drm/xe/hdcp: Add check to remove hdcp2 compatibility

On Tue, Oct 22, 2024 at 12:59:20PM +0530, Suraj Kandpal wrote: > Add check to remove HDCP2 compatibility from BMG as it does not > have GSC which ends up causing warning when we try to get reference > of GSC FW. Why do you say BMG doesn't have GSC? I don't see anything in the bspec indicating it

Re: [PATCH 10/11] drm/i915/dsi: convert to struct intel_display

On Tue, Oct 22, 2024 at 06:57:27PM +0300, Jani Nikula wrote: > struct intel_display will replace struct drm_i915_private as the main > device pointer for display code. Switch ICL DSI code over to it. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 444 ++

Re: [PATCH 09/11] drm/i915/ips: convert to struct intel_display

On Tue, Oct 22, 2024 at 06:57:26PM +0300, Jani Nikula wrote: > struct intel_display will replace struct drm_i915_private as the main > device pointer for display code. Switch HSW IPS code over to it. > > Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/display

Re: [PATCH 08/11] drm/i915/power: convert assert_chv_phy_status() to struct intel_display

On Tue, Oct 22, 2024 at 06:57:25PM +0300, Jani Nikula wrote: > struct intel_display will replace struct drm_i915_private as the main > device pointer for display code. Switch assert_chv_phy_status() and its > callers to it. Main motivation to do just one function is to stop > passing i915 to intel_

Re: [PATCH 07/11] drm/i915/display: convert vlv_wait_port_ready() to struct intel_display

On Tue, Oct 22, 2024 at 06:57:24PM +0300, Jani Nikula wrote: > struct intel_display will replace struct drm_i915_private as the main > device pointer for display code. Switch vlv_wait_port_ready() over to > it. The main motivation to do just one function is to stop passing i915 > to intel_de_wait()

✗ Fi.CI.BAT: failure for drm/i915/xe2lpd: Update C20 HDMI TMDS algorithm to include tx_misc (rev2)

== Series Details == Series: drm/i915/xe2lpd: Update C20 HDMI TMDS algorithm to include tx_misc (rev2) URL : https://patchwork.freedesktop.org/series/140136/ State : failure == Summary == CI Bug Log - changes from CI_DRM_15586 -> Patchwork_140136v2

[PATCH 0/5] Introduce drm sharpness property

Many a times images are blurred or upscaled content is also not as crisp as original rendered image. Traditional sharpening techniques often apply a uniform level of enhancement across entire image, which sometimes result in over-sharpening of some areas and potential loss of natural detail

Re: [PATCH] drm/i915/rc6: Disable RPG during workload execution

On 23-10-2024 20:18, Rodrigo Vivi wrote: On Wed, Oct 23, 2024 at 11:03:57AM +0530, Nilawar, Badal wrote: On 22-10-2024 22:39, Rodrigo Vivi wrote: On Tue, Oct 22, 2024 at 03:28:43PM +0200, Andi Shyti wrote: Hi Badal, On Tue, Oct 22, 2024 at 06:52:26PM +0530, Badal Nilawar wrote: Encounte

[PATCH 3/5] drm/i915/display: Enable the second scaler for sharpness

As only second scaler can be used for sharpness check if it is available and also check if panel fitting is also not enabled, then set the sharpness. Panel fitting will have the preference over sharpness property. v2: Add the panel fitting check before enabling sharpness v3: Reframe commit message

[PATCH 5/5] drm/i915/display: Load the lut values and enable sharpness

Load the lut values during pipe enable. v2: Add the display version check Signed-off-by: Nemesa Garg --- drivers/gpu/drm/i915/display/intel_crtc.c| 3 +++ drivers/gpu/drm/i915/display/intel_display.c | 6 ++ .../gpu/drm/i915/display/intel_display_types.h | 2 ++ drivers/gpu

Re: [PATCH] drm/i915/rc6: Disable RPG during workload execution

On 23-10-2024 21:31, Nilawar, Badal wrote: On 23-10-2024 20:18, Rodrigo Vivi wrote: On Wed, Oct 23, 2024 at 11:03:57AM +0530, Nilawar, Badal wrote: On 22-10-2024 22:39, Rodrigo Vivi wrote: On Tue, Oct 22, 2024 at 03:28:43PM +0200, Andi Shyti wrote: Hi Badal, On Tue, Oct 22, 2024 at 06

[PATCH 4/5] drm/i915/display: Add registers and compute the strength

Add new registers and related bits. Compute the strength value and tap value based on display mode. v2: Replace i915/dev_priv with display[Jani] v3: Create separate file for defining register[Jani] Add display->drm in debug prints[Jani] v4: Rebase Signed-off-by: Nemesa Garg --- drivers/gpu/

[PATCH 2/5] drm/i915/display: Compute the scaler filter coefficients

The sharpness property requires the use of one of the scaler so need to set the sharpness scaler coefficient values. These values are based on experiments and vary for different tap value/win size. These values are normalized by taking the sum of all values and then dividing each value with a sum.

[PATCH 1/5] drm: Introduce sharpness strength property

Introduces the new crtc property "SHARPNESS_STRENGTH" that allows the user to set the intensity so as to get the sharpness effect. The value of this property can be set from 0-255. It is useful in scenario when the output is blurry and user want to sharpen the pixels. User can increase/decrease the

Re: [PATCH v3 2/8] drm/i915/dp: Ensure panel power remains enabled during connector detection

On Wed, Oct 23, 2024 at 06:19:11PM +0300, Jani Nikula wrote: > On Wed, 16 Oct 2024, Imre Deak wrote: > > The sink's capabilities, like the DSC caps, depend on the source OUI > > written to the sink's DPCD registers and so this OUI value should be > > valid for the whole duration of the detection.

✗ Fi.CI.SPARSE: warning for pmu changes with igt

== Series Details == Series: pmu changes with igt URL : https://patchwork.freedesktop.org/series/140379/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.

Re: [PATCH 8/9] drm/i915/pfit: Extract intel_pfit.c

On Tue, Oct 22, 2024 at 11:31:57AM +0300, Jani Nikula wrote: > On Wed, 16 Oct 2024, Ville Syrjala wrote: > > diff --git a/drivers/gpu/drm/i915/display/intel_pfit.h > > b/drivers/gpu/drm/i915/display/intel_pfit.h > > new file mode 100644 > > index ..add8d78de2c9 > > --- /dev/null > > +

[PATCH v2 1/2] drm/i915/cx0: Pass crtc_state to intel_c20_compute_hdmi_tmds_pll()

The variable crtc_state already contains everything that intel_c20_compute_hdmi_tmds_pll() needs. Simplify the function's signature by passing that struct instead of separate variables. Suggested-by: Jani Nikula Signed-off-by: Gustavo Sousa --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 12

[PATCH v2 2/2] drm/i915/xe2lpd: Update C20 algorithm to include tx_misc

There has been an update to the BSpec in which we need to set tx_misc=0x5 field for C20 TX Context programming for HDMI TMDS for Xe2_LPD and newer. That field is mapped to the bits 7:0 of SRAM_GENERIC__TX_CNTX_CFG_1, which in turn translates to tx[1] of our state struct. Update the algorithm to ref

[PATCH v2 0/2] drm/i915/xe2lpd: Update C20 HDMI TMDS algorithm to include tx_misc

This is v2 of [1] with an extra patch to have intel_c20_compute_hdmi_tmds_pll() using crtc_state to simplify the interface. [1] https://patchwork.freedesktop.org/series/140136/ Gustavo Sousa (2): drm/i915/cx0: Pass crtc_state to intel_c20_compute_hdmi_tmds_pll() drm/i915/xe2lpd: Update C20 al

✗ Fi.CI.CHECKPATCH: warning for pmu changes with igt

== Series Details == Series: pmu changes with igt URL : https://patchwork.freedesktop.org/series/140379/ State : warning == Summary == Error: dim checkpatch failed c76c6233c788 pmu changes -:7: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit descrip

✗ Fi.CI.BAT: failure for pmu changes with igt

== Series Details == Series: pmu changes with igt URL : https://patchwork.freedesktop.org/series/140379/ State : failure == Summary == CI Bug Log - changes from CI_DRM_15585 -> Patchwork_140379v1 Summary --- **FAILURE** Serious un

Re: [PATCH 1/6] PCI/PM: Respect pci_dev->skip_bus_pm in the .poweroff() path

On Wed, Sep 25, 2024 at 02:28:42PM -0500, Bjorn Helgaas wrote: > On Wed, Sep 25, 2024 at 05:45:21PM +0300, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > On some older laptops i915 needs to leave the GPU in > > D0 when hibernating the system, or else the BIOS > > hangs somewhere. Currently

Re: [PATCH v2] drm/i915/display: Fuse bit for power management disable removed

On Fri, Oct 18, 2024 at 12:59:19PM -0700, Clint Taylor wrote: > Starting with Display 13 the fuse bit to disable Display PM has been > removed. > > v2: Bit removed starting with Display13 (MattR) Nitpicks: we should write this out as "display version 13" in the two places above rather than treati

Re: [PATCH v3 2/8] drm/i915/dp: Ensure panel power remains enabled during connector detection

On Wed, 16 Oct 2024, Imre Deak wrote: > The sink's capabilities, like the DSC caps, depend on the source OUI > written to the sink's DPCD registers and so this OUI value should be > valid for the whole duration of the detection. An eDP sink will reset > this OUI value when the panel power is disab

Re: [PATCH v4 10/15] drm/i915/display: add subplatform group for HSW/BDW ULT

On Mon, Oct 21, 2024 at 04:54:11PM +0300, Jani Nikula wrote: > Add support for defining aliases for subplatform groups, such as HSW/BDW > ULT that covers both ULT and ULX. > > ULT is a special case, because we slightly abuse the ULT subplatform > both as a subplatform and group, but with the way t

Re: [PATCH 06/11] drm/i915/crt: convert to struct intel_display

On Tue, Oct 22, 2024 at 06:57:23PM +0300, Jani Nikula wrote: > struct intel_display will replace struct drm_i915_private as the main > device pointer for display code. Switch CRT code over to it. > > Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/display/int

Re: [PATCH 05/11] drm/i915/dp/hdcp: convert to struct intel_display

On Tue, Oct 22, 2024 at 06:57:22PM +0300, Jani Nikula wrote: > struct intel_display will replace struct drm_i915_private as the main > device pointer for display code. Switch DP HDCP code over to it. > > Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/i915/display

[CI] pmu changes

By Peter: git://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git perf/pmu-unregister https://lore.kernel.org/all/20241022215210.ga31...@noisy.programming.kicks-ass.net/ Signed-off-by: Lucas De Marchi --- include/linux/idr.h| 17 + include/linux/perf_event.h | 35 ++- kernel/ev

Re: [PATCH 04/11] drm/i915/hdcp: further conversion to struct intel_display

On Tue, Oct 22, 2024 at 06:57:21PM +0300, Jani Nikula wrote: > There are some unconverted stragglers left in the HDCP API still using > struct drm_i915_private. Convert to struct intel_display. > > Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi > --- > .../drm/i915/display/intel_display

Re: [PATCH 03/11] drm/i915/dpio: convert to struct intel_display

On Tue, Oct 22, 2024 at 06:57:20PM +0300, Jani Nikula wrote: > struct intel_display will replace struct drm_i915_private as the main > device pointer for display code. Switch DPIO PHY code over to it. > > Signed-off-by: Jani Nikula Reviewed-by: Rodrigo Vivi > --- > .../i915/display/intel_disp

Re: [PATCH 02/11] drm/i915/cx0: convert to struct intel_display

On Tue, Oct 22, 2024 at 06:57:19PM +0300, Jani Nikula wrote: > struct intel_display will replace struct drm_i915_private as the main > device pointer for display code. Switch Cx0 PHY code over to it. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 308 ++

Re: [PATCH 01/11] drm/i915/gmbus: convert to struct intel_display

On Tue, Oct 22, 2024 at 06:57:18PM +0300, Jani Nikula wrote: > struct intel_display will replace struct drm_i915_private as the main > device pointer for display code. Switch gmbus code over to it. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_bios.c | 6 +- > d

[PATCH 0/1] pmu changes with igt

Test-with: 20241023042909.3038309-2-lucas.demar...@intel.com Lucas De Marchi (1): pmu changes include/linux/idr.h| 17 + include/linux/perf_event.h | 35 ++- kernel/events/core.c | 620 + 3 files changed, 455 insertions(+), 217 deletions(-)

[PATCH 1/1] pmu changes

By Peter: git://git.kernel.org/pub/scm/linux/kernel/git/peterz/queue.git perf/pmu-unregister https://lore.kernel.org/all/20241022215210.ga31...@noisy.programming.kicks-ass.net/ Signed-off-by: Lucas De Marchi --- include/linux/idr.h| 17 + include/linux/perf_event.h | 35 ++- kernel/ev

Re: [PATCH] drm/i915/rc6: Disable RPG during workload execution

On Wed, Oct 23, 2024 at 11:03:57AM +0530, Nilawar, Badal wrote: > > > On 22-10-2024 22:39, Rodrigo Vivi wrote: > > On Tue, Oct 22, 2024 at 03:28:43PM +0200, Andi Shyti wrote: > > > Hi Badal, > > > > > > On Tue, Oct 22, 2024 at 06:52:26PM +0530, Badal Nilawar wrote: > > > > Encountering forcewake

Re: [PATCH v4 08/15] drm/i915/display: remove the display platform enum as unnecessary

On Wed, Oct 23, 2024 at 04:09:03PM +0300, Jani Nikula wrote: > On Tue, 22 Oct 2024, Rodrigo Vivi wrote: > > On Mon, Oct 21, 2024 at 04:54:09PM +0300, Jani Nikula wrote: > >> @@ -1466,7 +1462,7 @@ find_subplatform_desc(struct pci_dev *pdev, const > >> struct platform_desc *desc) > >>const stru

Re: [PATCH v4 4/8] drm/i915/dp: Track source OUI validity explicitly

On Wed, Oct 23, 2024 at 03:16:11PM +0300, Ville Syrjälä wrote: > On Tue, Oct 22, 2024 at 12:46:23PM +0300, Imre Deak wrote: > > While updating the source OUI on the sink the driver should avoid > > writing the OUI if it's already up-to-date to prevent the sink from > > resetting itself in response

✓ Fi.CI.BAT: success for drm/i915: ensure segment offset never exceeds allowed max

== Series Details == Series: drm/i915: ensure segment offset never exceeds allowed max URL : https://patchwork.freedesktop.org/series/140374/ State : success == Summary == CI Bug Log - changes from CI_DRM_15585 -> Patchwork_140374v1 Summary

Re: [PATCH v3 1/8] drm/i915/dp: Flush modeset commits during connector detection

On Wed, Oct 23, 2024 at 03:15:11PM +0300, Ville Syrjälä wrote: > On Wed, Oct 16, 2024 at 04:23:58PM +0300, Imre Deak wrote: > > Make sure that a DP connector detection doesn't happen in parallel > > with an ongoing modeset on the connector. The reasons for this are: > > > > - Besides reading the c

[PATCH v2] drm/i915: ensure segment offset never exceeds allowed max

Commit 255fc1703e42 ("drm/i915/gem: Calculate object page offset for partial memory mapping") introduced a new offset that affects r.sgt.curr value. This field is used in remap_sg() function, in set_pte_at() call and changing its value causes page table entry to also be affected (see set_ptes() des

Re: [PATCH v4 08/15] drm/i915/display: remove the display platform enum as unnecessary

On Tue, 22 Oct 2024, Rodrigo Vivi wrote: > On Mon, Oct 21, 2024 at 04:54:09PM +0300, Jani Nikula wrote: >> @@ -1466,7 +1462,7 @@ find_subplatform_desc(struct pci_dev *pdev, const >> struct platform_desc *desc) >> const struct subplatform_desc *sp; >> const u16 *id; >> >> -for (sp

Re: [PATCH] drm/i915/active: Use try_cmpxchg() in active_fence_cb()

On Thu, 03 Oct 2024, Uros Bizjak wrote: > Replace this pattern in active_fence_cb(): > > cmpxchg(*ptr, old, new) == old > > ... with the simpler and faster: > > try_cmpxchg(*ptr, &old, new) > > The x86 CMPXCHG instruction returns success in the ZF flag, > so this change saves a compare aft

Re: [PATCH v3 7/8] drm/i915/dp: Write the source OUI during connector detection

On Wed, Oct 16, 2024 at 04:24:04PM +0300, Imre Deak wrote: > The DP sink's capabilities, like DSC, may depend on the source OUI > written to the sink. On eDP this OUI value could have been reset before > the detection started if the panel power on it got disabled. Make sure > the OUI is re-written

Re: [PATCH v3 2/8] drm/i915/dp: Ensure panel power remains enabled during connector detection

On Wed, Oct 16, 2024 at 04:23:59PM +0300, Imre Deak wrote: > The sink's capabilities, like the DSC caps, depend on the source OUI > written to the sink's DPCD registers and so this OUI value should be > valid for the whole duration of the detection. An eDP sink will reset > this OUI value when the

Re: [PATCH v3 3/8] drm/i915/dp: Initialize the source OUI write timestamp always

On Wed, Oct 16, 2024 at 04:24:00PM +0300, Imre Deak wrote: > If the source OUI DPCD register value matches the expected Intel OUI > value, the write timestamp doesn't get updated leaving it at the 0 > initial value if the OUI wasn't written before. This can lead to an > incorrect wait duration in i

Re: [PATCH v3 1/8] drm/i915/dp: Flush modeset commits during connector detection

On Wed, Oct 16, 2024 at 04:23:58PM +0300, Imre Deak wrote: > Make sure that a DP connector detection doesn't happen in parallel > with an ongoing modeset on the connector. The reasons for this are: > > - Besides reading the capabilities, EDID etc. the detection may change > the state of the sink

Re: [PATCH v4 4/8] drm/i915/dp: Track source OUI validity explicitly

On Tue, Oct 22, 2024 at 12:46:23PM +0300, Imre Deak wrote: > While updating the source OUI on the sink the driver should avoid > writing the OUI if it's already up-to-date to prevent the sink from > resetting itself in response to the update. On eDP - the only output > type where the OUI was update

Re: [PATCH v3 6/8] drm/i915/dp: Write the source OUI for eDP before detecting sink capabilities

On Wed, Oct 16, 2024 at 04:24:03PM +0300, Imre Deak wrote: > The eDP sink's capabilities, like DSC, may depend on the source OUI > written to the sink, so ensure the OUI is written before reading out the > capabilities. > > Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä > --- > drivers/g

Re: [PATCH v3 5/8] drm/i915/dp: Reuse intel_dp_detect_dsc_caps() for eDP

On Wed, Oct 16, 2024 at 04:24:02PM +0300, Imre Deak wrote: > Reuse intel_dp_detect_dsc_caps() which already checks for the source's > DSC cap and retrieves the DPCD version from the DPRX caps. > > Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_d

RE: [PATCH] drm/i915: Allow fastset for change in HDR infoframe

> -Original Message- > From: Borah, Chaitanya Kumar > Sent: Wednesday, October 23, 2024 10:11 AM > To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org > Cc: Shankar, Uma ; jani.nik...@linux.intel.com; > ville.syrj...@linux.intel.com > Subject: [PATCH] drm/i915: Allow fas

Re: [PATCH v1] drm/i915/gt: Use ENGINE_TRACE for tracing.

Hi Nitin, On Wed, Oct 23, 2024 at 12:18:29PM +0530, Nitin Gote wrote: > Instead of drm_err(), use ENGINE_TRACE for tracing. Patch looks good, but can you please be a bit more specific in the log why ENGINE_TRACE() is preferrable over drm_err? Thanks, Andi > Signed-off-by: Nitin Gote > --- > .

Re: [PATCH] drm/i915: Use string enable/disable choice helpers

On Wed, 23 Oct 2024, Sai Teja Pottumuttu wrote: > Replace the last few remaining instances of string enable(d)/disable(d) > choices with the linux string choice helpers to avoid further > cocci warnings. > > Signed-off-by: Sai Teja Pottumuttu Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i

Re: [PATCH] drm/i915: Allow fastset for change in HDR infoframe

Hi Caitanya, Can you please use "drm/i915/display: ..." next time? Thanks, Andi On Wed, Oct 23, 2024 at 10:11:22AM +0530, Chaitanya Kumar Borah wrote: > Changes in Dynamic Range and Mastering infoframe > should not trigger a full modeset. Therefore, allow > fastset. DP SDP programming is already

[PULL] drm-intel-gt-next

Hi Dave, Sima, This is the main pull request for 6.13 merge window. PXP GuC auto-teardown feature got enabled, GPU reset robustness improvement for Haswell and basic PMU functionality was enabled for Gen2 platforms. The rest is a handful of small cleanups. Regards, Tvrtko drm-intel-gt-next-

Re: [PATCH] drm/i915/psr: vbt.psr.enable is only for eDP panels

On Mon, 2024-10-21 at 14:10 +0530, Naladala, Ramanaidu wrote: Hi Jouni, On 10/21/2024 1:03 PM, Jouni Högander wrote: We don't want to check vbt.psr.enable on DP Panel Replay as it is targeted for eDP panel usage only. Signed-off-by: Jouni Högander --- dr

RE: [PATCH 02/16] drm/i915/display: Prepare for dsc 3 stream splitter

> -Original Message- > From: Nautiyal, Ankit K > Sent: Wednesday, October 23, 2024 12:23 PM > To: intel-gfx@lists.freedesktop.org > Cc: intel...@lists.freedesktop.org; Kandpal, Suraj > Subject: [PATCH 02/16] drm/i915/display: Prepare for dsc 3 stream splitter > > At the moment dsc_spl

RE: [PATCH 08/16] drm/i915/display: Add macro HAS_PIXEL_REPLICATION

> -Original Message- > From: Nautiyal, Ankit K > Sent: Wednesday, October 23, 2024 12:23 PM > To: intel-gfx@lists.freedesktop.org > Cc: intel...@lists.freedesktop.org; Kandpal, Suraj > Subject: [PATCH 08/16] drm/i915/display: Add macro HAS_PIXEL_REPLICATION > > Add macro for Pixel rep

✓ Fi.CI.BAT: success for drm/i915/gt: Use ENGINE_TRACE for tracing. (rev2)

== Series Details == Series: drm/i915/gt: Use ENGINE_TRACE for tracing. (rev2) URL : https://patchwork.freedesktop.org/series/140358/ State : success == Summary == CI Bug Log - changes from CI_DRM_15582 -> Patchwork_140358v2 Summary ---

RE: [PATCH 07/16] drm/i915/dp: Enable 3 DSC engines for 12 slices

> -Original Message- > From: Nautiyal, Ankit K > Sent: Wednesday, October 23, 2024 12:23 PM > To: intel-gfx@lists.freedesktop.org > Cc: intel...@lists.freedesktop.org; Kandpal, Suraj > Subject: [PATCH 07/16] drm/i915/dp: Enable 3 DSC engines for 12 slices > > Certain resolutions requi

RE: [PATCH 06/16] drm/i915/dp: Ensure hactive is divisible by slice count

> -Original Message- > From: Nautiyal, Ankit K > Sent: Wednesday, October 23, 2024 12:23 PM > To: intel-gfx@lists.freedesktop.org > Cc: intel...@lists.freedesktop.org; Kandpal, Suraj > Subject: [PATCH 06/16] drm/i915/dp: Ensure hactive is divisible by slice count > > According to the

RE: [PATCH 04/16] drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2

> -Original Message- > From: Nautiyal, Ankit K > Sent: Wednesday, October 23, 2024 12:23 PM > To: intel-gfx@lists.freedesktop.org > Cc: intel...@lists.freedesktop.org; Kandpal, Suraj > Subject: [PATCH 04/16] drm/i915/vdsc: Introduce 3rd VDSC engine VDSC2 > > Introduce the register bit

RE: [PATCH v2 4/4] drm/i915/dg2: Implement Wa_14022698537

> -Original Message- > From: Jadav, Raag > Sent: Wednesday, October 23, 2024 12:40 PM > To: Nilawar, Badal > Cc: jani.nik...@linux.intel.com; joonas.lahti...@linux.intel.com; Vivi, > Rodrigo > ; Roper, Matthew D ; > andi.sh...@linux.intel.com; intel-gfx@lists.freedesktop.org; Gupta, A

✗ Fi.CI.CHECKPATCH: warning for Add support for 3 VDSC engines 12 slices (rev5)

== Series Details == Series: Add support for 3 VDSC engines 12 slices (rev5) URL : https://patchwork.freedesktop.org/series/139934/ State : warning == Summary == Error: dim checkpatch failed e10dc647dab1 drm/i915/dp: Update Comment for Valid DSC Slices per Line 9b62b6dbf1b1 drm/i915/display: P

✓ Fi.CI.BAT: success for Add support for 3 VDSC engines 12 slices (rev5)

== Series Details == Series: Add support for 3 VDSC engines 12 slices (rev5) URL : https://patchwork.freedesktop.org/series/139934/ State : success == Summary == CI Bug Log - changes from CI_DRM_15581 -> Patchwork_139934v5 Summary ---

✗ Fi.CI.BAT: failure for drm/i915/gt: Use ENGINE_TRACE for tracing.

== Series Details == Series: drm/i915/gt: Use ENGINE_TRACE for tracing. URL : https://patchwork.freedesktop.org/series/140358/ State : failure == Summary == CI Bug Log - changes from CI_DRM_15581 -> Patchwork_140358v1 Summary --- **F

RE: [PATCH i-g-t] xe: Add test to check pci memory barrier capability

> -Original Message- > From: Kamil Konieczny > Sent: Wednesday, October 9, 2024 11:00 PM > To: igt-...@lists.freedesktop.org > Cc: Upadhyay, Tejas ; intel- > g...@lists.freedesktop.org; Piecielska, Katarzyna > > Subject: Re: [PATCH i-g-t] xe: Add test to check pci memory barrier capabil

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