From: LiaoShihua
Zmmul extension is Multiply only extension for RISC-V.It implements the
multiplication subset of the M extension.
The encodings are identical to those of the corresponding M-extension
instructions.
When You both use M extension add Zmmul extension, it will warning
From: LiaoShihua
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc:
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
* config/riscv/riscv-opts.h (MASK_ZMMUL):
(TARGET_ZMMUL):
* config/riscv/riscv.cc (riscv_option_override):
* config/riscv/ris
From: LiaoShihua
Zmmul extension is Multiply only extension for RISC-V.It implements the
multiplication subset of the M extension.
The encodings are identical to those of the corresponding M-extension
instructions.
When You both use M extension add Zmmul extension, it will warning
From: LiaoShihua
gcc\ChangeLog:
* common/config/riscv/riscv-common.cc: Add zmmul.
* config/riscv/riscv-opts.h (MASK_ZMMUL): New.
(TARGET_ZMMUL): Ditto.
* config/riscv/riscv.cc (riscv_option_override): Prohibit division if
Zmmul is present.
* config/riscv/
From: LiaoShihua
Zmmul extension is Multiply only extension for RISC-V.It implements the
multiplication subset of the M extension.
The encodings are identical to those of the corresponding M-extension
instructions.
LiaoShihua (1):
RISC-V: Support Zmmul extension
gcc/common/config/
From: LiaoShihua
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Zmmul.
* config/riscv/riscv-opts.h (MASK_ZMMUL): New.
(TARGET_ZMMUL): Ditto.
* config/riscv/riscv.cc (riscv_option_override):Ditto.
* config/riscv/riscv.md: Add Zmmul
* conf
OK, I will send another one which remove riscv_scalar_crypto.h and update
testcases with __builtin_riscv_XX
> -原始邮件-
> 发件人: "Kito Cheng"
> 发送时间: 2023-02-16 21:28:34 (星期四)
> 收件人: "Liao Shihua"
> 抄送: gcc-patches@gcc.gnu.org, jia...@iscas.ac.cn, m...@
From: LiaoShihua
The crypto extension have several shorthand extensions that don't consist of
any extra instructions.
Take zk for example, while the extension would imply zkn, zkr, zkt.
The 3 extensions should also combine back into zk to maintain the canonical
order in isa strings.
This patch
From: LiaoShihua
ZTSO is the extension of tatol store order model.
This extension adds no new instructions to the ISA, and you can use it
with arch "ztso".
If you use it, TSO flag will be generate in the ELF header.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
From: LiaoShihua
After commit 591b6e00d1bfe12932ca31530d5859f95db8a35a " riscv: fix
-Wformat-diag errors ", some strings in implement was changed.
This patch update the check info in testcases to sync with it.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/arch-9.c: Update the ch
From: LiaoShihua
ZMMUL extension is Multiply only extension for RISC-V.It implements the
multiplication subset of the M extension.
The encodings are identical to those of the corresponding M-extension
instructions.
When You both use M extension add ZMMUL extension, it will wa
From: LiaoShihua
gcc/ChangeLog:
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):Add __riscv_zks,
__riscv_zk, __riscv_zkn
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-17.c: New test.
---
gcc/config/riscv/riscv-c.cc| 9
gcc/testsuite/gcc.target/r
definitions of intrinsic functions come from
https://github.com/rvkrypto/rvkrypto-fips .
This work is done by Liao Shihua and Wu Siyu.
LiaoShihua (5):
RISC-V:Implement instruction patterns for Crypto extensions
RISC-V:Implement built-in instructions for Crypto extensions
RISC-V:Implement
From: LiaoShihua
gcc/ChangeLog:
* config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2): Defined new
function prototypes.
(RISCV_FTYPE_NAME3): Ditto.
(AVAIL): Defined new riscv_builtin_avail for crypto extension.
(RISCV_ATYPE_SI): Defined new argument type.
..591066fac3b
--- /dev/null
+++ b/gcc/config/riscv/crypto.md
@@ -0,0 +1,383 @@
+;; Machine description for K extension.
+;; Copyright (C) 2022 Free Software Foundation, Inc.
+;; Contributed by SiYu Wu (s...@isrc.iscas.ac.cn) and ShiHua Liao
(shi...@iscas.ac.cn).
+
+;; This file is part of GCC.
+
+;; GCC
From: LiaoShihua
These testcases use intrinsics .
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbkb32.c: New test.
* gcc.target/riscv/zbkb64.c: New test.
* gcc.target/riscv/zbkc32.c: New test.
* gcc.target/riscv/zbkc64.c: New test.
* gcc.target/riscv/z
From: LiaoShihua
These headers are in https://github.com/rvkrypto/rvkrypto-fips .
gcc/ChangeLog:
* config.gcc: Add extra_headers.
* config/riscv/riscv_crypto.h: New file.
* config/riscv/riscv_crypto_scalar.h: New file.
* config/riscv/rvk_asm_intrin.h: New
From: Liaoshihua
---
gcc/common/config/riscv/riscv-common.c | 3 +++
gcc/config/riscv/riscv-c.c | 2 +-
gcc/config/riscv/riscv-opts.h | 3 +++
gcc/config/riscv/riscv.c | 5 -
gcc/config/riscv/riscv.md | 30 +-
gcc/co
From: Liao Shihua
This patch support rv64 insn in ilp32 ABI. It was inspired by aarch64
both
support 64-bit and 32-bit ABI with the same set of instructions.
gcc/ChangeLog:
* config.gcc: Implememt ilp32* with rv64*.
* config/riscv/riscv.cc (riscv_option_override
From: Liao Shihua
patch v1<https://gcc.gnu.org/pipermail/gcc-patches/2022-December/608370.html>
1. use ABI_LEN_SPEC instead of ABI_LEN_SPEC
This patch support rv64 insn in ilp32 ABI. It was inspired by aarch64
both
support 64-bit and 32-bit ABI with the same set of instru
LGTM,and I think it would be better to have a test example.
> From: zengxiao
>
> This patch makes R_RISCV_SUB6 conforms to riscv abi standard.
> R_RISCV_SUB6 only the lower 6 bits of the code are valid.
> The proposed specification which can be found in 8.5. Relocations of,
> https://github.c
From: LiaoShihua
because riscv32 not support __int128, so skip if -march=rv32*.
gcc/testsuite\ChangeLog:
* gcc.target/riscv/pr103302.c: skip if -march=rv32*
---
gcc/testsuite/gcc.target/riscv/pr103302.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/gcc.target
From: LiaoShihua
because riscv32 not support __int128, so skip if int128 not support.
gcc/testsuite\ChangeLog:
* gcc.target/riscv/pr103302.c: skip if int128 not support
---
gcc/testsuite/gcc.target/riscv/pr103302.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
From: LiaoShihua
following 'false' branch in line 20, 'tmp.word_state' leaks in line 26. So
free 'tmp.word_state' before return 'rval'.
gcc/testsuite\ChangeLog:
* gcc.dg/analyzer/pr103526.c:
---
gcc/testsuite/gcc.dg/analyzer/pr103526.c | 3 ++-
1 file changed, 2 insertions(+),
From: LiaoShihua
* gcc.dg/pr102892-2.c: Add definition of function foo() which declared
in pr102892-1.c
---
gcc/testsuite/gcc.dg/pr102892-2.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/pr102892-2.c
b/gcc/testsuite/gcc.dg/pr102892-2.c
index b39bd6c97b3
From: LiaoShihua
When I built riscv-gcc with newlib, it will be terminated with message "fatal
error: endian.h: No such file or directory".
So, fixed it in fast_float.h.
libstdc++-v3\ChangeLog:
* src/c++17/fast_float/fast_float.h (defined):fast_float.h will include
with using newlib
upport bfloat16_t in RISC-V port, but
Zfbf extension's patch will be sent after it released.
Liao Shihua
在 2023/6/1 14:51, Jin Ma 写道:
hi,
Are there any new developments about Zfb? Are there any plans to implement
the Zvfbfmin and Zvfbfwma expansion? I see that Zfb is being reviewed in
llvm, mayb
x86_64/i686/AArch64 has for a few months working std::bfloat16_t
support, __bf16 there is no longer a storage only type, but can
be used for arithmetics and is supported in libgcc and libstdc++.
The patch adds similar support for RISC-V. __bf16 has been merged
in psABI. The c
This patch implement RISC-V Scalar Cryptography extension.
It includes machine descrption , intrinsic and testcase .
Liao Shihua (5):
Add prototypes for RISC-V Crypto built-in functions
Implement ZBKB, ZBKC and ZBKX extensions
Implement ZKND and ZKNE extensions
Implement ZKNH
This patch implement RISC-V Scalar Cryptography extension.
It includes machine descrption , intrinsic and testcase .
Liao Shihua (5):
Add prototypes for RISC-V Crypto built-in functions
Implement ZBKB, ZBKC and ZBKX extensions
Implement ZKND and ZKNE extensions
Implement ZKNH
Implement ZKNH extensions.
ZKNH is NIST Suite: Hash Function Instructions.
gcc/ChangeLog:
* config/riscv/crypto.md (riscv_sha256sig0_):Add ZKNH's
instructions.
(riscv_sha256sig1_): Likewise.
(riscv_sha256sum0_): Likewise.
(riscv_sha256sum1_): Likewise.
Add prototypes for RISC-V Crypto built-in functions .
gcc/ChangeLog:
* config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2): New enumeration
identifier.
(RISCV_FTYPE_NAME3): Likewise.
(RISCV_ATYPE_QI): New Argument types.
(RISCV_ATYPE_HI): Likewise.
(RIS
Implement ZKSH and ZKSED extensions.
ZKSH is ShangMi Suite: SM3 Hash Function Instructions.
ZKSED is ShangMi Suite: SM4 Block Cipher Instructions.
gcc/ChangeLog:
* config/riscv/crypto.md (riscv_sm3p0_): Add ZKSH's and ZKSED's
instructions.
(riscv_sm3p1_): Like
Implement ZKND and ZKNE extensions.
ZKND is NIST Suite: AES Decryption.
ZKNE is NIST Suite: AES Encryption.
gcc/ChangeLog:
* config/riscv/constraints.md (D03): New constraints of bs.
(DsA):New constraints of rnum.
* config/riscv/crypto.md (riscv_aes
Implement ZBKB, ZBKC and ZBKX extensions.
ZBKB is Bitmanip instructions for Cryptography.
ZBKC is Carry-less multiply instructions.
ZBKX is Crossbar permutation instructions.
Only add Machine description and intrinsics of these instructions which are
not defined in the first Bitman
Co-Authored-By: SiYu Wu
---
gcc/config/riscv/riscv-builtins.cc | 8
gcc/config/riscv/riscv-ftypes.def | 10 ++
2 files changed, 18 insertions(+)
diff --git a/gcc/config/riscv/riscv-builtins.cc
b/gcc/config/riscv/riscv-builtins.cc
index 25ca407f9a9..ded91e17554 100644
--- a/gcc
This patch support Zkne and Zknd extension.
It includes instruction's machine description, built-in funtion, and
intrinsics.
gcc/ChangeLog:
* config/riscv/constraints.md (D03): New constraints of bs.
(DsA):New constraints of rnum.
* config/riscv/crypto.md (riscv_aes32ds
This patch support Zksh and Zksed extension.
It includes instruction's machine description, built-in funtion, and
intrinsics.
gcc/ChangeLog:
* config/riscv/crypto.md (riscv_sm3p0_): Add ZKSH's and ZKSED's
instructions.
(riscv_sm3p1_): Likewise.
(riscv_sm4ed_): Likewise
can be found here:
https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0-scalar
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/31
It works by Wu Siyu and Liao Shihua .
Liao Shihua (5):
Add prototypes for RISC-V Crypto built-in functions
Implement ZBKB, ZBKC and ZBKX extensions
This patch support Zknh extension.
It includes instruction's machine description, built-in funtion, and
intrinsics.
gcc/ChangeLog:
* config/riscv/crypto.md (riscv_sha256sig0_):Add ZKNH's
instructions.
(riscv_sha256sig1_): Likewise.
(riscv_sha256sum0_): Likewise.
This patch support Zkbk, Zbkc and Zkbx extension.
It includes instruction's machine description, built-in funtion, and
intrinsics.
It is worth mentioning that this patch only adds instructions in Zbkb but no
longer in Zbb.
If any instructions both in Zbb and Zbkb, they will be generated by code
gcc/ChangeLog:
* config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2): New enumeration
identifier.
(RISCV_FTYPE_NAME3): Likewise.
(RISCV_ATYPE_QI): New Argument types.
(RISCV_ATYPE_HI): Likewise.
(RISCV_FTYPE_ATYPES2): New RISCV_ATYPE.
(RISCV_FTYPE_AT
This patch support Zksh and Zksed extension.
It includes instruction's machine description, built-in funtion, and
intrinsics.
gcc/ChangeLog:
* config/riscv/crypto.md (riscv_sm3p0_): Add ZKSH's and ZKSED's
instructions.
(riscv_sm3p1_): Likewise.
(riscv_sm4ed_): Likewise
can be found here:
https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0-scalar
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/31
It works by Wu Siyu and Liao Shihua .
Liao Shihua (5):
Add prototypes for RISC-V Crypto built-in functions
Implement ZBKB, ZBKC and ZBKX extensions
This patch support Zkne and Zknd extension.
It includes instruction's machine description, built-in funtion, and
intrinsics.
gcc/ChangeLog:
* config/riscv/constraints.md (D03): New constraints of bs.
(DsA):New constraints of rnum.
* config/riscv/crypto.md (riscv_aes32ds
This patch support Zknh extension.
It includes instruction's machine description, built-in funtion, and
intrinsics.
gcc/ChangeLog:
* config/riscv/crypto.md (riscv_sha256sig0_):Add ZKNH's
instructions.
(riscv_sha256sig1_): Likewise.
(riscv_sha256sum0_): Likewise.
This patch support Zkbk, Zbkc and Zkbx extension.
It includes instruction's machine description, built-in funtion, and
intrinsics.
It is worth mentioning that this patch only adds instructions in Zbkb but no
longer in Zbb.
If any instructions both in Zbb and Zbkb, they will be generated by code
/v1.0.0-scalar
It works by Wu Siyu and Liao Shihua .
Liao Shihua (5):
Add prototypes for RISC-V Crypto built-in functions
Implement ZBKB, ZBKC and ZBKX extensions
Implement ZKND and ZKNE extensions
Implement ZKNH extension
Implement ZKSH and ZKSED extensions
gcc/config/riscv/bitmanip.md
This patch supports Zksh and Zksed extension.
It includes instruction's machine description and built-in funtions.
gcc/ChangeLog:
* config/riscv/crypto.md (riscv_sm3p0_): Add ZKSED's and ZKSH's
instructions.
(riscv_sm3p1_):
(riscv_sm4ed_):
(riscv_sm4ks_):
This patch adds prototypes for RISC-V Crypto built-in functions.
gcc/ChangeLog:
* config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2):
(RISCV_FTYPE_NAME3):
(RISCV_ATYPE_QI):
(RISCV_ATYPE_HI):
(RISCV_FTYPE_ATYPES2):
(RISCV_FTYPE_ATYPES3):
* co
This patch supports Zkne and Zknd extension.
It includes instruction's machine description and built-in funtions.
gcc/ChangeLog:
* config/riscv/constraints.md (D03): Add constants of bs and rnum.
(DsA):
* config/riscv/crypto.md (riscv_aes32dsi): Add ZKND's and ZKNE's
in
This patch supports Zkbk, Zbkc and Zkbx extension.
It includes instruction's machine description and built-in funtions.
It is worth mentioning that this patch only adds instructions in Zbkb but no
longer in Zbb.
If any instructions both in Zbb and Zbkb, they will be generated by code
generator
This patch supports Zknh extension.
It includes instruction's machine description and built-in funtions.
gcc/ChangeLog:
* config/riscv/crypto.md (riscv_sha256sig0_): Add ZKNH's
instructions.
(riscv_sha256sig1_):
(riscv_sha256sum0_):
(riscv_sha256sum1_):
According to https://github.com/riscv/riscv-bfloat16 , zfbfmin extension
depends on zfh/zfhmin extension.
According to the discussion
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/367, this use __bf16
and use DF16b in riscv_mangle_type like x86.
gcc\ChangeLog:
* com
This patch support ilp32 on rv64.
It remove option check when -march=rv64* -mabi=ilp32. And replace XLEN_SPEC in
LINK_SPEC by ABI_LEN_SPEC. In addition, it some machine descriptions.
The series kernel support in this link.
https://lore.kernel.org/linux-riscv/20230518131013.3366406-1-guo...@kern
ble?
Oh, I was negligent and will make improvements in the next patch.
Best Regards
Liao Shihua
in and intrinsic.
4. Typo fix.
Update v1 -> v2:
1. Rename *_intrinsic-* to *_intrinsic-XLEN.
2. Typo fix.
3. Intrinsics with immediate arguments will use marcos at O0 .
It's a little patch add just provides a mapping from the RV intrinsics to the
builtin
names within GCC.
The serials patch provides a mapping from the RV intrinsics to the builtin
names.
There are some duplicates testsuites between intrinsic and built-in function.
Remove the Scalar Bitmanip and Scalar Crypto Built-In function testsuites
that will be included in the intrinsic functions.
gcc/testsuite
This patch adds C intrinsics for Scalar Crypto Extension.
gcc/ChangeLog:
* config.gcc: Include riscv_crypto.h.
* config/riscv/riscv_crypto.h: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/scalar_crypto_intrinsic-32.c: New test.
* gcc.target/riscv/scalar_c
This patch adds C intrinsics for Bitmanip Extension.
RISCV_BUILTIN_NO_PREFIX is a new riscv_builtin_description like RISCV_BUILTIN.
But it uses CODE_FOR_##INSN rather than CODE_FOR_riscv_##INSN.
Changed orcb, clmul, brev8 pattern's mode form X to GPR because orcbsi,
clmul_si,
brev8_si are both in
e:
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/622233.html
No problem.
And I would tend to remove the D03 constraint if we used const_0_3_operand.
BR
Liao Shihua
The serials patch provides a mapping from the RV intrinsics to the builtin
names.
There are some duplicates testsuites between intrinsic and built-in function.
Remove the Scalar Bitmanip and Scalar Crypto Built-In function testsuites
that will be included in the intrinsic functions.
gcc/testsuit
s with immediate arguments will use marcos at O0 .
It's a little patch add just provides a mapping from the RV intrinsics to the
builtin
names within GCC.
Liao Shihua (3):
RISC-V: Remove the Scalar Bitmanip and Crypto Built-In function
testsuites
RISC-V: Add C intrinsic for Scalar Crypt
This patch adds C intrinsics for Scalar Crypto Extension.
gcc/ChangeLog:
* config.gcc: Include riscv_crypto.h.
* config/riscv/riscv_crypto.h: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/scalar_crypto_intrinsic-32.c: New test.
* gcc.target/riscv/scalar_c
This patch adds C intrinsics for Bitmanip Extension.
RISCV_BUILTIN_NO_PREFIX is a new riscv_builtin_description like RISCV_BUILTIN.
But it uses CODE_FOR_##INSN rather than CODE_FOR_riscv_##INSN.
Changed orcb, clmul, brev8 pattern's mode form X to GPR because orcbsi,
clmul_si,
brev8_si are both in
It's a little patch add just provides a mapping from the RV intrinsics to the
builtin
names within GCC.
Liao Shihua (2):
Add C intrinsics of Scalar Crypto Extension
Add C intrinsics of Bitmanip Extension
gcc/config.gcc| 2 +-
gcc/config/riscv/
This patch adds C intrinsics for Scalar Crypto Extension.
gcc/ChangeLog:
* config.gcc: Add riscv_crypto.h.
* config/riscv/riscv_crypto.h: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/scalar_crypto_intrinsic-1.c: New test.
* gcc.target/riscv/scalar_cryp
This patch adds C intrinsics for Bitmanip Extension.
RISCV_BUILTIN_NO_PREFIX is a new riscv_builtin_description like RISCV_BUILTIN.
But it uses CODE_FOR_##INSN rather than CODE_FOR_riscv_##INSN.
Some of the instructions are different to spec, see
https://github.com/riscv-non-isa/riscv-c-api-doc/
This patch adds C intrinsics for Scalar Crypto Extension.
gcc/ChangeLog:
* config.gcc: Add riscv_crypto.h.
* config/riscv/riscv_crypto.h: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/scalar_crypto_intrinsic-32.c: New test.
* gcc.target/riscv/scalar_crypt
m the RV intrinsics to the
builtin
names within GCC.
Liao Shihua (2):
Add C intrinsics of Scalar Crypto Extension
Add C intrinsics of Bitmanip Extension
gcc/config.gcc| 2 +-
gcc/config/riscv/riscv-builtins.cc| 22 ++
gcc/config/riscv/riscv-ft
This patch adds C intrinsics for Bitmanip Extension.
RISCV_BUILTIN_NO_PREFIX is a new riscv_builtin_description like RISCV_BUILTIN.
But it uses CODE_FOR_##INSN rather than CODE_FOR_riscv_##INSN.
gcc/ChangeLog:
* config.gcc: Add riscv_bitmanip.h
* config/riscv/riscv-builtins.cc (AV
In Scalar Crypto Built-In functions, some require immediate parameters,
But register_operand are incorrectly used in the pattern.
E.g.:
__builtin_riscv_aes64ks1i(rs1,1)
Before:
li a5,1
aes64ks1i a0,a0,a5
Assembler messages:
Error: instruction aes64ks1i requires
could easier test that?
On Wed, Dec 28, 2022 at 2:25 AM Palmer Dabbelt wrote:
On Tue, 27 Dec 2022 10:24:10 PST (-0800), gcc-patches@gcc.gnu.org wrote:
On 12/12/22 23:49, shi...@iscas.ac.cn wrote:
From: Liao Shihua
This patch support rv64 insn in ilp32 ABI. It was inspired by aarch64
This patch add C intrinsics for scalar crypto extension.
Because of riscv-c-api
(https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44/files) includes
zbkb/zbkc/zbkx's
intrinsics in bit manipulation extension, this patch only support zkn*/zks*'s
intrinsics.
gcc/ChangeLog:
* config.g
在 2023/11/29 23:03, Christoph Müllner 写道:
On Mon, Nov 27, 2023 at 9:36 AM Liao Shihua wrote:
This patch add C intrinsics for scalar crypto extension.
Because of riscv-c-api
(https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44/files) includes
zbkb/zbkc/zbkx's
intrinsics i
Missing boolean_expression TARGET_ZMMUL in riscv_rtx_costs() casuse different
instructions when multiplying an integer with a constant.
( https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1482 )
int foo(int *ib) {
*ib = *ib * 33938;
return 0;
}
rv64im:
lw a4,0(a1)
Update v1->v2
Add testcase for this patch.
Missing boolean_expression TARGET_ZMMUL in riscv_rtx_costs() cause different
instructions when
multiplying an integer with a constant. (
https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1482 )
int foo(int *ib) {
*ib = *ib * 33938;
PR 116150: Zvk* and Zvb* extensions requires v or zve* extension, but
on gcc v is implied.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Removed the zvk extension's
implicit expansion of v extension.
* config/riscv/arch-canonicalize: Ditto.
* config/ris
在 2024/8/6 12:34, Jeff Law 写道:
On 8/5/24 10:23 AM, Patrick O'Neill wrote:
On 8/5/24 01:23, Liao Shihua wrote:
PR 116150: Zvk* and Zvb* extensions requires v or zve*
extension, but on gcc v is implied.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Remove
This patch has been merged in GCC-14 but it needs to be added into GCC-13 as
well.
Missing boolean_expression TARGET_ZMMUL in riscv_rtx_costs() cause different
instructions when
multiplying an integer with a constant. (
https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1482 )
int foo
RISC-V N32 ABI means using 32-bit ABI on 64-bit ISA, the discussion in
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/381 .
At this moment, N32 is supported batemental toolchain.
Three OpenSource RTOS using this feature and have been merged in upstream.
You can see them in
EasyXem (A
Update Sifive Xsfvqmacc and Xsfvfnrclip extension's testcases.
Co-Authored by: Jiawei Chen
Co-Authored by: Yulong Shi
Co-Authored by: Yixuan Chen
gcc/ChangeLog:
* config/riscv/vector.md: Add sf_vqmacc and sf_vfnrclip to has_vtype_op.
gcc/testsuite/ChangeLog:
* gcc.target/ris
The following warning was encountered while building GCC, fix it:
../.././gcc/gcc/config/riscv/bitmanip.md:809:1: warning: source missing a mode?
../.././gcc/gcc/config/riscv/bitmanip.md:809:1: warning: source missing a mode?
gcc/ChangeLog:
* config/riscv/bitmanip.md (*bsetclr_zero_extrac
Update Sifive Xsfvqmacc and Xsfvfnrclip extension's testcases.
Co-Authored by: Jiawei Chen
Co-Authored by: Yulong Shi
Co-Authored by: Yixuan Chen
gcc/ChangeLog:
* config/riscv/vector.md: Add sf_vqmacc and sf_vfnrclip to the
has_vtype_op,ta,ma.
gcc/testsuite/ChangeLog:
* gcc
The pass ext-dce is only activated at O2 and above. Using O2 instead of O1
in testsuites when using -fdump-ext_dce.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/core_list_init.c: Using -O2 instead of -O1.
* gcc.target/riscv/pr111384.c: Ditto.
---
gcc/testsuite/gcc.target/riscv/c
Fix broken testsuite like
"ERROR: gcc.target/riscv/cmo-zicbop-2.c -Os : 1: too many arguments for "
dg-do 1 compile target { { rv32-*-*}} "
gcc/testsuite/ChangeLog:
* gcc.target/riscv/cmo-zicbop-1.c: Fix missing { before target .
* gcc.target/riscv/cmo-zicbop-2.c: Likewise.
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