This patch support Zknh extension.
It includes instruction's machine description, built-in funtion, and
intrinsics.
gcc/ChangeLog:
* config/riscv/crypto.md (riscv_sha256sig0_<mode>):Add ZKNH's
instructions.
(riscv_sha256sig1_<mode>): Likewise.
(riscv_sha256sum0_<mode>): Likewise.
(riscv_sha256sum1_<mode>): Likewise.
(riscv_sha512sig0h): Likewise.
(riscv_sha512sig0l): Likewise.
(riscv_sha512sig1h): Likewise.
(riscv_sha512sig1l): Likewise.
(riscv_sha512sum0r): Likewise.
(riscv_sha512sum1r): Likewise.
(riscv_sha512sig0): Likewise.
(riscv_sha512sig1): Likewise.
(riscv_sha512sum0): Likewise.
(riscv_sha512sum1): Likewise.
* config/riscv/riscv-builtins.cc (AVAIL): Add ZKNH's AVAIL.
* config/riscv/riscv-crypto.def (RISCV_BUILTIN): Add ZKNH's built-in
functions.
(DIRECT_BUILTIN): Likewise.
* config/riscv/riscv_scalar_crypto.h (__riscv_sha256sig0): Add ZKNH's
intrinsics.
(__riscv_sha256sig1): Likewise.
(__riscv_sha256sum0): Likewise.
(__riscv_sha256sum1): Likewise.
(__riscv_sha512sig0h): Likewise.
(__riscv_sha512sig0l): Likewise.
(__riscv_sha512sig1h): Likewise.
(__riscv_sha512sig1l): Likewise.
(__riscv_sha512sum0r): Likewise.
(__riscv_sha512sum1r): Likewise.
(__riscv_sha512sig0): Likewise.
(__riscv_sha512sig1): Likewise.
(__riscv_sha512sum0): Likewise.
(__riscv_sha512sum1): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zknh-sha256.c: New test.
* gcc.target/riscv/zknh-sha512-32.c: New test.
* gcc.target/riscv/zknh-sha512-64.c: New test.
Co-Authored-By: SiYu Wu
---
gcc/config/riscv/crypto.md | 138 ++++++++++++++++++
gcc/config/riscv/riscv-builtins.cc | 2 +
gcc/config/riscv/riscv-crypto.def | 22 +++
gcc/config/riscv/riscv_scalar_crypto.h | 48 ++++++
gcc/testsuite/gcc.target/riscv/zknh-sha256.c | 29 ++++
.../gcc.target/riscv/zknh-sha512-32.c | 43 ++++++
.../gcc.target/riscv/zknh-sha512-64.c | 31 ++++
7 files changed, 313 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index d76a872775f..063a8025f20 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -48,6 +48,22 @@
UNSPEC_AES_ESM
UNSPEC_AES_ESI
UNSPEC_AES_ESMI
+
+ ;; ZKNH unspecs
+ UNSPEC_SHA_256_SIG0
+ UNSPEC_SHA_256_SIG1
+ UNSPEC_SHA_256_SUM0
+ UNSPEC_SHA_256_SUM1
+ UNSPEC_SHA_512_SIG0
+ UNSPEC_SHA_512_SIG0H
+ UNSPEC_SHA_512_SIG0L
+ UNSPEC_SHA_512_SIG1
+ UNSPEC_SHA_512_SIG1H
+ UNSPEC_SHA_512_SIG1L
+ UNSPEC_SHA_512_SUM0
+ UNSPEC_SHA_512_SUM0R
+ UNSPEC_SHA_512_SUM1
+ UNSPEC_SHA_512_SUM1R
])
;; ZBKB extension
@@ -247,3 +263,125 @@
"TARGET_ZKNE && TARGET_64BIT"
"aes64esm\t%0,%1,%2"
[(set_attr "type" "crypto")])
+
+;; ZKNH - SHA256
+
+(define_insn "riscv_sha256sig0_<mode>"
+ [(set (match_operand:X 0 "register_operand" "=r")
+ (unspec:X [(match_operand:X 1 "register_operand" "r")]
+ UNSPEC_SHA_256_SIG0))]
+ "TARGET_ZKNH"
+ "sha256sig0\t%0,%1"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sig1_<mode>"
+ [(set (match_operand:X 0 "register_operand" "=r")
+ (unspec:X [(match_operand:X 1 "register_operand" "r")]
+ UNSPEC_SHA_256_SIG1))]
+ "TARGET_ZKNH"
+ "sha256sig1\t%0,%1"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sum0_<mode>"
+ [(set (match_operand:X 0 "register_operand" "=r")
+ (unspec:X [(match_operand:X 1 "register_operand" "r")]
+ UNSPEC_SHA_256_SUM0))]
+ "TARGET_ZKNH"
+ "sha256sum0\t%0,%1"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sum1_<mode>"
+ [(set (match_operand:X 0 "register_operand" "=r")
+ (unspec:X [(match_operand:X 1 "register_operand" "r")]
+ UNSPEC_SHA_256_SUM1))]
+ "TARGET_ZKNH"
+ "sha256sum1\t%0,%1"
+ [(set_attr "type" "crypto")])
+
+;; ZKNH - SHA512
+
+(define_insn "riscv_sha512sig0h"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")]
+ UNSPEC_SHA_512_SIG0H))]
+ "TARGET_ZKNH && !TARGET_64BIT"
+ "sha512sig0h\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig0l"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")]
+ UNSPEC_SHA_512_SIG0L))]
+ "TARGET_ZKNH && !TARGET_64BIT"
+ "sha512sig0l\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig1h"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")]
+ UNSPEC_SHA_512_SIG1H))]
+ "TARGET_ZKNH && !TARGET_64BIT"
+ "sha512sig1h\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig1l"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")]
+ UNSPEC_SHA_512_SIG1L))]
+ "TARGET_ZKNH && !TARGET_64BIT"
+ "sha512sig1l\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum0r"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")]
+ UNSPEC_SHA_512_SUM0R))]
+ "TARGET_ZKNH && !TARGET_64BIT"
+ "sha512sum0r\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum1r"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")]
+ UNSPEC_SHA_512_SUM1R))]
+ "TARGET_ZKNH && !TARGET_64BIT"
+ "sha512sum1r\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig0"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_SHA_512_SIG0))]
+ "TARGET_ZKNH && TARGET_64BIT"
+ "sha512sig0\t%0,%1"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig1"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_SHA_512_SIG1))]
+ "TARGET_ZKNH && TARGET_64BIT"
+ "sha512sig1\t%0,%1"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum0"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_SHA_512_SUM0))]
+ "TARGET_ZKNH && TARGET_64BIT"
+ "sha512sum0\t%0,%1"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum1"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_SHA_512_SUM1))]
+ "TARGET_ZKNH && TARGET_64BIT"
+ "sha512sum1\t%0,%1"
+ [(set_attr "type" "crypto")])
\ No newline at end of file
diff --git a/gcc/config/riscv/riscv-builtins.cc
b/gcc/config/riscv/riscv-builtins.cc
index b92619f99e4..2a35167e6fb 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -111,6 +111,8 @@ AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT)
AVAIL (crypto_zkne32, TARGET_ZKNE && !TARGET_64BIT)
AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT)
+AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
+AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
AVAIL (always, (!0))
/* Construct a riscv_builtin_description from the given arguments.
diff --git a/gcc/config/riscv/riscv-crypto.def
b/gcc/config/riscv/riscv-crypto.def
index 57d031c2e09..831ab8c0d01 100644
--- a/gcc/config/riscv/riscv-crypto.def
+++ b/gcc/config/riscv/riscv-crypto.def
@@ -58,3 +58,25 @@ DIRECT_BUILTIN (aes32esi, RISCV_SI_FTYPE_SI_SI_SI,
crypto_zkne32),
DIRECT_BUILTIN (aes32esmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32),
DIRECT_BUILTIN (aes64es, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
DIRECT_BUILTIN (aes64esm, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
+
+// ZKNH
+RISCV_BUILTIN (sha256sig0_si, "sha256sig0", RISCV_BUILTIN_DIRECT,
RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sig0_di, "sha256sig0", RISCV_BUILTIN_DIRECT,
RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sig1_si, "sha256sig1", RISCV_BUILTIN_DIRECT,
RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sig1_di, "sha256sig1", RISCV_BUILTIN_DIRECT,
RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sum0_si, "sha256sum0", RISCV_BUILTIN_DIRECT,
RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sum0_di, "sha256sum0", RISCV_BUILTIN_DIRECT,
RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sum1_si, "sha256sum1", RISCV_BUILTIN_DIRECT,
RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sum1_di, "sha256sum1", RISCV_BUILTIN_DIRECT,
RISCV_DI_FTYPE_DI, crypto_zknh64),
+
+DIRECT_BUILTIN (sha512sig0h, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sig0l, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sig1h, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sig1l, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sum0r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sum1r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+
+DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64),
diff --git a/gcc/config/riscv/riscv_scalar_crypto.h
b/gcc/config/riscv/riscv_scalar_crypto.h
index 3418bcf5774..06e73a0169b 100644
--- a/gcc/config/riscv/riscv_scalar_crypto.h
+++ b/gcc/config/riscv/riscv_scalar_crypto.h
@@ -148,3 +148,51 @@ static inline int64_t __riscv_aes64es(int64_t rs1, int64_t
rs2)
static inline int64_t __riscv_aes64esm(int64_t rs1, int64_t rs2)
{ return _RVK_INTRIN_IMPL(aes64esm)(rs1, rs2); } //
AES64ESM
#endif
+
+// === (mapping) Zknh: NIST Suite: Hash Function Instructions
+
+static inline long __riscv_sha256sig0(long rs1)
+ { return _RVK_INTRIN_IMPL(sha256sig0)(rs1); } //
SHA256SIG0
+
+static inline long __riscv_sha256sig1(long rs1)
+ { return _RVK_INTRIN_IMPL(sha256sig1)(rs1); } //
SHA256SIG1
+
+static inline long __riscv_sha256sum0(long rs1)
+ { return _RVK_INTRIN_IMPL(sha256sum0)(rs1); } //
SHA256SUM0
+
+static inline long __riscv_sha256sum1(long rs1)
+ { return _RVK_INTRIN_IMPL(sha256sum1)(rs1); } //
SHA256SUM1
+
+#ifdef RVKINTRIN_RV32
+static inline int32_t __riscv_sha512sig0h(int32_t rs1, int32_t rs2)
+ { return _RVK_INTRIN_IMPL(sha512sig0h)(rs1, rs2); } //
SHA512SIG0H
+
+static inline int32_t __riscv_sha512sig0l(int32_t rs1, int32_t rs2)
+ { return _RVK_INTRIN_IMPL(sha512sig0l)(rs1, rs2); } //
SHA512SIG0L
+
+static inline int32_t __riscv_sha512sig1h(int32_t rs1, int32_t rs2)
+ { return _RVK_INTRIN_IMPL(sha512sig1h)(rs1, rs2); } //
SHA512SIG1H
+
+static inline int32_t __riscv_sha512sig1l(int32_t rs1, int32_t rs2)
+ { return _RVK_INTRIN_IMPL(sha512sig1l)(rs1, rs2); } //
SHA512SIG1L
+
+static inline int32_t __riscv_sha512sum0r(int32_t rs1, int32_t rs2)
+ { return _RVK_INTRIN_IMPL(sha512sum0r)(rs1, rs2); } //
SHA512SUM0R
+
+static inline int32_t __riscv_sha512sum1r(int32_t rs1, int32_t rs2)
+ { return _RVK_INTRIN_IMPL(sha512sum1r)(rs1, rs2); } //
SHA512SUM1R
+#endif
+
+#ifdef RVKINTRIN_RV64
+static inline int64_t __riscv_sha512sig0(int64_t rs1)
+ { return _RVK_INTRIN_IMPL(sha512sig0)(rs1); } //
SHA512SIG0
+
+static inline int64_t __riscv_sha512sig1(int64_t rs1)
+ { return _RVK_INTRIN_IMPL(sha512sig1)(rs1); } //
SHA512SIG1
+
+static inline int64_t __riscv_sha512sum0(int64_t rs1)
+ { return _RVK_INTRIN_IMPL(sha512sum0)(rs1); } //
SHA512SUM0
+
+static inline int64_t __riscv_sha512sum1(int64_t rs1)
+ { return _RVK_INTRIN_IMPL(sha512sum1)(rs1); } //
SHA512SUM1
+#endif
diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha256.c
b/gcc/testsuite/gcc.target/riscv/zknh-sha256.c
new file mode 100644
index 00000000000..88bf01eb279
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknh-sha256.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zknh -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include"riscv_scalar_crypto.h"
+long foo1(long rs1)
+{
+ return __riscv_sha256sig0(rs1);
+}
+
+long foo2(long rs1)
+{
+ return __riscv_sha256sig1(rs1);
+}
+
+long foo3(long rs1)
+{
+ return __riscv_sha256sum0(rs1);
+}
+
+long foo4(long rs1)
+{
+ return __riscv_sha256sum1(rs1);
+}
+
+/* { dg-final { scan-assembler-times "sha256sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum1" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
b/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
new file mode 100644
index 00000000000..dcea6ad1536
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zknh -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include"riscv_scalar_crypto.h"
+
+int32_t foo1(int32_t rs1, int32_t rs2)
+{
+ return __riscv_sha512sig0h(rs1,rs2);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2)
+{
+ return __riscv_sha512sig0l(rs1,rs2);
+}
+
+int32_t foo3(int32_t rs1, int32_t rs2)
+{
+ return __riscv_sha512sig1h(rs1,rs2);
+}
+
+int32_t foo4(int32_t rs1, int32_t rs2)
+{
+ return __riscv_sha512sig1l(rs1,rs2);
+}
+
+int32_t foo5(int32_t rs1, int32_t rs2)
+{
+ return __riscv_sha512sum0r(rs1,rs2);
+}
+
+int32_t foo6(int32_t rs1, int32_t rs2)
+{
+ return __riscv_sha512sum1r(rs1,rs2);
+}
+
+/* { dg-final { scan-assembler-times "sha512sig0h" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig0l" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1h" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1l" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum0r" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum1r" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
b/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
new file mode 100644
index 00000000000..ed87e1e93bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zknh -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include"riscv_scalar_crypto.h"
+
+int64_t foo1(int64_t rs1)
+{
+ return __riscv_sha512sig0(rs1);
+}
+
+int64_t foo2(int64_t rs1)
+{
+ return __riscv_sha512sig1(rs1);
+}
+
+int64_t foo3(int64_t rs1)
+{
+ return __riscv_sha512sum0(rs1);
+}
+
+int64_t foo4(int64_t rs1)
+{
+ return __riscv_sha512sum1(rs1);
+}
+
+
+/* { dg-final { scan-assembler-times "sha512sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum1" 1 } } */
--
2.38.1.windows.1
