Sorry. It should be:
else if (CONST_VECTOR_P (sel)
&& GET_MODE_BITSIZE (GET_MODE_INNER (sel_mode)).to_constant () > 16
&& riscv_get_v_regno_alignment (data_mode) > 1)
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-09-22 09:39
To: Li Xu; gcc-patches
CC: kit
LGTM. You can commit it after you pass the regression.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-09-22 10:37
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH V2] RISC-V: Optimization of vrgather.vv into
vrgatherei16.vv[PR111451]
From: xuli
Consider this
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-22 11:39
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Remove arch and abi option for run test case.
From: Pan Li
Remove the -march and -mabi.
gcc/testsuite/ChangeLog:
* gcc.target
ok
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-22 17:11
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Move ceil test cases to unop folder
From: Pan Li
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/math-ceil-0.c: Moved to
I prefer change expand_vec_copysign into emit_vec_copysign。
Likewise， emit_fabs. ...etc.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-22 19:19
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Refine the code gen for ceil auto vectorization
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-22 20:16
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Refine the code gen for ceil auto vectorization.
From: Pan Li
We vectorized below ceil code already.
void
test_ceil (float *out
floor needs the same floating point const as ceil. */
return gen_ceil_const_fp (inner_mode);
}
So rename it :
gen_ceil_const_fp (machine_mode inner_mode)
into:
get_fp_rounding_coefficient
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-26 10:39
To: gcc-patches
CC: juzhe.zhong; pan2.li
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-26 11:12
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Rename rounding const fp function for refactor
From: Pan Li
The rounding related API shared one const, rename it to avoid
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-26 15:19
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Support FP nearbyint auto-vectorization
From: Pan Li
This patch would like to support auto-vectorization for the
nearbyint API in
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-26 15:24
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP rint auto-vectorization
From: Pan Li
This patch would like to support auto-vectorization for the
rint API in math.h. It
Hi, Richi.
Addresse comments.
One is V2 patch for COND_LEN_ADD reduction:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631340.html
The second one is optimize COND_ADD reduction:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631341.html
juzhe.zh...@rivai.ai
From
Address comments：
V3
COND_LEN_ADD：https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631350.html
V2 COND_ADD:
https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631352.html
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-09-26 17:41
To: Juzhe-Zhong
CC: gcc
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-26 19:00
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP round auto-vectorization
From: Pan Li
This patch would like to support auto-vectorization for the
round API in math.h
_vl (insn->rtl ()) : dem.get_avl ();
+ = (has_vl_op (insn->rtl ()) && REG_P (get_vl (insn->rtl (
+ ? get_vl (insn->rtl ())
+ : dem.get_avl ();
How about:
rtx avl = dem.get_avl_or_vl_reg ();
I wonder whether it is possible add a testcase for this issue ?
juzhe.zh...@riva
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-27 11:28
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP trunc auto-vectorization
From: Pan Li
This patch would like to support auto-vectorization for the
trunc API in math.h
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-27 16:20
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP roundeven auto-vectorization
From: Pan Li
This patch would like to support auto-vectorization for the
roundeven API in
>> Why add `can_create_pseudo_p ()` here? this will split after reload,
>> but we forbid that pattern between reload and split2?
I have no ideal. Some fortran tests just need recognization of mem-to-mem
pattern before RA.
I don't know the reason.
juzhe.zh...@rivai.ai
From
e mov pattern.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-27 18:07
To: juzhe.zh...@rivai.ai
CC: kito.cheng; gcc-patches; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
I can understand why remove mem to mem pattern, but why the norma
LGTM. Thanks for fixing it.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-09-28 09:33
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH v2] RISC-V: Bugfix for RTL check[PR111533]
From: xuli
Consider the flowing situation:
BB5: local_dem(RVV Insn 1, AVL(reg zero))
RVV
Plz add "!flag_trapping_math"
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-28 13:59
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support {U}INT64 to FP16 auto-vectorization
From: Pan Li
This patch would like to suppor
Since middle-end patch is approved, LGTM this patch.
Thanks for improving RVV vectorization.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-25 20:40
To: gcc-patches
CC: juzhe.zhong; kito.cheng; richard.guenther; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add testcases for
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 3/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM
form 3
From: Pan Li
This patch would like to add test cases for the
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 2/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM
form 2
From: Pan Li
This patch would like to add test cases for the
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 4/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM
form 4
From: Pan Li
This patch would like to add test cases for the
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-01 09:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 1/4] RISC-V: Add testcases for unsigned scalar .SAT_ADD IMM
form 1
From: Pan Li
This patch would like to add test cases for the
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-03 13:22
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Fix asm check failure for truncated after SAT_SUB
From: Pan Li
It seems that the asm check is incorrect for truncated after
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-07-03 17:39
To: gcc-patches
CC: rdapp.gcc; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw; Li, Pan2
Subject: [PATCH] RISC-V: Use tu policy for first-element vec_set [PR115725].
Hi,
this patch changes the tail policy for vmv.s.x
ook odd to me. Could you optimize it in a more straightforward way?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-05 09:23
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Implement .SAT_TRUNC for vector unsigned int
From: Pan Li
+ if (double_mode == E_VOIDmode && quad_mode == E_VOIDmode)
Why we have VOID mode ? I still don't understand the codes.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-08 12:48
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v2] RISC
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-08 14:57
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v3] RISC-V: Implement .SAT_TRUNC for vector unsigned int
From: Pan Li
This patch would like to implement the .SAT_TRUNC for the RISC-V
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-07-11 16:29
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add testcases for vector .SAT_SUB in zip benchmark
From: Pan Li
This patch would like to add the test cases for the vector
Thanks for supporting vf/vx transforming.
I'd rather let Robin review this patch.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-07-17 18:55
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc
Subject: [PATCH] RISC-V: More support of vx and vf for autovec compa
RISC-V part LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-05-16 12:05
To: gcc-patches
CC: juzhe.zhong; kito.cheng; tamar.christina; richard.guenther;
Richard.Sandiford; Pan Li
Subject: [PATCH v2 2/3] RISC-V: Implement vectorizable early exit with
vcond_mask_len
From: Pan Li
After
RISC-V part LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-05-16 12:05
To: gcc-patches
CC: juzhe.zhong; kito.cheng; tamar.christina; richard.guenther;
Richard.Sandiford; Pan Li
Subject: [PATCH v2 3/3] RISC-V: Enable vectorizable early exit testsuite
From: Pan Li
After we supported
LGTM.
juzhe.zh...@rivai.ai
CC Robin who knows better than me in case of scheduling model in RISC-V
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2024-05-20 15:59
To: gcc-patches
CC: kito.cheng; palmer; tamar.christina; richard.guenther; Richard.Sandiford;
juzhe.zhong; zhengyu; pan2.li; xuli
Subject: [PATCH] RISC-V: Enable
some one backport them to GCC-14 ?
Thanks.
juzhe.zh...@rivai.ai
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-03 11:09
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1 1/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 1
From: Pan Li
After the middle-end support the form 1 of unsigned SAT_ADD and
the RISC
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-03 11:09
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1 2/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 2
From: Pan Li
After the middle-end support the form 2 of unsigned SAT_ADD and
the RISC
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-03 11:09
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1 3/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 3
From: Pan Li
After the middle-end support the form 3 of unsigned SAT_ADD and
the RISC
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-03 11:09
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1 4/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 4
From: Pan Li
After the middle-end support the form 4 of unsigned SAT_ADD and
the RISC
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-03 11:09
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1 5/5] RISC-V: Add testcases for scalar unsigned SAT_ADD form 5
From: Pan Li
After the middle-end support the form 5 of unsigned SAT_ADD and
the RISC
)(V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) &&
TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-08-27 22:02
To: gcc-patches
CC: pal...@dabbelt.com; kito.ch...@gmail.com; juzhe.zh...@rivai.ai;
jeffreya...@gmail.c
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-13 16:26
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix vec_extract vls mode iterator restriction
mismatch
From: Pan Li
We have vec_extract pattern which takes ZVFHMIN as
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3
From: Pan Li
After the middle-end support the form 3 of unsigned
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 3/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 5
From: Pan Li
After the middle-end support the form 5 of unsigned
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 7/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 9
From: Pan Li
After the middle-end support the form 9 of unsigned
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 4/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 6
From: Pan Li
After the middle-end support the form 6 of unsigned
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 5/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 7
From: Pan Li
After the middle-end support the form 7 of unsigned
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 2/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 4
From: Pan Li
After the middle-end support the form 4 of unsigned
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 6/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 8
From: Pan Li
After the middle-end support the form 8 of unsigned
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 8/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form
10
From: Pan Li
After the middle-end support the form 10 of unsigned
LGTM
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-06-21 09:54
To: gcc-patches
CC: kito.cheng; juzhe.zhong; jinma.contrib; Feng Wang
Subject: [PATCH 1/3] RISC-V: Add vector type of BFloat16 format
The vector type of BFloat16 format is added in this patch,
subsequent extensions to zvfbfmin
;
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2024-06-21 09:54
To: gcc-patches
CC: kito.cheng; juzhe.zhong; jinma.contrib; Feng Wang
Subject: [PATCH 2/3] RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic
Accroding to the intrinsic doc, the 'Zvfbfmin' and 'Zvfbfwma' intrinsic
functions are
I see, it's operator== overloaded.
LGTM.
juzhe.zh...@rivai.ai
From: wangf...@eswincomputing.com
Date: 2024-06-21 17:03
To: juzhe.zhong; gcc-patches
CC: kito.cheng; jinma.contrib
Subject: Re: Re: [PATCH 2/3] RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic
On 2024-06-21 12:24 juzhe.zhong
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-12 14:08
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix ICE non-vector in
TARGET_FUNCTION_VALUE_REGNO_P
From: Pan Li
This patch would like to fix one ICE when vector is not enabled
in hook
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-20 09:04
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for wv insn register overlap
From: Pan Li
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr112431-42.c: New
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-22 11:19
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for widening register overlap
of vf4/vf8
From: Pan Li
We reverted below patch for register group overlap, add the
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-22 14:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for highest-number regno
ternary overlap
From: Pan Li
We reverted below patch for register group overlap, add the
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-22 15:43
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v2] RISC-V: Add xfail test case for indexed load overlap with
SRC EEW < DEST EEW
From: Pan Li
Update in v2:
* Add change log to pr112431-3
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-22 16:27
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for highpart overlap
floating-point widen insn
From: Pan Li
We reverted below patch for register group overlap, add
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-24 10:48
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for highpart overlap of vext.vf
From: Pan Li
We reverted below patch for register group overlap, add the related
lgtm.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-04-24 18:09
To: gcc-patches; kito.cheng; rdapp; juzhe.zhong
CC: Kito Cheng
Subject: [PATCH][GCC 13] RISC-V: Fix recursive vsetvli checking [PR114172]
extract_single_source will recursive checking the sources to
make sure if it's s
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-25 09:25
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
From: Pan Li
We missed the existing early clobber for the dest operand of vwsll
pattern when
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-25 09:25
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add xfail test case for highpart register overlap
of vwcvt
From: Pan Li
We reverted below patch for register group overlap, add the
LGTM. THANKS
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-25 17:25
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li; Kito Cheng
Subject: [PATCH v1] RISC-V: Add test cases for insn does not satisfy its
constraints [PR114714]
From: Pan Li
We have one ICE when RVV register
LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-04-25 19:23
To: gcc-patches
CC: rdapp.gcc; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw; Patrick
O'Neill
Subject: [PATCH] RISC-V: Add testcase for PR114749.
Hi,
this adds a test case for PR114749.
Going to commit as ob
LGTM from my side. But give kito more time chime in.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-28 11:53
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Fix ICE for legitimize move on subreg
const_poly_move
From: Pan Li
When we build with isl, there
Hi, Han.
GCC 14 is branch out. You can commit it to trunk (GCC 15).
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-04-02 16:30
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc
Subject: [PATCH v2] RISC-V: Refine the condition for add additional vars in RVV
cost
LGTM。
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2024-05-07 09:17
To: gcc-patches; kito.cheng; palmer; jeffreyalaw; rdapp; juzhe.zhong; pan2.li
CC: Kito Cheng
Subject: [PATCH][GCC 13] RISC-V: Fix vsetvli local eliminate [PR114747]
vsetvli local eliminate is only consider the current demand
lgtm
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-05-09 11:05
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Make full-vec-move1.c test robust for optimization
From: Pan Li
During investigate the support of early break autovec, we notice
the test full-vec
LGTM from my side. Wait for kito chime in.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-05-11 15:54
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar
From: Pan Li
For the vfw vx format RVV intrinsic, the
I think you'd better change assembler checking of "spill-*.c" cases.
Check they don't have "addi sp,sp,0" redundant instruction.
Let's see whether Kito aggree with that.
juzhe.zh...@rivai.ai
From: jiawei
Date: 2022-11-15 10:37
To: Kito Cheng
CC: gcc-patch
LGTM. Thanks for fixing my mistake.
Let's see whether other RISC-V folks are happy with this patch.
juzhe.zh...@rivai.ai
From: jiawei
Date: 2022-11-15 16:33
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; jeffreyalaw; christoph.muellner;
philipp.tomsich; wuwei2016; jiawei
Su
I s0) then file
assertion in RTL_SSA.
Instead, we should not eliminate "s0" dependency.
Thanks
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-19 08:56
To: Kito Cheng; juzhe.zhong; Richard Biener
CC: gcc-patches; palmer
Subject: Re: [PATCH] RISC-V: Fix bug reported by PR109535
On
you mind giving me more suggestions?
Thanks
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-19 09:11
To: juzhe.zh...@rivai.ai; kito.cheng; Richard Biener
CC: gcc-patches; palmer
Subject: Re: [PATCH] RISC-V: Fix bug reported by PR109535
On 4/18/23 19:04, juzhe.zh...@rivai.ai wrote:
>
can see "vl" operand only serves as "avl" which is used already
in vsetvli instructions before, so this operand is not used anymore in
"vadd.vx" instruction,
I removed this operand and dependency.
Feel free to give me more comments. Thanks.
juzhe.zh...@rivai.ai
From: Jef
).
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-04-19 17:34
To: Li, Pan2
CC: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang,
Yanzhang
Subject: Re: [PATCH] RISC-V: Allow VMS{Compare} (V1, V1) shortcut optimization
Hi Pan:
>rtx expand (function_expander
Thanks Jeff.
Address Jeff's comment and resend fix patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616170.html
This patch also added a testcase coming from Kito (Kito reduced google/highway
testcase from over 10W lines codes into 100 lines codes!!!).
juzhe.zh...@rivai.ai
imple len_load/len_store.
I have sent the patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616223.html to initial
basic auto-vectorization.
juzhe.zh...@rivai.ai
From: Michael Collison
Date: 2023-04-18 02:36
To: gcc-patches
Subject: [PATCH v4 04/10] RISC-V:autovec: Add target
ook at "preferred_simd_mode" function.
And also, I have a bunch of -march combinations of testcase, make sure compiler
will not auto-vectorize the codes
if we don't want it:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616224.html
juzhe.zh...@rivai.ai
From: Michael Coll
olicy = get_tail_policy_no_pred();
+ rtx mask = CONSTM1_RTX(mode);
+ rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX);
These operands preparation codes should be added into a wrapper.
How to add a wrapper, you can reference "emit_nonvlmax_op" , "emit_pred_op"...
functions.
Thanks.
ju
cc/testsuite/gcc.target/riscv/rvv/base/spill-10.c":28:1
>>727 {*movvnx8qi_whole}
>>(nil))
Oh, I see. According to your situation, the LMUL = 1 is 128bit. VNx8QImode is
MF2 which is 64bit size.
GCC tie VNx8QI into a scalar register. I think it can be easily fixed in the
ba
Thanks Richard reminding me. I originally think community does not allow me
support variable amount IV and let me do this in RISC-V backend.
It seems that I can do that in middle-end. Thank you so much. I will update the
patch. Really appreciate it!
juzhe.zh...@rivai.ai
From: Richard
-vector-bits-, However, it was objected by LLVM
community.
https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/33
I think in case of compile options, Kito may give more comments since he is the
RISC-V ABI and convention maintainer.
I develop this patch following his order.
date patch.
Is that right? Feel free to correct me.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-04-20 17:11
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther; jeffreyalaw
Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
ot;WHILE_LEN" pattern.
Overall the global reviewers accept our RVV loop control mechanism in
middle-end,
I am going to support RVV loop control mechanism in middle-end first. Then, we
can
have perfect codegen like RVV ISA example soon.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date:
Ahhh. Thanks kito.
Can you give more comments about Robin's opinion that he want to change into
"fixed" vs "varying" or "fixed vector size" vs "dynamic vector size" ?
I am Ok with any of them.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-0
L = 1/2/4/8 auto-vectorization (You can see the codes in rvv.exp).
Then, he let me add --param options.
I can change compile option as you suggested.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-04-20 17:42
To: juzhe.zh...@rivai.ai; kito.cheng
CC: gcc-patches; palmer; jeffreyalaw
Subje
function.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-04-20 17:54
To: Richard Biener
CC: juzhe.zhong\@rivai.ai; gcc-patches; jeffreyalaw
Subject: Re: [PATCH] VECT: Add WHILE_LEN pattern for decrement IV support for
auto-vectorization
Richard Biener writes:
> On Thu, 20 Apr 20
LGTM。
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-04-21 14:49
To: gcc-patches
CC: Juzhe-Zhong
Subject: [committed v2] RISC-V: Add local user vsetvl instruction elimination
[PR109547]
From: Juzhe-Zhong
This patch is to enhance optimization for auto-vectorization.
Before this patch
.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-22 04:36
To: juzhe.zhong; gcc-patches
CC: kito.cheng
Subject: Re: [PATCH] RISC-V: Fine tune gather load RA constraint
On 3/13/23 02:28, juzhe.zh...@rivai.ai wrote:
> From: Ju-Zhe Zhong
>
> For DEST EEW < SOURCE EEW, we can par
I can push codes yet. Can you push them for me?
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-22 04:42
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer
Subject: Re: [PATCH] RISC-V: Fix redundant vmv1r.v instruction in vmsge.vx
codegen
On 3/22/23 06:15, juzhe.zh...@rivai.ai wrote
LMUL = 1/2/4/8 so far.
Then we can support the feature of picking LMUL during auto-vectorization in
the future when we figure out how to do that.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-04-25 14:00
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer
Subject: Re: [PATCH] RISC-V: Ad
o all callers would need to be updated,
>>but IMO that's OK. Not sure what others think though.
>>The patch doesn't seem to change vect_estimate_min_profitable_iters though,
>>so the comment doesn't seem accurate.
Address all comments and fix patch V3:
https://gcc
11_31 = VEC_PACK_TRUNC_EXPR ;
vect__7.11_32 = VEC_PACK_TRUNC_EXPR ;
vect__7.10_33 = VEC_PACK_TRUNC_EXPR ;
...
.LEN_STORE (_13, 16B, X, vect__7.10_33); (INT16)
Is this correct ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-04-26 16:06
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenthe
gc->controls.is_empty ()
&& vect_maybe_permute_loop_masks (&header_seq, rgc, half_rgc))
continue;
}
Is that correct?
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-04-26 16:55
To: richard.sandiford
CC: gcc-patches; rguenther
Subject: Re: Re: [PATCH] VECT: Add decrement IV
ctrl;
}
return index_after_incr;
}
Am I understand correctly ? I think I may need to implement VEC_PACK_TRUNC to
test your idea.
Thanks
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-04-26 17:06
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATCH] VECT
atch more? Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-04-29 00:10
To: gcc-patches; Kito Cheng; Kito.cheng; palmer; juzhe.zh...@rivai.ai; Michael
Collison; jeffreyalaw
Subject: [PATCH] riscv: Allow vector constants in riscv_const_insns.
Hi,
I figured I'm going to start sendin
vluxei32.v v1,(0),v1 is not correct assembly.
Instead, it should be vluxei32.v v1,(zero),v1
You should change the assembly print: (%1) --> (%z1)
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-05-04 16:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subj
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