LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 7/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 9
From: Pan Li <pan2...@intel.com>
After the middle-end support the form 9 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 9 of unsigned .SAT_SUB.
Form 9:
#define SAT_SUB_U_9(T) \
T sat_sub_u_9_##T (T x, T y) \
{ \
T ret; \
T overflow = __builtin_sub_overflow (x, y, &ret); \
return overflow ? 0 : ret; \
}
Passed the rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-33.c: New test.
* gcc.target/riscv/sat_u_sub-34.c: New test.
* gcc.target/riscv/sat_u_sub-35.c: New test.
* gcc.target/riscv/sat_u_sub-36.c: New test.
* gcc.target/riscv/sat_u_sub-run-33.c: New test.
* gcc.target/riscv/sat_u_sub-run-34.c: New test.
* gcc.target/riscv/sat_u_sub-run-35.c: New test.
* gcc.target/riscv/sat_u_sub-run-36.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h | 10 ++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-36.c | 17 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-33.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-34.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-35.c | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-36.c | 25 +++++++++++++++++++
9 files changed, 182 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-36.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-33.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-34.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-35.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-36.c
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 9f901de5cdf..ecb74e56e9c 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -138,6 +138,15 @@ sat_u_sub_##T##_fmt_8 (T x, T y) \
return ret & (T)-(!overflow); \
}
+#define DEF_SAT_U_SUB_FMT_9(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_9 (T x, T y) \
+{ \
+ T ret; \
+ T overflow = __builtin_sub_overflow (x, y, &ret); \
+ return overflow ? 0 : ret; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -146,6 +155,7 @@ sat_u_sub_##T##_fmt_8 (T x, T y) \
#define RUN_SAT_U_SUB_FMT_6(T, x, y) sat_u_sub_##T##_fmt_6(x, y)
#define RUN_SAT_U_SUB_FMT_7(T, x, y) sat_u_sub_##T##_fmt_7(x, y)
#define RUN_SAT_U_SUB_FMT_8(T, x, y) sat_u_sub_##T##_fmt_8(x, y)
+#define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c
new file mode 100644
index 00000000000..aca4bd28b5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-33.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_9:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_9(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c
new file mode 100644
index 00000000000..f87a51a504b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-34.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_9:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_9(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c
new file mode 100644
index 00000000000..13c3e922f14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-35.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_9:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_9(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-36.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-36.c
new file mode 100644
index 00000000000..0254f539e09
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-36.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
-fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_9:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_9(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-33.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-33.c
new file mode 100644
index 00000000000..ab8b4750d01
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-33.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_9
+
+DEF_SAT_U_SUB_FMT_9(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-34.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-34.c
new file mode 100644
index 00000000000..66a82f20ca5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-34.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_9
+
+DEF_SAT_U_SUB_FMT_9(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-35.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-35.c
new file mode 100644
index 00000000000..a54b5c33bc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-35.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_9
+
+DEF_SAT_U_SUB_FMT_9(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-36.c
b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-36.c
new file mode 100644
index 00000000000..97943b3e3b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-36.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_9
+
+DEF_SAT_U_SUB_FMT_9(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"
--
2.34.1
