Hi, this patch is very interesting patch and I found it's very beneficial after
applying to my downstream RVV GCC.
However, it has been a long time that this patch didn't update.
Is it possible that this patch will be refined and merged into trunk in the
future ?
Thanks
juzhe.zh...@rivai.ai
default behavior in case of alignment which is already in this patch
should not be changed in the future.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-15 16:02
To: Robin Dapp
CC: juzhe.zh...@rivai.ai; gcc-patches; palmer; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Support
Address comments.
Thanks.
juzhe.zh...@rivai.ai
From: Philipp Tomsich
Date: 2023-05-15 16:21
To: juzhe.zhong
CC: gcc-patches; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Add rounding mode operand for fixed-point patterns
On Mon, 15 May 2023 at 10
I think it is the issue of include file.
Kito may know the better the solution instead of changing stdint.h into
stdint-gcc.h.
Thanks.
juzhe.zh...@rivai.ai
From: Andreas Schwab
Date: 2023-05-15 17:10
To: Robin Dapp via Gcc-patches
CC: juzhe.zh...@rivai.ai; Kito Cheng; Michael Collison
Address comments.
juzhe.zh...@rivai.ai
From: Bernhard Reutner-Fischer
Date: 2023-05-15 17:22
To: juzhe.zh...@rivai.ai; philipp.tomsich
CC: gcc-patches; kito.cheng; Kito.cheng; palmer; palmer; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH] RISC-V: Add rounding mode operand for fixed-point
No, ARM SVE is 128bit alignment instead of element align (in aarch64-modes.def).
If you want to tune the alignment, you should add tunning info into
riscv-modes.def
instead of this target hook.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-15 16:58
To: juzhe.zh...@rivai.ai
Ping。
Is it Ok for trunk ? I have double checked the floating-point instructions
needed FRM.
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-15 22:53
To: gcc-patches
CC: kito.cheng; palmer; rdapp.gcc; jeffreyalaw; Juzhe-Zhong
Subject: [PATCH V2] RISC-V: Add FRM and rounding
nu.org/pipermail/gcc-patches/2023-May/618638.html
which has fixed the comments as you suggested.
Besides, we will going to add more patterns has length included:
len_mask_load/len_mask_stores, len_mask_gather_load/ len_cond...etc
They are all undefine behavior for length larger than the vector length
between [a4/2, vf] depending
on the hardward design.
Since our current data reference pointer IV is added by VF (in bytes) by
default.
Then it will be an issue.
So, may be for case 2 like your said, we should not involve undefine behavior
into len_load/len_store,
instead, we should well ha
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-16 14:57
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer
"juzhe.zh...@rivai.ai" writes:
>>> The examples are good, but this one made
_44; ->remove
+ ...
+ if (ivtmp_46 != 0)
+ goto ; [83.33%]
+ else
+ goto ; [16.67%]
Is it reasonable ? Or you do have better idea for it?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-16 14:57
patch?
Since I am gonna to put them in RISC-V backend testsuite, I was planning to
post them after this patch is finished and merged into trunk.
What do you suggest ?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-16 16:16
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rgue
Also, I have append my testcases too in this patch too.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-16 16:30
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer
"juzhe.zh...@rivai.ai"
tch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618724.html
I think this patch is the reasonable patch now!
Could you take a look at it?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-16 16:30
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATC
understanding than before.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-16 16:30
To: juzhe.zhong\@rivai.ai
CC: gcc-patches; rguenther
Subject: Re: [PATCH V7] VECT: Add decrement IV support in Loop Vectorizer
"juzhe.zh...@rivai.ai" writes:
> Hi, Richard.
>
> RVV inf
nment does not set up simulator (QEMU
or SPIKE or GEM5) correctly.
For example, did not enable vector extension in simulator, I don't you may try.
Thanks.
juzhe.zh...@rivai.ai
Oh, I see. Kito has add /* { dg-do run { target { riscv_vector } } } */
But not all RVV tests has use this and I not sure whether it can work.
I think Kito can answer it.
If yes, I think we should add all of them.
Thanks.
juzhe.zh...@rivai.ai
From: Andrew Pinski
Date: 2023-05-17 10:02
To
n to generate a mask.
>> nit: builder.inner_mode () rather than GET_MODE_INNER (dup_mode)?
They are the same. I can change it using GET_MODE_INNER
>> And I would like have more commnet to explain why we need force_reg here.
Since it will creat ICE.
juzhe.zh...@rivai.ai
From: Kito
n elements rather than bytes.
>> So I think the above part of the patch should go in ahead of the IV changes.
>> But the test should be based on factor rather than
>> TYPE_VECTOR_SUBPARTS.Since the length control measured by bytes instead of
>> bytes is not appropriate for
abandoned and need to rewrite the whole thing.
Would you mind giving me more information?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-19 18:23
To: juzhe.zhong
CC: gcc-patches; rguenther
Subject: Re: [PATCH V11] VECT: Add decrement IV support in Loop Vectorizer
Thanks for
Hi, Richard and Richi.
This patch bootstrap PASS on X86 and regression no surprise change.
Ok for trunk ?
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-22 10:08
To: gcc-patches
CC: richard.sandiford; rguenther; pan2.li; Ju-Zhe Zhong
Subject: [PATCH V12] VECT: Fix issue of
27;s pushed,
>> could you post the updated decrementing IV patch?
Sure, I am working on it.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-22 16:00
To: juzhe.zhong
CC: gcc-patches; rguenther; pan2.li
Subject: Re: [PATCH V12] VECT: Fix issue of multiple-rgroup for length is
counting
Hi, Richard.
I have rebase to trunk and send the updated patch for "decrement IV support":
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619115.html
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-22 16:00
To: juzhe.zhong
CC: gcc-patches; rguenther; pan2.
Thanks Robin. Address comment.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-22 16:07
To: juzhe.zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; palmer; jeffreyalaw; Richard Sandiford
Subject: Re: [PATCH] RISC-V: Add RVV comparison autovectorization
Hi Juzhe,
thanks. Some remarks inline
Yeah, I agree wit kito.
For example, I see you have rename "get_prefer_***" into "get_preferred_**"
I think this NFC patch should be separated patch.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-22 17:05
To: Robin Dapp
CC: 钟居哲; gcc-patches; palmer; Michae
ue for RVV).
So you could image I will post more middle-end patches for RVV
auto-vectorization in the future.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-22 18:12
To: Richard Sandiford; juzhe.zh...@rivai.ai; gcc-patches; rguenther
Subject: Re: [PATCH V11] VECT: Add decreme
framework suitable for all of them to simplify the
future work.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-22 20:14
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; Kito.cheng; palmer; jeffreyalaw; richard.sandiford
Subject: Re: [PATCH] RISC-V: Add RVV comparison
...@rivai.ai
From: Robin Dapp
Date: 2023-05-22 20:26
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; Kito.cheng; palmer; jeffreyalaw; richard.sandiford
Subject: Re: [PATCH] RISC-V: Add RVV comparison autovectorization
> I do refactoring since we are going to have many different
> auto-vectori
many places and I personally prefer this way since
it will make codes much cleaner.
I dislike the way making the function argument with multiple operand ,like this:
void func(rtx dest, rtx src1, rtx src2, )
If we are doing this, we will need to add helpers forever...
Sending V2 patch soon
s" looks codes much cleaner.
Hi, kito. Could you take a look at the V2 refactor patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619291.html
This is important for us since we can't post more autovec patches without
refactor patch.
Thanks
juzhe.zh...@rivai.ai
From: Kit
Oh， Thanks.
Let's wait for Kito's final approved.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-23 17:44
To: juzhe.zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw
Subject: Re: [PATCH V2] RISC-V: Refactor the framework of RVV auto-vector
Bootstrap on X86 passed.
Ok for trunk?
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-22 16:38
To: gcc-patches
CC: richard.sandiford; rguenther; Ju-Zhe Zhong
Subject: [PATCH V12] VECT: Add decrement IV iteration loop control by variable
amount support
From: Ju-Zhe Zhong
gcc
Ok. Let's wait for Kito's more comments.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-24 05:07
To: 钟居哲; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; Jeff Law;
richard.sandiford
Subject: Re: [PATCH V2] RISC-V: Add RVV comparison autovectorization
Yeah. Can I merge it?
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2023-05-24 09:32
To: juzhe.zhong
CC: gcc-patches; Kito Cheng; kito.cheng; jeffreyalaw; rdapp.gcc; juzhe.zhong
Subject: Re: [PATCH V2] RISC-V: Fix magic number of RVV auto-vectorization
expander
On Tue, 23 May 2023 18:28:48
Yes, I built it and regression has passed.
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2023-05-24 09:37
To: juzhe.zhong
CC: gcc-patches; Kito Cheng; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: Re: [PATCH V2] RISC-V: Fix magic number of RVV auto-vectorization
expander
On Tue, 23 May
I always finished build up && regression testsuite before I posted the patches.
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-05-24 09:37
To: palmer
CC: gcc-patches; kito.cheng; Kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V2] RISC-V: Fix magic number of
Thanks. I fix it by separating VL and normal operand.
V2 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619356.html
Does it look more reasonable to you?
Just finished the building test && regression.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-24
if (cond[i])
a[i] = b[i]
We need len_mask_load/len_mask_store for such code and I am gonna support them
in the middle-end after this patch is merged.
Both integer && floating (order and unorder) are tested.
built && regression passed.
Ok for trunk?
Thanks.
juzhe.zh...@riva
Thanks a lot. Part of the comments has already been fixed in V4.
But forget about V4 patch.
Could you continue review V5 patch that I just send ?
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619366.html
with all comments from you have been fixed.
Thanks.
juzhe.zh...@rivai.ai
From
Thanks kito.，
change it into define_insn_and_split send V2 soon.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-24 15:18
To: juzhe.zhong
CC: gcc-patches; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH] RISC-V: Add RVV mask logic auto-vectorization
Just one comment
>
> From: Juzhe-Zhong
>
> This patch is adding mask logic auto-vectorization.
> define the pattern as "define_insn_and_split" to allow
>don't forgot to update here ^
I notice I missed changeLog here. Is that you want me to fix in the
commit log?
juzhe.
egen.
Could you take a look at it:
V15 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619534.html
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-05-25 04:05
To: 钟居哲
CC: gcc-patches; rguenther
Subject: Re: [PATCH V14] VECT: Add decrement IV iteration loop control by
variab
is a vector bool mode. */
+#define VECTOR_BOOL_MODE_P(MODE) \
+ (GET_MODE_CLASS (MODE) == MODE_VECTOR_BOOL) \
+
Why do you add this? But no use. You should drop this.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-05-25 11:09
To: gcc-patches
CC: juzhe.zhong
segment intrinsics are really huge amount.
Even though I have tried to optimized them, still we have the issues..
How about LLVM? Can kito help with this issue?
LLVM has already support full intrinsics for a long time and no issues.
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date
tion?
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-05-25 11:43
To: Palmer Dabbelt; Vineet Gupta
CC: kito.cheng; gcc-patches; Kito Cheng; Patrick O'Neill; Jeff Law; macro;
juzhe.zh...@rivai.ai
Subject: Re: RISC-V Bootstrap problems
On 5/24/23 17:13, Palmer Dabbelt wrote:
> O
>> IIRC LLVM is using the table driven mechanism, so it's less impact on the
>> compilation time when the instruction becomes more and more.
Oh, I see. Could you share more details ?
Maybe we can support this in GCC.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-05-25 1
. Do we have the chance optimize it?
I believe the tablegen mechanism in LLVM is well optimized in case of generated
files and functions
so that they won't be affected to much as instructions go up.
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-05-25 12:07
To: juzhe.zh...@r
Bootstrap && Regression on X86 passed.
Ok for trunk ?
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-05-25 10:58
To: gcc-patches
CC: richard.sandiford; rguenther; Ju-Zhe Zhong
Subject: [PATCH V15] VECT: Add decrement IV iteration loop control by variable
amount support
From: Ju-Z
e already.
Wait for kito's final approval.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-25 17:03
To: gcc-patches; Kito Cheng; palmer; juzhe.zh...@rivai.ai; jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH] RISC-V: Add autovec sign/zero extension and truncation.
Hi,
this patch impl
r_iter * iv_rgc->factor
>> != rgc->max_nscalars_per_iter * rgc->factor) ?
When I have this in the condition, ICE for fail to generate IR:
loop_len_76 = MIN_EXPR ;
loop_len_66 = MIN_EXPR ;
loop_len_66 = MIN_EXPR ;
loop_len_65 = MIN_EXPR <0, 4>;
_103 = -loop_len_65;
loop_
IN_EXPR <_103, 4>;
_104 = _103 - loop_len_66; -> use MIN - loop_len_66
loop_len_65 = MIN_EXPR <_104, 4>;
_105 = _104 - loop_len_65;
loop_len_64 = MIN_EXPR <_105, 4>;
loop_len_63 = _105 - loop_len_64;
Could you help me with this ?
Thanks.
juzhe.zh...@rivai.ai
From: R
You should not use RVV_UNOP+2. Instead, you should add an enum call RVV_UNOP_MU
and replace it.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-25 18:08
To: gcc-patches; Kito Cheng; palmer; juzhe.zh...@rivai.ai; jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH v2] RISC-V: Implement aut
e_vlmax_p ())
+{
Doing this just like in riscv_vector::preferred_simd_modes
Others let Kito chime in more comments.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-05-25 17:03
To: gcc-patches; Kito Cheng; palmer; juzhe.zh...@rivai.ai; jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH] R
here are powerpc machines in the GCC compile farm.
It seems that Power is ok with decrement IV since most cases are improved.
I think Richard may help to explain decrement IV more clearly.
Thanks
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-05-26 14:46
To: 钟居哲
CC: gcc-patches;
OK. You mean we should check why if fails in ref_maybe_used_by_stmt_p
instead of doing the data-ref analysis outside dse_classify_store ?
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2022-09-22 15:32
To: Ju-Zhe Zhong
CC: gcc-patches; richard.sandiford
Subject: Re: [PATCH] DSE: Enhance dse
Does your local code exclude my codes?
I am using GCC12.2. When I delete all my codes and apply your codes only.
It fails to delete redundant stores and no auto-vecotorization of my RVV GCC in
this test.
I am not sure whether I am on the same page with you.
juzhe.zh...@rivai.ai
From
OK. Thank you so much fixing this for me. Would you mind pushing your
optimization upstream?
I will abandon my codes. Thank you so much.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2022-09-22 16:48
To: juzhe.zh...@rivai.ai
CC: gcc-patches
Subject: Re: Re: [PATCH] DSE: Enhance dse with
this book provided?
Or you have another better option to fix this issue ? Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2022-09-22 16:48
To: juzhe.zh...@rivai.ai
CC: gcc-patches
Subject: Re: Re: [PATCH] DSE: Enhance dse with def-ref analysis
On Thu, 22 Sep 2022, juzhe.zh...@rivai.ai
to exit the loop)
if (TVL ==0)
exit loop
..
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2022-09-29 17:24
To: Richard Biener via Gcc-patches
CC: Andrew Stubbs; Richard Biener; juzhe.zhong
Subject: Re: [PATCH] vect: while_ult for integer mask
Richard Biener via Gcc-patches writes:
Thank you so much. I will apply this patch and test it in downstream RVV GCC
（12.2.0)
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2022-10-10 19:03
To: gcc-patches
CC: richard.sandiford; ams; juzhe.zhong
Subject: [PATCH][RFT] Vectorization of first-order recurrences
The following picks up
but Clang succeed ?
I am familiar with LLVM. I think I can do this job.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2022-10-10 19:03
To: gcc-patches
CC: richard.sandiford; ams; juzhe.zhong
Subject: [PATCH][RFT] Vectorization of first-order recurrences
The following picks up the
OK. I am gonna commit this with the following patches.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2022-10-12 11:39
To: juzhe.zhong
CC: gcc-patches
Subject: Re: [PATCH] RISC-V: Refine riscv-vector-builtins.o include files and
makefile.
I would suggest we do not include those header files
LGTM.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2022-10-14 15:07
To: Richard Sandiford
CC: Andrew Stubbs; gcc-patches; juzhe.zhong
Subject: Re: [PATCH][RFT] Vectorization of first-order recurrences
On Tue, 11 Oct 2022, Richard Sandiford wrote:
> Richard Biener writes:
> > O
I made a mistake in this patch. I mixed 2 commits into a single patch.
Sorry about that. Please ignore this patch. Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2022-10-24 09:53
To: gcc-patches
CC: kito.cheng; palmer; Ju-Zhe Zhong
Subject: [PATCH] RISC-V: Support (set (mem
Address comments. Fix it soon.
juzhe.zh...@rivai.ai
From: Andrew Pinski
Date: 2022-10-24 10:14
To: juzhe.zhong
CC: gcc-patches; kito.cheng
Subject: Re: [PATCH] RISC-V: Support (set (mem) (const_poly_int))
On Sun, Oct 23, 2022 at 7:04 PM wrote:
>
> From: Ju-Zhe Zhong
>
> g
Hi, since these RVV testcases doesn't necessary need abi configuration.
I fix these testcase in this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604642.html
Plz, verify it and merge it. Thanks.
juzhe.zh...@rivai.ai
From: Andreas Schwab
Date: 2022-10-30 19:00
To: juzhe.
Hi, since these RVV testcases doesn't necessary need abi configuration.
I fix these testcase in this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2022-October/604642.html
Plz, verify it and merge it. Thanks.
juzhe.zh...@rivai.ai
From: Andreas Schwab
Date: 2022-10-30 19:02
To: juzhe.
Thank you so much. Address your comment. I think "maybe_gt (nunits, 1)" is a
more solid solution than I do.
I will send a patch to fix this.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2022-08-19 16:03
To: juzhe.zhong
CC: gcc-patches; rguenther; kito.cheng
Subject: Re: [PAT
t (GET_MODE_NUNITS (inner_mode), 1))
test_vector_subregs_modes (x, nunits - min_nunits, count);
It passed with no warning.
Is 'known_gt (GET_MODE_NUNITS (inner_mode), 1)' a good solution for this?
Thanks!
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2022-08-19 16:03
To: juzhe.zhong
CC: gc
ctorization. And I think only allow poly (1,1)mode used in intrinsics
will
not create issues. Am I understanding wrong ？Feel free to correct me. Thanks ~
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2022-08-19 17:35
To: juzhe.zhong\@rivai.ai
CC: rguenther; gcc-patches; kito.cheng
Subject:
it yourself?
Thank you so much.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2022-08-22 16:31
To: 钟居哲
CC: rguenther; gcc-patches; kito.cheng
Subject: Re: [PATCH] middle-end: skipp stepped vector test of poly_int (1, 1)
and allow the machine_mode definition with poly_uint16 (1, 1)
I sent another patch called "Fix issue of poly_uint16 (1,1) in self test" to
fix it.
I didn't send V2 following this patch because this patch name is misleading.
Thank you so much. Richard.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2022-08-22 16:56
To: juzhe.zhong\@r
I tried #define LOGICAL_OP_NON_SHORT_CIRCUIT 1 in RISC-V port. The warning is
still there.
Are you considering this
patch:https://gcc.gnu.org/pipermail/gcc-patches/2022-August/600120.html
to solve this issue ? Or you are trying another solution to fix this ?
juzhe.zh...@rivai.ai
From
Could you rebase to the trunk ? I don't think segment load store cost depends
on previous patch you sent.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-03-01 23:07
To: 钟居哲; gcc-patches; palmer; kito.cheng
CC: rdapp.gcc; Jeff Law
Subject: Re: [PATCH] RISC-V: Add initial cost handlin
: (vec_duplicate) (reg)))
juzhe.zh...@rivai.ai
From: Demin Han
Date: 2024-03-05 16:40
To: 钟居哲; gcc-patches
CC: kito.cheng; Li, Pan2; jeffreyalaw; Robin Dapp; richard.sandiford
Subject: RE: Re:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of
vec and imm
Hi,
I applied the
LGTM. Thanks for clean up.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-03-05 16:59
To: gcc-patches
CC: juzhe.zhong; kito.cheng; yanzhang.wang; Pan Li
Subject: [PATCH v1] RISC-V: Cleanup unused code in riscv_v_adjust_bytesize [NFC]
From: Pan Li
Cleanup mode_size related code which is not
Hi, han.
I think you can commit this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2024-March/646931.html
RISC-V: Refactor expand_vec_cmp
It's an NFC patch that I approved.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-03-04 14:51
To: gcc-patches
CC: juzhe.zhong; kito.cheng
Su
Thanks for support it.
I leave this patch review to kito who is much more familiar with it than me.
CCing more folks who may be interested at this stuff.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-03-06 14:38
To: gcc-patches
CC: juzhe.zhong; kito.cheng; yanzhang.wang; Pan Li
Subject
LGTM.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-03-07 13:54
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw
Subject: [PATCH] RISC-V: Fix ICE in riscv vector costs
The following code can result in ICE:
-march=rv64gcv_zba_zbb --param riscv-autovec-lmul=dynamic -O3
char
Could you plz add testcase ? I just noticed you didn't append a testcase (jpeg)
in this patch.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-03-07 13:54
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw
Subject: [PATCH] RISC-V: Fix ICE in riscv vector costs
The foll
I suggest open an PR with a PR id.
juzhe.zh...@rivai.ai
发件人： Demin Han
发送时间： 2024-03-07 15:39
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： kito.cheng; pan2.li; jeffreyalaw
主题： RE: [PATCH] RISC-V: Fix ICE in riscv vector costs
OK.
Which is better for testcase name?
1. ice-biggestmode.c or
2
LGTM except a nit comment:
PR 114264 -> PR target/114264
No need to send V3, just commit it with this change.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-03-07 16:32
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw
Subject: [PATCH v2] RISC-V: Fix ICE in riscv vec
gt;Should it really be called autovec-max-lmul? We also use TARGET_MAX_LMUL
>>for builtins etc. Or are we just following LLVM's naming here?
>>Isn't -mrvv-max-lmul sufficient?
The original option is kito's recommandation. Both -mrvv-max-lmul and
-mrvv-autovec-max-lmul a
I can't review this stuff. Let kito review this.
Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-03-18 14:05
To: gcc-patches
CC: juzhe.zhong; kito.cheng; yanzhang.wang; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix ICE for __attribute__((target("arch=+v"))
From: Pan Li
T
LGTM.
juzhe.zh...@rivai.ai
From: Christoph Müllner
Date: 2024-03-22 07:45
To: gcc-patches; Kito Cheng; Palmer Dabbelt; Andrew Waterman; Philipp Tomsich;
Camel Coder; Bruce Hoult; Juzhe-Zhong; Jun Sha; Xianmiao Qu; Jin Ma
CC: Christoph Müllner
Subject: [PATCH] RISC-V: Don't add fract
I think it's harmless to let this patch in GCC-14.
So LGTM from my side to land this path in GCC-14..
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-03-26 01:07
To: Jeff Law; 钟居哲; gcc-patches; palmer; kito.cheng
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: Add initial cost handlin
Thanks a lot for trying to optimize the dynamic LMUL cost model.
The need_additional_vector_vars_p looks good to me.
But
- = (*program_points_per_bb.get (bb)).length () - 1;
+ = (*program_points_per_bb.get (bb)).length ();
I wonder why you remove - 1?
juzhe.zh
OK. It's an obvious fix but it seems to be unrelated to the PR.
Could you split it 2 separate patches ?
Thanks.
juzhe.zh...@rivai.ai
发件人： Demin Han
发送时间： 2024-03-28 19:06
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： kito.cheng; pan2.li; jeffreyalaw; Robin Dapp
主题： RE: [PATCH] RISC-V: R
Thanks for fixing it. LGTM to GCC-15 as Jeff suggested.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-04-02 16:30
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc
Subject: [PATCH v2] RISC-V: Refine the condition for add additional vars in RVV
cost model
The
It's obvious fix to previous incorrect typo.
So LGTM to trunk (GCC-14).
Thanks.
juzhe.zh...@rivai.ai
From: demin.han
Date: 2024-04-02 16:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; jeffreyalaw; rdapp.gcc
Subject: [PATCH] RISC-V: Minor fix for max_point
The program points
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-08 16:09
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Refine the error msg for RVV intrinisc required ext
From: Pan Li
The RVV intrinisc API has sorts of required extension from both
the march
Thanks for fixing it. LGTM from my side.
I prefer wait kito for another ACK.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-11 10:16
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Bugfix ICE for the vector return arg in mode switch
From: Pan Li
This
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-11 11:51
To: gcc-patches
CC: juzhe.zhong; kito.cheng; Pan Li
Subject: [PATCH v1] RISC-V: Remove -Wno-psabi for test build option [NFC]
From: Pan Li
Just notice there are some test case still have -Wno-psabi option,
which is deprecated
ad_64-12.c (internal
compiler error: in validate_change_or_fail, at config/riscv/riscv-v.cc:4972)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12.c (test for
excess errors)
FAIL: gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-3.c
(internal compiler error: in validate_change_or_fail, at
config/riscv/riscv-v.cc:4972)
juzhe.zh...@rivai.ai
Hi, Monk.
This model doesn't include vector. Will you add vector pipeline in the
followup patches ?
juzhe.zh...@rivai.ai
Maybe I do the wrong testing. Let me use a clean linux environment and try
again.
juzhe.zh...@rivai.ai
From: Edwin Lu
Date: 2024-02-01 14:13
To: juzhe.zh...@rivai.ai; gcc-patches
CC: Robin Dapp; kito.cheng; jeffreyalaw; palmer; vineetg; Patrick O'Neill
Subject: Re: [COMMITTED V3 1/4] R
excess errors)
FAIL: gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c (test for excess errors)
Your patch is good.
Thanks for the help.
juzhe.zh...@rivai.ai
From: Edwin Lu
Date: 2024-02-01 14:13
To: juzhe.zh...@rivai.ai; gcc-patches
CC: Robin Dapp; kito.cheng; jeffreyalaw; palmer; vineetg
../../../../gcc/gcc/config/riscv/riscv-avlprop.cc:200
0x1fe3b05 pass_avlprop::execute(function*)
../../../../gcc/gcc/config/riscv/riscv-avlprop.cc:506
Would you mind taking a look at it ?
juzhe.zh...@rivai.ai
From: Edwin Lu
Date: 2024-02-01 14:13
To: juzhe.zh...@rivai.ai; gcc
Thanks. I wonder whether p600 will enable dynamic lmul by default ?
Does dynamic LMUL help with sifive p600 chip ?
juzhe.zh...@rivai.ai
From: Monk Chiang
Date: 2024-02-01 16:10
To: juzhe.zh...@rivai.ai
CC: gcc-patches; kito.cheng
Subject: Re: [PATCH v2] RISC-V: Support scheduling for sifive
x this issue:
diff --git a/gcc/loop-iv.cc b/gcc/loop-iv.cc
index eb7e923a38b..09750951845 100644
--- a/gcc/loop-iv.cc
+++ b/gcc/loop-iv.cc
@@ -646,10 +646,10 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode,
rtx reg,
if (!set)
return false;
- rhs = find_reg_equal_equiv_note (in
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