Yes. I think we are lacking some combine patterns to do all vector-scalar combinations.
If you are interested at this topic, you can do some investigations on that (I believe currently no body works on it for now). I bet we should add some patterns for late-combine PASS for example: (set (plus : (vec_duplicate) (reg))) juzhe.zh...@rivai.ai From: Demin Han Date: 2024-03-05 16:40 To: 钟居哲; gcc-patches CC: kito.cheng; Li, Pan2; jeffreyalaw; Robin Dapp; richard.sandiford Subject: RE: Re:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm Hi, I applied the mentioned last_combine patch(https://patchwork.ozlabs.org/project/gcc/patch/mptbka7em9w....@arm.com/). And did some initial tests. Found that: 1. Float vector-scalar and vector-imm are OK 2. Integer vector-scalar is OK 3. Integer vector-imm(e.g. a[i] > 16) is not OK. When reaches last_combine pass, vec_duplicate(0x10) form is still kept, but no pattern match this now, because all scalar patterns have “register_operand” predication. I think MD file or expand function of rvv need to change for this situation. Regards, Demin
