LGTM
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-08-15 23:49
To: gcc-patches; palmer; Kito Cheng; jeffreyalaw; juzhe.zh...@rivai.ai
CC: rdapp.gcc
Subject: [PATCH] RISC-V: Fix reduc_strict_run-1 test case.
Hi,
this patch changes the equality check for the reduc_strict_run-1
testcase
LGTM.
Thanks for fixing my previous mistakes.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-08-17 19:43
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw
Subject: [PATCH] RISC-V: Fix XPASS slp testcases
This patch fixs XPASS slp testcases on trunk by
making the
/zvksg.c -O3 -g (test for excess errors)
FAIL: gcc.target/riscv/zvksg.c -Os (test for excess errors)
juzhe.zh...@rivai.ai
Why does this patch not have HAS_FRM?
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-08-17 16:05
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support RVV VFWREDUSUM.VS rounding mode intrinsic
API
From: Pan Li
This patch would like to
lcm_av' didn't give us.
>> Just to say
>> you are possibly going to blow up compile-time complexity of your
>> VSETVL dataflow problem?
No, I export 'compute_earliest' as global because 'pre_edge_lcm_av' didn't give
us the 'earliest' re
o the job for calculating
the location of the program to do VSETVL fusion and
turns out it's a quite more reliable and reasonable approach than I do.
So that's why I export those 2 functions for us to be use in Phase 3 (Demand
fusion) in RISC-V backend VSETVL PASS.
Thanks.
juzhe.
p *, sbitmap *, sbitmap *);"
which is already exported as global.
Do you mean I add those 2 functions (I export this patch) and
"compute_avaialble" which has already been exported
into namespace lcm like this:
namespace lcm
{
compute_available
compute_antinout_edge
compute_earliest
}
?
think it's a little bit ugly since some functions in lcm.cc belongs to LCM
namespace, some are not.
And we already have compute_available that has non LCM name.
May be this patch is better and OK?
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-08-21 16:06
To: rguenth
Yes. I wonder why some floating-point rounding mode has HAS_FRM, some doesn't
have?
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-08-21 15:10
To: juzhe.zh...@rivai.ai; gcc-patches
CC: Wang, Yanzhang; kito.cheng
Subject: RE: [PATCH v1] RISC-V: Support RVV VFWREDUSUM.VS rounding
Thanks kewen.
I am gonna wait for stefan's test result before I merge this patch.
Thanks.
juzhe.zh...@rivai.ai
From: Kewen.Lin
Date: 2023-08-22 09:12
To: Juzhe-Zhong
CC: richard.sandiford; rguenther; stefansf; gcc-patches
Subject: Re: [PATCH V5] VECT: Support loop len control on EXTRACT
Thanks for fixing it.
I am wonder could you add testcase into the patch?
Or the testcase is too big and not appropriate to add.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-08-22 10:29
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; xuli
Subject: [PATCH] RISCV: Fix PR111074 [GCC13 BUG
Ok to backport GCC 13.
You could disscuss with Pan Li whether you backport it or he backport it.
Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-08-22 10:42
To: xuli1; gcc-patches
CC: kito.cheng; palmer; juzhe.zhong
Subject: Re: [PATCH] RISCV: Fix PR111074 [GCC13 BUG]
The test case is
at bootstrap didn't report this.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-08-21 22:16
To: Juzhe-Zhong
CC: gcc-patches; rguenther
Subject: Re: [PATCH] gimple_fold: Support
COND_LEN_FNMA/COND_LEN_FMS/COND_LEN_FNMS gimple fold
Juzhe-Zhong writes:
> Hi, Richard and
LGTM.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-08-22 11:02
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; palmer; jeffreyalaw
Subject: [PATCH] RISC-V: Change fnms testcases assertion to xfail
Hi,
This patch fixes inappropriate assertions in fnms testcases since
we want to
nd, float extend, abs, sqrt, ceil, floor,
etc.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-08-22 15:33
To: juzhe.zhong; Andrew Pinski
CC: rdapp.gcc; Lehua Ding; gcc-patches@gcc.gnu.org; kito.ch...@gmail.com;
pal...@rivosinc.com; jeffreya...@gmail.com
Subject: Re: [PATCH] RISC-V
+/* Nonzero if MODE is a vector float mode. */
+#define VECTOR_FLOAT_MODE_P(MODE) \
+ (GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT)
Why you add this?
Remove it. Otherwise, LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-16 15:28
To: gcc-patches
CC: juzhe.zhong
LGTM. Thanks for fix this bug.
Let's wait for Jeff's final approve.
Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-16 16:09
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Bugfix for RVV integer re
Thanks a lot! I will wait for Richard final approve.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-16 17:04
To: Ju-Zhe Zhong
CC: gcc-patches; richard.sandiford; rdapp.gcc
Subject: Re: [PATCH V4] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs
On Thu, 15 Jun 2023,
Thanks Robin.
I have sent V5 for future merge convenience.
I didn't change len_load/len_store description since I think it should be
another separate patch.
This patch is adding len_maskload/len_maskstore.
I will wait for Richard S the final comments.
juzhe.zh...@rivai.ai
From: Robin
Address comments and send V6.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-16 18:10
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; rguenther; richard.sandiford
Subject: Re: [PATCH V4] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs
> <= (operand 2 + opera
I notice VWF_ZVE64
should be removed.
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-06-19 09:29
To: 钟居哲; gcc-patches
CC: rdapp.gcc; Jeff Law; Wang, Yanzhang; kito.cheng
Subject: RE: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64
Thanks Juzhe, will not send the V2 as only
ipermail/gcc-patches/2023-June/622089.html
So the current these 2 fixes are not necessary.
Would you mind sending V2 with only "VWEXTF" fix ?
Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-06-19 12:26
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; Li Xu
Subject: [PATCH]
LGTM.
Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-06-19 13:52
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; Li Xu
Subject: [PATCH v2] RISC-V: Fix VWEXTF iterator requirement
gcc/ChangeLog:
* config/riscv/vector-iterators.md: zvfh/zvfhmin depends on the Zve32f
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-19 14:46
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64
From: Pan Li
The rvv widdening reduction has 3 different
Bootstrap && Regression on X86 no surprise difference.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-06-20 00:17
To: gcc-patches
CC: rguenther; richard.sandiford; Ju-Zhe Zhong
Subject: [PATCH] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer
From: Ju-Zhe Zhong
This patch
more of the underlying
registers than vnx2bi.
And adjust commit log "vnx16bi" into "vnx16qi".
Otherwise, LGTM.
Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-06-20 14:07
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; Li Xu
Subject: [PATCH] RISC-V: Set the natu
LGTM. Thanks!
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-06-20 14:46
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; Li Xu
Subject: [PATCH v2] RISC-V: Set the natural size of constant vector mask modes
to one RVV data vector.
If reinterpret vnx2bi as vnx16qi, vnx16qi must occupy no
turns out is
very obvious consume 1 more vector insn.
You may argue that this patch needs 1 more scalar insn (slli) which is relative
cheaper than vector insn.
I prefer this patch solution.
Address comments. I have add comments to send V2.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date:
Ok. No need to wait just commit.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-20 15:58
To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@rivai.ai; jeffreyalaw
CC: rdapp.gcc
Subject: [PATCH] RISC-V: Fix vmul test expectation.
Hi,
I forgot to check for vfmul in the
.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-20 16:03
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Optimize codegen of VLA SLP
> This is a nice improvement. Even though we're in the SLP realm
Ok. Just sent V2. I will adjust comment and send V3 again :)
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-20 16:55
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; kito.cheng; Kito.cheng; palmer; palmer; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Optimize codegen of VLA SLP
Ok.
juzhe.zh...@rivai.ai
From: Lehua Ding
Date: 2023-06-20 17:45
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; kito.cheng; palmer; jeffreyalaw; pan2.li
Subject: [PATCH] RISC-V: Fix compiler warning of riscv_arg_has_vector
Hi,
This little patch fixes a compile warning issue that my previous
Could you merge it ?
By the way, could Lehua get the write access?
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-20 18:47
To: Lehua Ding; gcc-patches
CC: rdapp.gcc; juzhe.zhong; kito.cheng; palmer; jeffreyalaw; pan2.li
Subject: Re: [PATCH] RISC-V: Fix compiler warning of
Hi, Richi. I am not sure why I failed to send this patch to @sues email at the
first time.
Now I cc your gmail.
This is the V2 patch addressing your comments for V1.
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-06-20 21:42
To: gcc-patches
CC: richard.sandiford; rguenther; Ju
Good catch!
vmulh.vx v24,v24,zero -> vmv.v.i v1,0
can eliminate use of v24 and reduce register pressure.
But I wonder why you pick only VI_QHS?
+ [(set (match_operand:VI_QHS 0 "register_operand")
SEW = 64 should always have such optimization.
Thanks.
juzhe.zh...@ri
k you need to get_mask_mode, instead, you can simplify the code as
follows:
emit_insn (gen_pred_mov (mode, operands[0], CONST1_RTX (mode),
+ RVV_VUNDEF (mode), CONST0_RTX (GET_MODE (operands[0])),
+ operands[5], operands[6], operands[7], operands[8]));
use mode to get the mask mode.
juz
Oh. Yes. Thanks for Robin pointing this.
@yanzhang, could you refine this patch more deeply to gain more optimizations ?
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-21 14:27
To: yanzhang.wang; gcc-patches
CC: rdapp.gcc; juzhe.zhong; kito.cheng; pan2.li
Subject: Re: [PATCH
LGTM as long as you remove all stuff related to UNSPEC_VNCOPYSIGN
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-21 14:36
To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff Law
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: Implement autovec copysign.
> You should remove all &quo
No, I don't think we need another UNSPEC.
You just need to modify predicate of (match_operand: 4 "reg_or_0_operand")
juzhe.zh...@rivai.ai
From: Wang, Yanzhang
Date: 2023-06-21 15:08
To: juzhe.zh...@rivai.ai; Robin Dapp; gcc-patches
CC: Robin Dapp; Kito.cheng; Li, Pan2
Subject:
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: shiyulong
Date: 2023-06-21 15:39
To: gcc-patches
CC: palmer; kito.cheng; jeffreyalaw; juzhe.zhong; pan2.li; wuwei2016; jiawei;
shihua; dje.gcc; pinskia; yulong
Subject: [PATCH V1] RISC-V:Add float16 tuple type abi
From: yulong
gcc/ChangeLog
on the same page with you.
Could you help me with that?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-21 16:53
To: Ju-Zhe Zhong
CC: gcc-patches; richard.sandiford
Subject: Re: [PATCH V3] VECT: Apply LEN_MASK_{LOAD,STORE} into vectorizer
On Tue, 20 Jun 2023, juzhe.zh...@rivai.
ore_mode but
it fail to compile:
../../../riscv-gcc/gcc/optabs-query.h:191:63: error: ‘internal_fn’ has not been
declared
opt_machine_mode get_len_load_store_mode (machine_mode, bool, internal_fn* =
nullptr);
I am not sure whether I am on the same page with you.
Could you help me with that?
T
Such issue will be addressed by this patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/622440.html
But still wait for Jakub's comments.
juzhe.zh...@rivai.ai
From: Andreas Schwab
Date: 2023-06-23 18:25
To: shiyulong
CC: gcc-patches; palmer; kito.cheng; jim.wilson.gcc; juzhe.
Hi, Li.
Appreciate for catching this!
I think it's better:
-emit_insn (gen_rtx_SET (gen_lowpart (e.vector_mode (), e.target), src));
+emit_move_insn (gen_lowpart (e.vector_mode (), e.target), src);
do this to fix this issue.
Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-06-25 11:
LGTM.
Thanks for fixing it.
Hi, Jeff:
I saw Li Xu is frequently helping RVV support in GCC. Is it possible to give
him the write access?
Thanks.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-06-25 17:09
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; zhengyu; Li Xu
Subject: [PATCH v2
ength isn't constant the code should
>>be the same as the IFN_MASK_STORE variant.
I understand your idea. Forget about V2 patch (which I sent). I will send V3
patch to fix
both LEN_STORE and LEN_MASK_STORE.
Thank you so much for the review!
juzhe.zh...@rivai.ai
From: Richard Biener
Da
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-26 17:36
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Remove duplicated extern function_base decl
From: Pan Li
Signed-off-by: Pan Li
gcc/ChangeLog:
* config
Hi, Richi. I am wondering whether it is true that :?
TYPE_VECTOR_SUBPARTS (vectype).to_constant ()
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-26 19:18
To: Ju-Zhe Zhong
CC: gcc-patches; richard.sandiford
Subject: Re: [PATCH V2] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE
No, I don't think we can use first case (vid + vand -npatterns) for base != 0,
since the first element value of vid is alway 0.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-26 15:51
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; palmer; palmer; jeffre
a));
return b;
}
}
It seems that assertion will fail When nunits = [2,2] , len + bias = 3, for
example.
I may be wrong.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-26 20:16
To: Ju-Zhe Zhong
CC: gcc-patches; richard.sandiford
Subject: Re: [PATCH V3] SCCVN: Add L
Sure. Sent it:
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/622836.html
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-06-26 17:10
To: Robin Dapp
CC: Juzhe-Zhong; gcc-patches; kito.cheng; palmer; palmer; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Enhance RVV VLA SLP auto
Yes, we have a fix patch (which has been reviewed by jakub) already but missing
testing.
And we are finding a nvdia GPU to test offload of that patch.
We will land it after we finished the test.
Thanks.
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-06-27 14:15
To: Li Xu; gcc-patches
: Support DYNAMIC rounding mode on mode-switching which may need to
modify the mode-switching PASS.
Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-27 14:06
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang; jeffreyalaw
Subject: [PATCH v1] RISC-V: Allow rounding mode
so why I was
>> asking for VL vector testcases.
Ok, I understand your point, but RVV doesn't use LEN_MASK_STORE in intrinsics.
I am not sure how to reproduce VL vectors
in C code.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-27 15:33
To: Ju-Zhe Zhong
CC: gcc-pat
des, RVV currently can't have VLS modes (V4SI) since LTO issue.
I am trying to find a CSE opportunity on VL vectors.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-27 15:47
To: juzhe.zh...@rivai.ai
CC: gcc-patches; richard.sandiford; pan2.li
Subject: Re: Re: [PATCH V4] SCCVN:
VE: https://godbolt.org/z/63a6WcT9o
It also fail to have CSE opportunity.
It seems that it's difficult to have such CSE opportunity in VL vectors.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-27 15:47
To: juzhe.zh...@rivai.ai
CC: gcc-patches; richard.sandiford; pan2.li
Subje
all the RVV auto-vectorization patterns in middle-end, I
come back to take a look at LEN_MASK_STORE in SCCVN?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-27 16:34
To: juzhe.zh...@rivai.ai
CC: gcc-patches; richard.sandiford; pan2.li
Subject: Re: Re: [PATCH V4] SCCVN: Add
and documents (No complicate
vectorizer support).
Really appreciate your help!
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-27 16:56
To: juzhe.zh...@rivai.ai
CC: gcc-patches; richard.sandiford; pan2.li
Subject: Re: Re: [PATCH V4] SCCVN: Add LEN_MASK_STORE and fix LEN_STORE
On Tue
This patch is the critical patch for following patches since it is a bug which
I already address in rvv-next.
juzhe.zh...@rivai.ai
From: Juzhe-Zhong
Date: 2023-06-28 09:59
To: gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; Juzhe-Zhong
Subject: [PATCH V2] RISC
I have commented in commit log:
before this patch:
The mask is:
.LC1:
.byte 68 > 0b01000100
However, this is incorrect for RVV since RVV always uses 1-bit compact mask,
now after this patch:
.LC1:
.byte 10 > 0b1010
juzhe.zh...@rivai.ai
From: Kito Cheng
Date
+= BYTES_PER_RISCV_VECTOR.to_constant () / min_lmul;
+ unsigned container_size = MAX (CEIL (npatterns (), 8), min_container_size);
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-06-28 14:01
To: Jeff Law
CC: juzhe.zh...@rivai.ai; gcc-patches; kito.cheng; palmer; palmer; Robin Dapp
Subject: Re: [PATCH V2] RISC-V: Fix
RVV is scalable vector which always uses ADJUST_NUNTIS and
ADJUST_BYTESIZE && ADJUST_PRECISION.
So this will make a confusion to GCC.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-28 15:17
To: Jeff Law
CC: Kito Cheng; juzhe.zh...@rivai.ai; gcc-patches; kito.cheng; palm
.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-28 15:17
To: Jeff Law
CC: Kito Cheng; juzhe.zh...@rivai.ai; gcc-patches; kito.cheng; palmer; palmer;
Robin Dapp
Subject: Re: [PATCH V2] RISC-V: Fix bug of pre-calculated const vector mask
On Wed, Jun 28, 2023 at 6:09 AM Jeff Law via Gcc
Hi, after deeply diging into this issue:
I figure out what is happening, this is the V3 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/623052.html
There is a comprehensive explanation in commit log.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-06-28 11:16
To: juzhe.zh
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-29 09:40
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang; jeffreyalaw
Subject: [PATCH v1] RISC-V: Support vfadd static rounding mode by mode switching
From: Pan Li
This patch would like to support the vfadd static
, which API
doesn't need rounding mode.
Do not trust the rvv-intrinsic-doc since it's often wrong.
You should check doc too, if doc is wrong, you should not only correct GCC
implementation but also make a fix PR to the doc.
Thanks.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-0
It's meaningless. Drop this patch.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-29 14:00
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang; jeffreyalaw
Subject: [PATCH v1] RISC-V: Refactor vxrm_mode attr for type attr equal
From: Pan Li
This patch would li
he insn, we don't need to remove 4 places.
LGTM. Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-29 14:00
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang; jeffreyalaw
Subject: [PATCH v1] RISC-V: Refactor vxrm_mode attr for type attr equal
From: Pan Li
Thi
handle this in the RISC-V backend for VNx1BI/VNx2BI/VNx4BI.
I think this is RISC-V backend issue and can be well addressed in RISC-V port
(as this patch I post).
No need to bother generic codes since other target could not have the same
issues.
Thanks.
juzhe.zh...@rivai.ai
From: Richard
l generate padding bits for it which we
don't want it.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-29 16:14
To: Robin Dapp via Gcc-patches; 钟居哲; Jeff Law; kito.cheng; kito.cheng; palmer;
palmer; richard.sandiford
CC: rdapp.gcc
Subject: Re: [PATCH V3] RISC-V: Fix bug of pre-calcu
much.
I prefer it to be GCC-15 (such issue can be walk around in RISC-V backend)
since we have to much things need to be landed in GCC-14.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-29 16:53
To: juzhe.zh...@rivai.ai; gcc-patches; jeffreyalaw; kito.cheng; Kito.cheng;
palmer
to make it perfect.
The reason why I plan that is global reviewers bandwidth is very limit.
We should make the highest priority auto-vectorizaiton middle-end support first
and then let's come back to see the corner case issues.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-
(test for excess errors)
juzhe.zh...@rivai.ai
From: Thomas Schwinge
Date: 2023-06-29 17:29
To: Pan Li
CC: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; rdapp@gmail.com;
jeffreya...@gmail.com; yanzhang.w...@intel.com; kito.ch...@gmail.com;
rguent...@suse.de; ja...@redhat.com; Tobias Burnus
Ok. Thanks for taking care of it!
>> That looks like a different issue, though?
Yes, it's different issue and I am trying to fix it in RISC-V backend.
Thanks a lot.
juzhe.zh...@rivai.ai
From: Thomas Schwinge
Date: 2023-06-29 17:47
To: juzhe.zh...@rivai.ai
CC: pan2...@intel.com;
ons?
Thanks.
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-06-29 12:18
To: Jakub Jelinek; Richard Biener
CC: gcc-patches@gcc.gnu.org; jeffreya...@gmail.com; kito.ch...@gmail.com;
juzhe.zh...@rivai.ai; rdapp@gmail.com
Subject: RE: [PATCH] Prevent TYPE_PRECISION on VECTOR_TYPEs
Sorry
Yes. Thanks for taking care of it!
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-29 18:07
To: juzhe.zh...@rivai.ai; pan2.li; Richard Biener
CC: rdapp.gcc; gcc-patches; jeffreyalaw; kito.cheng
Subject: Re: [PATCH] Prevent TYPE_PRECISION on VECTOR_TYPEs
Ah, the one sub-thread continued
am not claiming that this patch solution is the only solution.
I am welcome you can provide another solution as long as you can make this
codegen become the perfect codegen that this patch achieved.
I think maybe you should make sure you are using the correct toolchain that
built with patch.
Tha
No, reduction patterns won't help.
As I said in vfwmul patch. You should make sure your environment is working
then try again.
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-06-30 07:43
To: 钟居哲; gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; rdapp.gcc
Subject: Re: [
Thanks a lot!
Really appreciate your help ! That's really helpful for RVV (RISC-V vector).
Could you merge your patch after you tested?
Thanks.
juzhe.zh...@rivai.ai
From: Thomas Schwinge
Date: 2023-06-30 04:14
To: Pan Li; gcc-patches@gcc.gnu.org; Richard Biener; Jakub Jelinek
CC: juz
h is not approved since I can get the perfect codegen in
my downstream.
Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-06-30 09:26
To: juzhe.zh...@rivai.ai; gcc-patches
CC: kito.cheng; Kito.cheng; palmer; palmer; Robin Dapp
Subject: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfw
Thanks for the comments.
I will fix doc's description as you suggested.
I personally prefer **NOT** to include BIAS in the gather/scatter since I don't
known how it will be used.
Let's wait for Richi or Richard more comments.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
D
dress = a5 + v2[3]
I am not sure why you mention 'len' in bytes.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-30 14:26
To: Ju-Zhe Zhong
CC: gcc-patches; richard.sandiford
Subject: Re: [PATCH V2] Machine Description: Add LEN_MASK_{GATHER_LOAD,
SCATTER_STORE} patt
Hi, Richi. I have added "BIAS" and send V4:
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/623293.html
Forget about V3. I made a mistake there, sorry about that.
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-30 14:26
To: Ju-Zhe Zhong
CC: gcc-patches; richard
misleading.
As Richard's comments, I have change the order of the arguments into:
loop_len = SELECT_VL
control_mask = comparison
v = LEN_MASK_GATHER_LOAD (.., loop_len, bias, control_mask)
LEN_SCATTER_STORE (... v, ..., loop_len, bias, control_mask)
Sorry about that.
juzhe.zh...@rivai.ai
Thanks for fixing it. LGTM.
I think you can merge it when Robin is ok since this is a simple typo fix.
Thanks.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-07-03 16:08
To: gcc-patches
CC: juzhe.zhong; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Fix one typo of
We failed to merge it since it's been rejected.
https://patchwork.sourceware.org/project/gcc/patch/20230628041512.188243-1-juzhe.zh...@rivai.ai/
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-07-03 15:49
To: juzhe.zhong
CC: rdapp.gcc; Jeff Law; gcc-patches; kito.cheng; kito.cheng; p
We can apply it but not sure why the patchwork shows it's rejected.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-07-03 16:44
To: juzhe.zh...@rivai.ai
CC: rdapp.gcc; jeffreyalaw; gcc-patches; kito.cheng; Kito.cheng; palmer; palmer
Subject: Re: [PATCH] RISC-V: Support vfwmul.vv co
OK. Thanks. Will commit with your cleanup patch.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-07-03 16:49
To: juzhe.zh...@rivai.ai
CC: rdapp.gcc; jeffreyalaw; gcc-patches; kito.cheng; Kito.cheng; palmer; palmer
Subject: Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering
On 7/3/23 10
Thanks kito.
Lehua will merge it for me.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-07-03 17:01
To: Robin Dapp
CC: juzhe.zh...@rivai.ai; jeffreyalaw; gcc-patches; Kito.cheng; palmer; palmer
Subject: Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering
Tried on local
amp;& TARGET_64BIT"
{
rtx mem = adjust_address (operands[0], BLKmode, 0);
rtx len = gen_reg_rtx (SImode);
emit_move_insn (len, gen_rtx_ZERO_EXTEND (SImode, operands[2]));
emit_insn (gen_vstlv16qi (operands[1], len, mem));
DONE;
});;
is already correct order {len,bias}. Only Gimple IR need
LEN_MASK_LOAD/STORE, their orders are consistent now after this
patch.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-07-03 17:17
To: juzhe.zhong; gcc-patches
CC: rdapp.gcc; richard.sandiford; rguenther; linkw; krebbel
Subject: Re: [PATCH V2] Middle-end: Change order of
LEN_MASK_LOAD
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-07-03 18:57
To: gcc-patches
CC: juzhe.zhong; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Fix one typo for emit_mode_set.
From: Pan Li
This patch would like to fix one typo for scaler[should be scalar] in
LGTM
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-07-04 13:50
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Fix one bug for floating-point static frm
From: Pan Li
This patch would like to fix one bug to align below
I prefer to defer this patch when you implementing dynamic rounding mode.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-07-04 16:41
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Refine the insn pattern of fsrm
From
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-07-04 16:08
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Fix one bug for floating-point static frm
From: Pan Li
This patch would like to fix one bug to align below
Hi, Richi.
Thanks so much. I have addressed comments and sent V3 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/623566.html
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-07-04 17:27
To: Ju-Zhe Zhong
CC: gcc-patches; richard.sandiford
Subject: Re: [PATCH V2] VECT
Oh. Sorry for incorrect typo in commit log.
>> Address comments from Richard.
Change it into "Address comments from Richi." :).
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zhong
Date: 2023-07-04 17:54
To: gcc-patches
CC: richard.sandiford; rguenther; Ju-Zhe Zhong
Subject:
urn (conditional_internal_fn_code (fn) != ERROR_MARK
|| get_unconditional_internal_fn (fn) != IFN_LAST ? 0 : -1);
}
}
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-07-04 19:05
To: Ju-Zhe Zhong
CC: gcc-patches; richard.sandiford
Subject: Re: [PATCH V3] VECT: Apply
pport len_mask_gather_load in RISC-V port?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-07-04 19:17
To: juzhe.zh...@rivai.ai
CC: gcc-patches; richard.sandiford
Subject: Re: Re: [PATCH V3] VECT: Apply LEN_MASK_GATHER_LOAD/SCATTER_STORE into
vectorizer
On Tue, 4 Jul 2023, juzhe.zh...@rivai.ai
Sorry for I made a mistake in V4:
+ if (final_len && final_len)
It should be
+ if (final_len && final_mask)
I fixed it on V5 patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/623589.html
Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zho
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