LGTM yet.
Joshua
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发件人：juzhe.zh...@rivai.ai
发送时间：2024年1月10日(星期三) 10:34
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner&q
Hi Kito,
Thank you for your support again.
I believe we can get all our xtheadvector patches
ready before the end of Feb.
May I please ping the arch patch again?
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641801.html
This is the patch that all the following patches rely on.
Joshua
/config/riscv/thead-vector-builtins.cc+
Why do you rebuild another new object ?
+ Copyright (C) 2022-2023 Free Software Foundation, Inc.
Incorrect copyright
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-10 10:57
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philip
-
发件人：juzhe.zh...@rivai.ai
发送时间：2024年1月10日(星期三) 15:17
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Handle diffe
gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Handle differences between XTheadvector and Vector
Why do you need to invade existing shapes ?
juzhe.z
_ops
Instead, you should use all_v_scalar_const_ptr_ops
And revise th_loadstore_width, append the name according TYPE_UNSIGNED and
GET_MODE_BITSIZE (GET_MODE_INNER (TYPE_MODE
(instance.op_info->args[i].get_tree_type (instance.type.index
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Da
or-specific intrinsics.
instance.op_info->args[i].get_tree_type (instance.type.index) is output type.
You can use GDB debug it .
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-10 18:57
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.m
Can you see the images that I sent to you in the last email？
If not, maybe you can refer to the last chapter in the thead spec.
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发件人：joshua
发送时间：2024年1月10日(星期三) 19:06
收件人："juzhe.zh...@rivai.ai";
"gcc-patches&
s ?
+DEF_RVV_FUNCTION (th_vlb, th_loadstore_width, full_preds,
i8_v_scalar_const_ptr_ops)
Why it is not :
DEF_RVV_FUNCTION (th_vlb, th_loadstore_width, full_preds,
all_v_scalar_const_ptr_ops)
?
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-10 19:06
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wi
Hi Robin,
Thank you for your suggestions!
The patch has been updated by adding a new attribute to
disable alternative for xtheadvector or RVV1.0 instead of
overlaoding group_overlap.
Joshua
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发件人：钟居哲
发送时间：2024年1月10日(星期三) 21
uot;W87,W87,W87,W87, vr,
vr")) (match_operand:VOEXTI 2 "vector_merge_operand"" vu, vu,
0, 0, vu,0")))]- "TARGET_VECTOR"+ "TARGET_VECTOR &&
!TARGET_XTHEADVECTOR" "vext.vf8\t%0,%3%p1" [(set_attr &qu
To be specific, in CSE pass, the initial pattern will be optimized into the
sext/zext pattern.
--
发件人：joshua
发送时间：2024年1月11日(星期四) 17:11
收件人："juzhe.zh...@rivai.ai";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andr
ATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
You mean which pattern optimized sext/vzext pattern?
I didn't see theadvector-specific extension patterns. Could you show me?
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-11 17:14
收件人： juzhe.zh...@rivai.ai; gc
advector-specific extension patterns. Could you show me?
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-11 17:14
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; jinma; cooper.qu
主题： Re：[PATCH v5] RISC-V: Add support for xtheadvector
[(unspec:
+ [(match_operand: 0 "vector_mask_operand" "vmWc1")
+ (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 5 "const_int_operand" " i")
+ (reg:SI VL_REGNUM)
+
support for xtheadvector-specific intrinsics.
I prefer you remove those TARGET_THEADVECTOR for now.
And file PR let me see the real problem.
I don't believe this should not fixed by this way.
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-11 17:26
收件人： juzhe.zh...@rivai.ai; gcc-pat
cs.
Ok. Let's hold on "RISC-V: Handle differences between XTheadvector and Vector"
patch
until you can reproduce the issue for me.
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-11 17:29
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreya
LGTM. Could you resend the patch "RISC-V: Handle differences between
XTheadvector and Vector
Thanks.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-11 17:52
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhong; Jun Sh
v5] RISC-V: Add support for xtheadvector-specific intrinsics.
Ok. Let's hold on "RISC-V: Handle differences between XTheadvector and Vector"
patch
until you can reproduce the issue for me.
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-11 17:29
收件人： juzhe.zh...@rivai.ai; gcc-pat
ode_for_pred_vf2 (, mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
}
[(set_attr "type" "vext")
(set_attr "mode" "")])
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-11 20:05
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Ji
送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
(vec_duplicate:RVVM1QI (reg:QI 147
Find the RTL define pseudo 147 to me.
I guess
uot;gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
Does theadvector has extension instructions ?
Show me the
oshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
Yes.
juzhe.zh...@rivai.ai
发件人： joshua
发送时
cannot
come up with any better way than pattern copy. Do you have any suggestions?
Joshua
--
发件人：钟居哲
发送时间：2023年12月21日(星期四) 07:04
收件人："cooper.joshua";
"gcc-patches"
抄 送："jim.wilson.gcc"; palmer;
andrew
SPEC_VMSBC))]
"TARGET_XTHEADVECTOR"
"vmsbc.vvm\t%0,%1,%2,%3"
[(set_attr "type" "vicalu")
(set_attr "mode" "")
(set_attr "vl_op_idx" "4")
(set (attr "avl_type_idx") (const_int 5))])
Joshua
-
Hi Juzhe,
Sorry but I'm not quite familiar with the group_overlap framework. Could you
take this pattern as an example to show how to disable an alternative in some
target?
Joshua
--
发件人：juzhe.zh...@rivai.ai
发送时间：2023年12月22
s this used for ?
How about:
+ /* We need to add th. prefix to all the xtheadvector
+ insturctions here.*/
+ if (TARGET_XTHEADVECTOR && p[0] == 'v')
+ fputs ("th.", asm_out_file);
\ No newline at end of file
New line should be added into prefix.c
juzhe.zh...@rivai.ai
From:
ld be better to just prototype in riscv-vector-builtins-bases.h.
Joshua
--
发件人：Jeff Law
发送时间：2023年12月21日(星期四) 02:14
收件人："Jun Sha (Joshua)";
"gcc-patches"
抄 送："jim.wilson.gcc"; palmer;
andrew; &quo
Hi Jeff,
Yes, I will change soemthing in vector_csr_operand in the following
patches.
Constraints will be added that the AVL cannot be encoded as an
immediate for xtheadvecotr vsetvl.
Joshua
--
发件人：Jeff Law
发送时间：2023年12月21日
ld be better to just prototype in riscv-vector-builtins-bases.h.
Joshua
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发件人：Jeff Law
发送时间：2023年12月21日(星期四) 02:14
收件人："Jun Sha (Joshua)";
"gcc-patches"
抄 送："jim.wilson.gcc"; palmer;
andrew; &quo
ific intrinsics"?It adds support new xtheadvector
instructions. Is it OK to be merged?
Joshua
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发件人：juzhe.zh...@rivai.ai
发送时间：2023年12月29日(星期五) 09:58
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim W
ific intrinsics"? It adds support for new xtheadvector
instructions. Is it OK to be merged?
Joshua
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发件人：juzhe.zh...@rivai.ai
发送时间：2023年12月29日(星期五) 09:58
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim W
Hi Juzhe,
For vector_csr_operand, please refer to
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641124.html.
Joshua
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发件人：juzhe.zh...@rivai.ai
发送时间：2023年12月29日(星期五) 10:14
收件人："cooper.joshua";
"gcc-p
.@rivai.ai
发送时间：2023年12月29日(星期五) 10:22
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re: Re：[PATCH v4 5/6] RISC-V: Handle differences between XTheadv
Hi Juzhe,
These vsetvl patterns were written by you with csr_operand initially.
Are you sure it can be repalced by vector_length_operand?
Joshua
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发件人：juzhe.zh...@rivai.ai
发送时间：2023年12月29日(星期五) 10:25
收件人："cooper.j
rnative approach is we can change vsetlvi ASM rule:
"vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
if (TARGET_THEADVECTOR)
...
else
else if (code == CONST_INT)
{
/* Tail && Mask policy. */
asm_fprintf (file, "%s", IS_AGNOSTIC (UINTVAL (op))
ilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner"
主 题：Re: Re：[PATCH v4] RISC-V: Handle differences between XTheadvector and Vector
Like riscv_output_move
if (TARGET_THEADVECTOR)
return vsetvlino tail policy and mask policy.
else
return ..
SM rule:
"vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
if (TARGET_THEADVECTOR)
...
else
else if (code == CONST_INT)
{
/* Tail && Mask policy. */
asm_fprintf (file, "%s", IS_AGNOSTIC (UINTVAL (op)) ? "a" : "u");
Hi Juzhe,
So is the following patch that this patch relies on OK to commit?
https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641533.html
Joshua
--
发件人：钟居哲
发送时间：2024年1月2日(星期二) 06:57
收件人：Jeff Law;
"cooper.joshua&qu
Hi Juzhe,
Stage 3 will close today and there are still some patches that
haven't been reviewed left.
So is it possible to get xtheadvector merged in GCC-14?
We emailed Kito regarding this, but haven't got any reply ye
Hi Kito,
Thank you for your support.
So even during stage 4, we can merge this for GCC 14?
--
发件人：Kito Cheng
发送时间：2024年1月8日(星期一) 11:06
收件人：joshua
抄 送："juzhe.zh...@rivai.ai";
jeffreyalaw; "gcc-patches";
t;vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
+ { return TARGET_XTHEADVECTOR ? "vsetvli\t%0,%1,e%2,%m3" :
"vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"; }
I prefer do it in ASM_OUTPUT
+ Copyright (C) 2022-2023 Free Software Foundation, Inc.
Copyright is not correct.
juzhe.zh.
t in ASM_OUTPUT
+ Copyright (C) 2022-2023 Free Software Foundation, Inc.
Copyright is not correct.
juzhe.zh...@rivai.ai
From: Jun Sha (Joshua)
Date: 2024-01-03 14:15
To: gcc-patches
CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; juzhe.zhon
s invasion will come soon.
Joshua
--
发件人：Kito Cheng
发送时间：2023年11月18日(星期六) 18:33
收件人：Philipp Tomsich
抄 送：Jeff Law;
"juzhe.zh...@rivai.ai";
"gcc-patches"; "kito.cheng";
"cooper.joshua"; Robin
D
t;> where pthreads is enabled via other methods than just -lpthread (e.g.
>> MinGW)
>>
>> Signed-off-by: Joshua Watt
>> ---
>> config/ax_pthread.m4 | 485
>> gold/Makefile.am | 11 +-
>> gold/Makefile.in
On Mon, 2018-02-19 at 17:24 -0800, Cary Coutant wrote:
> Please see this patch posted to the binutils list:
>
>https://sourceware.org/ml/binutils/2018-02/msg00260.html
>
> where Joshua proposes to add the ax_pthread.m4 script, from the
> autoconf macro archive, to the co
On Fri, 2018-02-23 at 08:54 -0600, Joshua Watt wrote:
> On Mon, 2018-02-19 at 17:24 -0800, Cary Coutant wrote:
> > Please see this patch posted to the binutils list:
> >
> >https://sourceware.org/ml/binutils/2018-02/msg00260.html
> >
> > where Joshua propose
config/
* ax_pthread.m4: Add file
---
config/ax_pthread.m4 | 485 +++
1 file changed, 485 insertions(+)
create mode 100644 config/ax_pthread.m4
diff --git a/config/ax_pthread.m4 b/config/ax_pthread.m4
new file mode 100644
index 000.
On Thu, 2018-03-22 at 21:45 -0500, Joshua Watt wrote:
> config/
> * ax_pthread.m4: Add file
> ---
> config/ax_pthread.m4 | 485
> +++
> 1 file changed, 485 insertions(+)
> create mode 100644 config/ax_pthread.m4
>
On Tue, 2018-04-17 at 22:50 +0100, Pedro Alves wrote:
> On 04/17/2018 06:24 PM, Joshua Watt wrote:
> > Ping? I'd really like to get this in binutils, which apparently
> > requires getting it here first.
>
> I think it would help if you mentioned what this is and
>
On Wed, Apr 18, 2018, 05:20 Pedro Alves wrote:
> On 04/17/2018 11:10 PM, Joshua Watt wrote:
> > On Tue, 2018-04-17 at 22:50 +0100, Pedro Alves wrote:
> >> On 04/17/2018 06:24 PM, Joshua Watt wrote:
> >>> Ping? I'd really like to get this in binutils, which a
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share sa
For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
and floating-point compare instructions, an illegal instruction
exception will be raised if the destination vector register overlaps
a source vector register group.
To handle this issue, we use "group_overlap" and "enabled" attribu
For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
and floating-point compare instructions, an illegal instruction
exception will be raised if the destination vector register overlaps
a source vector register group.
To handle this issue, we use "group_overlap" and "enabled" attribu
This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(BASE): Define new builtin bases.
* con
This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(BASE): Define new builtin bases.
* con
For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
and floating-point compare instructions, an illegal instruction
exception will be raised if the destination vector register overlaps
a source vector register group.
To handle this issue, we add an attribute "spec_restriction" to di
This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(class th_extract): Define new builtin bases.
This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(class th_extract): Define new builtin bases.
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share sa
This patch series presents gcc implementation of the XTheadVector
extension [1].
[1] https://github.com/T-head-Semi/thead-extension-spec/
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not
This patch is to introduce basic XTheadVector support
(march string parsing and a test for __riscv_xtheadvector)
according to https://github.com/T-head-Semi/thead-extension-spec/
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse): Add new vendor extens
This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions. We only check the
prefix is 'v', so that no extra attribute is needed.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_asm_output_opcode):
Add new function to add assembl
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share sa
This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(class th_extract): Define new builtin bases.
For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
and floating-point compare instructions, an illegal instruction
exception will be raised if the destination vector register overlaps
a source vector register group.
To handle this issue, we add an attribute "spec_restriction" to di
There are some xtheadvector instructions that differ from RVV1.0
apart from simply adding "th." prefix. For example, RVV1.0
load/store instructions will have SEW while xtheadvector not;
RVV1.0 will have "o" for indexed-ordered store instructions while
xtheadvecotr not; xtheadvector and RVV1.0 have
This patch series presents gcc implementation of the XTheadVector
extension [1].
[1] https://github.com/T-head-Semi/thead-extension-spec/
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not
This patch moves the definition of the enums lst_type and
frm_op_type into riscv-vector-builtins-bases.h and removes
the static visibility of fold_fault_load(), so these
can be used in other compile units.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (enum lst_type):
This patch splits the definition of csr_operand in predicates.md.
The newly defined vector_csr_operand has the same functionality
as csr_operand but can only be used in vector patterns, so that
changes for vector will not affect scalar patterns in files
like riscv.md.
gcc/ChangeLog:
* con
This patch is to introduce basic XTheadVector support
(march string parsing and a test for __riscv_xtheadvector)
according to https://github.com/T-head-Semi/thead-extension-spec/
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse): Add new vendor extens
This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions.
gcc/ChangeLog:
* config/riscv/riscv-protos.h
(riscv_asm_output_opcode): New function.
* config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
* config/ri
This patch only involves the generation of xtheadvector
special load/store instructions and vext instructions.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class th_loadstore_width): Define new builtin bases.
(BASE): Define new builtin bases.
* con
This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions. In this version, we
follow Kito's suggestions and only check the prefix is 'v', so that
no extra attribute is needed.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_asm_output
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share sa
tract, none_preds, iu_x_s_u_ops)
+#undef REQUIRED_EXTENSIONS
+
+#undef DEF_RVV_FUNCTION
diff --git a/gcc/config/riscv/thead-vector-builtins.cc
b/gcc/config/riscv/thead-vector-builtins.cc
new file mode 100644
index 000..c0002f255ee
--- /dev/null
+++ b/gcc/config/riscv/thead-vector-builtins.cc
This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions. In this version, we
follow Kito's suggestions and only check the prefix is 'v', so that
no extra attribute is needed.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_asm_output
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share sa
h, th_indexed_loadstore_width, none_m_preds,
iu16_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsuxw, th_indexed_loadstore_width, none_m_preds,
iu32_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vext_x_v, th_extract, none_preds, iu_x_s_u_ops)
+#undef REQUIRED_EXTENSIONS
+
+#undef DEF_RVV_FUNCTION
This patch series presents gcc implementation of the XTheadVector
extension [1].
[1] https://github.com/T-head-Semi/thead-extension-spec/
For some vector patterns that cannot be avoided, we use
"!TARGET_XTHEADVECTOR" to disable them in order not to
generate instructions that xtheadvector does not
This patch moves the definition of the enums lst_type and
frm_op_type into riscv-vector-builtins-bases.h and removes
the static visibility of fold_fault_load(), so these
can be used in other compile units.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (enum lst_type):
This patch use vector_length_operand instead of csr_operand for
vsetvl patterns, so that changes for vector will not affect scalar
patterns using csr_operand in riscv.md.
gcc/ChangeLog:
* config/riscv/vector.md:
Use vector_length_operand for vsetvl patterns.
Co-authored-by: Jin M
This patch use vector_length_operand instead of csr_operand for
vsetvl patterns, so that changes for vector will not affect scalar
patterns using csr_operand in riscv.md.
gcc/ChangeLog:
* config/riscv/vector.md:
Use vector_length_operand for vsetvl patterns.
Co-authored-by: Jin M
This patch is to introduce basic XTheadVector support
(march string parsing and a test for __riscv_xtheadvector)
according to https://github.com/T-head-Semi/thead-extension-spec/
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse): Add new vendor extens
This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions. We only check the
prefix is 'v', so that no extra attribute is needed.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_asm_output_opcode):
New function to add assembler
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share sa
h, th_indexed_loadstore_width, none_m_preds,
iu16_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsuxw, th_indexed_loadstore_width, none_m_preds,
iu32_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vext_x_v, th_extract, none_preds, iu_x_s_u_ops)
+#undef REQUIRED_EXTENSIONS
+
+#undef DEF_RVV_FUNCTION
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share sa
For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
and floating-point compare instructions, an illegal instruction
exception will be raised if the destination vector register overlaps
a source vector register group.
To handle this issue, we use "group_overlap" and "enabled" attribu
There are some xtheadvector instructions that differ from RVV1.0
apart from simply adding "th." prefix. For example, RVV1.0
load/store instructions will have SEW while xtheadvector not;
RVV1.0 will have "o" for indexed-ordered store instructions while
xtheadvecotr not; xtheadvector and RVV1.0 have
This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions. We only check the
prefix is 'v', so that no extra attribute is needed.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_asm_output_opcode):
New function to add assembler i
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share sa
For th.vmadc/th.vmsbc as well as narrowing arithmetic instructions
and floating-point compare instructions, an illegal instruction
exception will be raised if the destination vector register overlaps
a source vector register group.
To handle this issue, we use "group_overlap" and "enabled" attribu
There are some xtheadvector instructions that differ from RVV1.0
apart from simply adding "th." prefix. For example, RVV1.0
load/store instructions will have SEW while xtheadvector not;
RVV1.0 will have "o" for indexed-ordered store instructions while
xtheadvecotr not; xtheadvector and RVV1.0 have
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share sa
h, th_indexed_loadstore_width, none_m_preds,
iu16_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vsuxw, th_indexed_loadstore_width, none_m_preds,
iu32_v_scalar_ptr_index_ops)
+DEF_RVV_FUNCTION (th_vext_x_v, th_extract, none_preds, iu_x_s_u_ops)
+#undef REQUIRED_EXTENSIONS
+
+#undef DEF_RVV_FUNCTION
This patch is to introduce basic XTheadVector support
(march string parsing and a test for __riscv_xtheadvector)
according to https://github.com/T-head-Semi/thead-extension-spec/
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse): Add new vendor extens
This patch is to handle the differences in instruction generation
between Vector and XTheadVector. In this version, we only support
partial xtheadvector instructions that leverage directly from current
RVV1.0 with simple adding "th." prefix. For different name xtheadvector
instructions but share sa
This patch series presents gcc implementation of the XTheadVector
extension [1].
[1] https://github.com/T-head-Semi/thead-extension-spec/
Contributors:
Jun Sha (Joshua)
Jin Ma
RISC-V: minimal support for xtheadvector
RISC-V: Handle differences between xtheadvector and vector
This patch is to introduce basic XTheadVector support
(march string parsing and a test for __riscv_xtheadvector)
according to https://github.com/T-head-Semi/thead-extension-spec/
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc
(riscv_subset_list::parse): : Add new vendor exte
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