This patch adds th. prefix to all XTheadVector instructions by
implementing new assembly output functions.
gcc/ChangeLog:
* config/riscv/riscv-protos.h
(riscv_asm_output_opcode): New function.
* config/riscv/riscv.cc (riscv_asm_output_opcode): Likewise.
* config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Likewise.
Co-authored-by: Jin Ma <[email protected]>
Co-authored-by: Xianmiao Qu <[email protected]>
Co-authored-by: Christoph Müllner <[email protected]>
---
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv.cc | 26 +++++++++++++++++++
gcc/config/riscv/riscv.h | 4 +++
.../riscv/rvv/xtheadvector/prefix.c | 12 +++++++++
4 files changed, 43 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index eaee53ce94e..f0eee71a18a 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -101,6 +101,7 @@ struct riscv_address_info {
};
/* Routines implemented in riscv.cc. */
+extern void riscv_asm_output_opcode(FILE *asm_out_file, const char *p);
extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
extern int riscv_float_const_rtx_index_for_fli (rtx);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8ae65760b6e..d3010bed8d8 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5595,6 +5595,32 @@ riscv_get_v_regno_alignment (machine_mode mode)
return lmul;
}
+void
+riscv_asm_output_opcode(FILE *asm_out_file, const char *p)
+{
+ if (!TARGET_XTHEADVECTOR)
+ return;
+
+ if (current_output_insn == NULL_RTX)
+ return;
+
+ /* We need to handle the 'vset' special case here since it cannot
+ be controlled by vector mode. */
+ if (!strncmp (p, "vset", 4))
+ {
+ fputs ("th.", asm_out_file);
+ return;
+ }
+
+ subrtx_iterator::array_type array;
+ FOR_EACH_SUBRTX (iter, array, PATTERN (current_output_insn), ALL)
+ if (*iter && riscv_v_ext_mode_p (GET_MODE (*iter)) && p[0] == 'v')
+ {
+ fputs ("th.", asm_out_file);
+ return;
+ }
+}
+
/* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are:
'h' Print the high-part relocation associated with OP, after stripping
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 6df9ec73c5e..7bb9c9ee408 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -826,6 +826,10 @@ extern enum riscv_cc get_riscv_cc (const rtx use);
asm_fprintf ((FILE), "%U%s", (NAME)); \
} while (0)
+#undef ASM_OUTPUT_OPCODE
+#define ASM_OUTPUT_OPCODE(STREAM, PTR) \
+ riscv_asm_output_opcode(STREAM, PTR)
+
#define JUMP_TABLES_IN_TEXT_SECTION 0
#define CASE_VECTOR_MODE SImode
#define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
new file mode 100644
index 00000000000..48867f4ddfb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32 -O0" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+prefix (vint32m1_t vx, vint32m1_t vy, size_t vl)
+{
+ return __riscv_vadd_vv_i32m1 (vx, vy, vl);
+}
+
+/* { dg-final { scan-assembler {\mth\.v\M} } } */
\ No newline at end of file
--
2.17.1
