When pass split2 starts, which_alternative is random depending on
last set of certain pass.
Even initialized, the generated movement is redundant.
The movement can be generated by assembly output template.
Signed-off-by: demin.han
gcc/ChangeLog:
* config/riscv/autovec.md: Delete which_
Sorry for not consider rv32 config.
The fix is OK. If convenient, please commit it.
On 2023/7/28 4:46, Patrick O'Neill wrote:
> The newly added testcase fails on rv32 targets with this message:
> FAIL: gcc.target/riscv/rvv/autovec/madd-split2-1.c -O3 -ftree-vectorize (test
> for excess errors)
>
Sorry for the unexpected truncation.
Hi,
vf and vx are not supported well when comparing vector and
immediate in current autovec.
For example, following insts generated for float type:
flw
vsetvli
vfmv.v.f
...
vmfxx.vv
Two issues:
1. Additional vsetvl and vfmv instructions
patterns. I think they are equal.
From: 钟居哲
Sent: 2024年3月1日 15:24
To: Demin Han ; gcc-patches
Cc: kito.cheng ; Li, Pan2 ;
jeffreyalaw ; Robin Dapp
Subject: Re:[PATCH 1/5] RISC-V: Remove float vector eqne pattern
Hello, han. Thanks for trying to optimize the codes.
But I believe those vector
Sent: 2024年3月1日 15:49
To: Demin Han ; gcc-patches
Cc: kito.cheng ; Li, Pan2 ;
jeffreyalaw ; Robin Dapp ;
richard.sandiford
Subject: Re:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec
and imm
Hi, han. I understand you are trying to support optimize vector-splat_vector
into
Hi,
I applied the mentioned last_combine
patch(https://patchwork.ozlabs.org/project/gcc/patch/mptbka7em9w@arm.com/).
And did some initial tests.
Found that:
1. Float vector-scalar and vector-imm are OK
2. Integer vector-scalar is OK
3. Integer vector-imm(e.g. a[i] > 16) is
OK, I will solve the comparison operation first and then do some check over
other operations.
Regards,
Demin
From: juzhe.zh...@rivai.ai
Sent: 2024年3月5日 17:02
To: Demin Han ; gcc-patches
Cc: kito.cheng ; pan2.li ; jeffreyalaw
; Robin Dapp ; richard.sandiford
Subject: Re: RE:[PATCH 3/5
Hi,
I will commit the patch you mentioned with [NFC] added.
And split and resubmit other patches after more check and discussion.
Regards,
Demin
From: juzhe.zh...@rivai.ai
Sent: 2024年3月6日 10:13
To: Demin Han ; gcc-patches
Cc: kito.cheng
Subject: Re: [PATCH] MAINTAINERS: Add myself to write
OK.
Which is better for testcase name?
1. ice-biggestmode.c or
2. Report a bug and name the testcase with PR id
From: juzhe.zh...@rivai.ai
Sent: 2024年3月7日 15:20
To: Demin Han ; gcc-patches
Cc: kito.cheng ; pan2.li ; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Fix ICE in riscv vector
Hi,
the point starts from 1. the max_point should equal to length();
Should I prepare an individual patch for this?
From: juzhe.zh...@rivai.ai
Sent: 2024年3月28日 18:45
To: Demin Han ; gcc-patches
Cc: kito.cheng ; pan2.li ; jeffreyalaw
; Robin Dapp
Subject: Re: [PATCH] RISC-V: Refine the
OK，I will spilt them.
Thanks.
From: juzhe.zh...@rivai.ai
Sent: 2024年3月28日 19:11
To: Demin Han ; gcc-patches
Cc: kito.cheng ; pan2.li ; jeffreyalaw
; Robin Dapp
Subject: 回复: RE: [PATCH] RISC-V: Refine the condition for add additional vars
in RVV cost model
OK. It's an obvious fix b
Some toolchain configs would report:
fatal error: gnu/stubs-ilp32.h: No such file or directory
Fix method suggested by Juzhe-Zhong
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/riscv_vector.h: New file.
Signed-off-by: demin.han
---
.../gcc.dg/vect/costmodel/riscv/rvv/
For the stmt _1 = _2 + _3, assume that _2 or _3 not used after this stmt.
_1 can use same register with _2 or _3 if without early clobber.
Two registers are needed, but current calculation is three.
This patch preserves point 0 for bb entry and excludes its def when
calculates live regs of certain
Hi juzhe,
The live ranges are represented as [def_point, last_use_point] in code.
For example:
0: _2 = _x1 + _x2
1: _3 = _y1 + _y2
2: _1 = _2 + _3
3: _4 = _1 + x1
Origin:
live ranges:
_1: [2, 3]
_2: [0, 2]
_3: [1, 2]
_x1:[0, 3]
max live regs calc:
_1 _2 _3 _x1
0 x x
1 x
Hi Jeff,
Thanks for reminding this.
Regression test info will be added to commit log in following patches.
Demin
On 2023/12/20 23:28, Jeff Law wrote:
>
>
> On 12/20/23 04:17, juzhe.zh...@rivai.ai wrote:
>> I see. LGTM. Thanks for explanation.
>>
>> I will ask Li Pan commit it for you.
> The pa
These two tests depend on -mabi.
Other toolchain configs would report:
fatal error: gnu/stubs-ilp32.h: No such file or directory
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c: Fix abi issue
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c: Dit
These two tests depend on -mabi.
Other toolchain configs would report:
fatal error: gnu/stubs-ilp32.h: No such file or directory
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c: Fix abi issue
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-4.c: Dit
Thanks for the suggestion.
The target selector method can not cover some cases.
On 2023/12/12 18:05, juzhe.zh...@rivai.ai wrote:
> A more reasonable solution is the add riscv_vector.h into
> gcc.dg/vect/costmodel/riscv/rvv
> with the following codes in riscv_vector.h:
>
> /* Wrapper of riscv_ve
> > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> > index d5793acc999..a772153 100644
> > --- a/gcc/config/riscv/autovec.md
> > +++ b/gcc/config/riscv/autovec.md
> > @@ -690,7 +690,7 @@ (define_expand "vec_cmp"
> > [(set (match_operand: 0 "register_operand")
> >
> -Original Message-
> From: Robin Dapp
> Sent: 2024年7月17日 22:43
> To: Demin Han ; gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; pan2...@intel.com;
> jeffreya...@gmail.com
> Subject: Re: [PATCH] RISC-V: More support of vx and vf for
> -Original Message-
> From: Li, Pan2
> Sent: 2024年7月19日 18:33
> To: Demin Han ; gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com;
> rdapp@gmail.com
> Subject: RE: [PATCH v2] RISC-V: More support of vx and vf for
Hi Robin,
Yes.
Can eqne pattern removal patches be committed firstly?
Regards,
Demin
> -Original Message-
> From: Robin Dapp
> Sent: 2024年5月16日 3:49
> To: Demin Han ; 钟居哲
> ; gcc-patches
> Cc: rdapp@gmail.com; kito.cheng ; Li, Pan2
> ; jeffreyalaw
> Subje
/
Regards,
Demin
From: 钟居哲
Sent: 2024年5月16日 10:02
To: Robin Dapp ; Demin Han ;
gcc-patches
Cc: rdapp.gcc ; kito.cheng ; Li,
Pan2 ; jeffreyalaw
Subject: Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
Would you minding sending this patch again？
I can not find the patch now
: Demin Han ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; pan2...@intel.com;
rdapp@gmail.com
Subject: Re: [PATCH] RISC-V: Fix double mode under RV32 not utilize vf
On Fri, Jul 19, 2024 at 12:07 PM Jeff Law
mailto:jeffreya...@gmail.com>> wrote:
On 7/19/24 2
Hi，
I‘m on vacation rencently.
I will return in a few days and summit new patch with the test.
Regards，
Demin
发件人: Jeff Law
发送时间: 星期一, 六月 10, 2024 9:49 下午
收件人: Robin Dapp ; Demin Han ;
钟居哲 ; gcc-patches
抄送: kito.cheng ; Li, Pan2
主题: Re: [PATCH 1/5] RISC
Hi Jeff,
Thanks for fixing that.
Regards,
Demin
> -Original Message-
> From: Jeff Law
> Sent: 2024年6月19日 22:33
> To: Demin Han ; gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; pan2...@intel.com;
> rdapp@gmail.com
> Subject: Re: [PAT
Hi, Juzhe.
Thanks for reminding.
I did regression again and committed.
Regard,
Demin
From: juzhe.zh...@rivai.ai
Sent: 2024年4月29日 13:10
To: Demin Han ; gcc-patches
Cc: kito.cheng ; pan2.li ; jeffreyalaw
; Robin Dapp
Subject: Re: [PATCH v2] RISC-V: Refine the condition for add additional vars
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