> > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> > index d5793acc999..a7111172153 100644
> > --- a/gcc/config/riscv/autovec.md
> > +++ b/gcc/config/riscv/autovec.md
> > @@ -690,7 +690,7 @@ (define_expand "vec_cmp<mode><vm>"
> > [(set (match_operand:<VM> 0 "register_operand")
> > (match_operator:<VM> 1 "comparison_operator"
> > [(match_operand:V_VLSF 2 "register_operand")
> > - (match_operand:V_VLSF 3 "register_operand")]))]
> > + (match_operand:V_VLSF 3 "nonmemory_operand")]))]
> Note this may be too loose. Do we really want to allow any non-memory
> operand or are you just trying to allow a few additional constants?
>
> If the latter, then we should create a suitable predicate that allows a
> register
> or just that set of constants rather than using nonmemory_operand.
Register or any const vector are allowed.
Same with integer conterpart:
(define_expand "vec_cmpu<mode><vm>"
[(set (match_operand:<VM> 0 "register_operand")
(match_operator:<VM> 1 "comparison_operator"
[(match_operand:V_VLSI 2 "register_operand")
(match_operand:V_VLSI 3 "nonmemory_operand")]))]
"TARGET_VECTOR"
{
riscv_vector::expand_vec_cmp (operands[0], GET_CODE (operands[1]),
operands[2], operands[3]);
DONE;
}
)
> Robin may have further comments.
>
> jeff
Demin
