The function `reconcat` cannot append string(s) to NULL,
as the concat process will stop at the first NULL.
Let's initialize `ret` with `concat (" ", NULL)`, then
it can be used by reconcat.
gcc/
PR target/112759
* config/mips/driver-native.cc (host_detect_local_cpu):
ini
For reconcat, if the `optr` can only be used as the last one
of string list, aka, we cannot append something to it.
Let's add some note into the document.
libiberty:
* concat.c (reconcat): Add note about append string to NULL
into document.
---
libiberty/concat.c | 3 +++
1 file c
Jakub Jelinek 于2023年12月18日周一 16:10写道：
>
> On Mon, Dec 18, 2023 at 11:44:21AM +0800, YunQiang Su wrote:
> > The function `reconcat` cannot append string(s) to NULL,
> > as the concat process will stop at the first NULL.
> >
> > Let's initialize `ret` with `conc
The function `reconcat` cannot append string(s) to NULL,
as the concat process will stop at the first NULL.
Let's always put the `ret` to the end, as it may be NULL.
We keep use reconcat here, due to that reconcat can make it
easier if we add more hardware features detecting, for example
by hwcap.
"&& reload_completed && register_operand (operands[1], VOIDmode)"
[(const_int 0)]
{
emit_note (NOTE_INSN_DELETED);
DONE;
}
[(set_attr "move_type" "move,move,load")
(set_attr "mode" "DI")])
--
YunQiang Su
fine TRULY_NOOP_TRUNCATION.
>
> Where is the subreg being generated?
>
It's from expand_assignment(tree to, tree from, bool nontemporal) in expr.cc.
to_rtx = expand_expr (tem, NULL_RTX, VOIDmode, EXPAND_WRITE);
--
YunQiang Su
Jakub Jelinek 于2023年12月19日周二 16:40写道：
>
> On Tue, Dec 19, 2023 at 09:30:49AM +0800, YunQiang Su wrote:
> > The function `reconcat` cannot append string(s) to NULL,
> > as the concat process will stop at the first NULL.
> >
> > Let's always put the `ret` to the
The function `reconcat` cannot append string(s) to NULL,
as the concat process will stop at the first NULL.
Let's always put the `ret` to the end, as it may be NULL.
We keep use reconcat here, due to that reconcat can make it
easier if we add more hardware features detecting, for example
by hwcap.
Users may wish just use -mtune=native for performance tuning only.
Let's don't make trouble for its case.
gcc/
* config/mips/driver-native.cc (host_detect_local_cpu):
don't add nan2008 option for -mtune=native.
---
gcc/config/mips/driver-native.cc | 3 ++-
1 file changed, 2 inser
On TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true platforms,
if 31 or above bits is polluted by an bitops, we will need an
truncate. Let's emit one, and mark let's use the same hardreg
as in and out, the RTL may like:
(insn 21 20 24 2 (set (subreg/s/u:SI (reg/v:DI 200 [ val ]) 0)
Jeff Law 于2023年12月24日周日 00:51写道：
>
>
>
> On 12/23/23 01:58, YunQiang Su wrote:
> > On TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true platforms,
> > if 31 or above bits is polluted by an bitops, we will need an
> > truncate. Let's emit one, and mark l
> > Yes. I also guess so. Any new idea?
> Well, I see multiple intertwined issues and I think MIPS has largely
> mucked this up.
>
> At a high level DI -> SI truncation is not a nop on MIPS64. We must
> explicitly sign extend the value from SI->DI to preserve the invariant
> that SI mode objects
Roger Sayle 于2023年12月24日周日 08:49写道：
>
>
> Hi YunQiang (and Jeff),
>
> > MIPS claims TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true
> > based on that the hard register is always sign-extended, but here
> > the hard register is polluted by zero_extract.
>
> I suspect that the bug here is th
Roger Sayle 于2023年12月24日周日 16:51写道：
>
>
> > What's exceedingly weird is T_N_T_M_P (DImode, SImode) isn't actually a
> > truncation! The output precision is first, the input precision is second.
> > The docs
> > explicitly state the output precision should be smaller than the input
> > precisio
MIPS backend had some information about INSN, including length,
count etc.
And since some instructions are more costly, let's add a new
attr `perf_ratio`. It's default value is (const_int 1).
The return value of mips_insn_cost is
insn_count * perf_ratio * 4.
The magic `4` here, is due to that
Jeff Law 于2023年12月29日周五 02:23写道：
>
>
>
> On 12/28/23 07:59, Roger Sayle wrote:
> >
> > This patch fixes PR rtl-optmization/104914 by tweaking/improving the way
> > that fields are written into a pseudo register that needs to be kept sign
> > extended.
> Well, I think "fixes" is a bit of a stretch.
In general, I agree with this change.
When gcc12 on RV64, more than one `sext.w` will be produced with our test.
(Note, use -O1).
>
> There are two things that help here. The first is that the most significant
> bit never appears in the middle of a field, so we don't have to worry about
> overlap
Roger Sayle 于2023年12月29日周五 00:54写道：
>
>
>
> The current (default) behavior is that when the target doesn’t define
>
> TARGET_INSN_COST the middle-end uses the backend’s
>
> TARGET_RTX_COSTS, so multiplications are slower than additions,
>
> but about the same size when optimizing for size (with -O
This match pattern allows combination (zero_extract:DI 8, 24, QI)
with an sign-extend to 32bit INS instruction on TARGET_64BIT.
The problem is that, for SI mode, if the sign-bit is modified by
bitops, we will need a sign-extend operation.
Since 32bit INS instruction can be sure that result is sign
The accurate cost of an pattern can get with
insn_count * perf_ratio
The default value is set to 0 instead of 1, since that
we will need to distinguish the default value and it is
really set for an pattern. Since it is not set for most
patterns yet, to use it, we will need to be sure tha
This match pattern allows combination (zero_extract:DI 8, 24, QI)
with an sign-extend to 32bit INS instruction on TARGET_64BIT.
The problem is that, for SI mode, if the sign-bit is modified by
bitops, we will need a sign-extend operation.
Since 32bit INS instruction can be sure that result is sign
The accurate cost of an pattern can get with
insn_count * perf_ratio
The default value is set to 0 instead of 1, since that
we will need to distinguish the default value and it is
really set for an pattern. Since it is not set for most
patterns yet, to use it, we will need to be sure tha
When we try to combine RTLs, the result may be very complex,
and `rtx_cost` may think that it need lots of costs. But in
fact, it may match a pattern in machine descriptions, which
may emit only 1 or 2 hardware instructions. This combination
may be refused due to cost comparison failure.
Since th
When combine some instructions, the generic `rtx_cost`
may over estimate the cost of result RTL, due to that
the RTL may be quite complex and `rtx_cost` has no
information that this RTL can be convert to simple
hardware instruction(s).
In this case, Let's use `get_attr_insn_count` to estimate
the
This match pattern allows combination (zero_extract:DI 8, 24, QI)
with an sign-extend to 32bit INS instruction on TARGET_64BIT.
For SI mode, if the sign-bit is modified by bitops, we will need a
sign-extend operation. Since 32bit INS instruction can be sure that
result is sign-extended, and the Q
> Right. But that's the whole point behind avoiding the narrowing subreg
> and forcing use of a truncate operation.
>
> So basically the question becomes is there a way to modify those bits in
> a way that GCC doesn't know that it needs to to truncate/extend?
>
I guess that this code may cause so
make: *** No rule to make target 'check-g++'. Stop.
gcc
* doc/install.texi (Testing): Correct check-g++ to
check-gcc-c++.
---
gcc/doc/install.texi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
index d20b43
Richard Sandiford 于2023年12月30日周六 23:35写道：
>
> Ping^3
>
I am testing it on MIPS.
> --- a/gcc/common/config/aarch64/aarch64-common.cc
> +++ b/gcc/common/config/aarch64/aarch64-common.cc
> @@ -55,6 +55,7 @@ static const struct default_options
> aarch_option_optimization_table[] =
> { OPT_LEVE
When building multilib libraries, CC/CXX etc are set with an option
-B*/lib/, instead of -B/lib/.
This will make some trouble in some case, for example building
cross toolchain based on Debian's cross packages:
If we have libc6-dev-i386-amd64-cross packages installed on
a non-x86 machine. This
The accurate cost of an pattern can get with
insn_count * perf_ratio
The default value is set to 0 instead of 1, since that
we will need to distinguish the default value and it is
really set for an pattern. Since it is not set for most
patterns yet, to use it, we will need to be sure tha
When combine some instructions, the generic `rtx_cost`
may over estimate the cost of result RTL, due to that
the RTL may be quite complex and `rtx_cost` has no
information that this RTL can be convert to simple
hardware instruction(s).
In this case, Let's use `insn_count * perf_ratio` to
estimate
This match pattern allows combination (zero_extract:DI 8, 24, QI)
with an sign-extend to 32bit INS instruction on TARGET_64BIT.
For SI mode, if the sign-bit is modified by bitops, we will need a
sign-extend operation. Since 32bit INS instruction can be sure that
result is sign-extended, and the Q
gcc/testsuite
* gcc.c-torture/compile/mipscop-1.c: Include stdio.h.
* gcc.c-torture/compile/mipscop-2.c: Ditto.
* gcc.c-torture/compile/mipscop-3.c: Ditto.
* gcc.c-torture/compile/mipscop-4.c: Ditto.
---
gcc/testsuite/gcc.c-torture/compile/mipscop-1.c | 1 +
gcc/te
I have tested this patch on mips64el: No regression.
For cross building with option:
--sysroot=/ --prefix=/usr --includedir=/usr/
just like Debian does, fixinc.sh will use the wrong header files
from /usr/include.
gcc/
* Makefile.in (CROSS_SYSTEM_HEADER_DIR): set according the
value of includedir.
---
gcc/Makefile.in | 6 +-
-D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 is always used for mips
when build libsanitizer in LLVM. Thus
FIRST_32_SECOND_64((_MIPS_SIM == _ABIN32) ? 176 : 160, 216);
instead of
FIRST_32_SECOND_64((_MIPS_SIM == _ABIN32) ? 160 : 144, 216);
in sanitizer_platform_limits_posix.h.
To keep sync wit
Hans-Peter Nilsson 于2023年1月11日周三 08:53写道：
>
> On Fri, 6 Jan 2023, YunQiang Su wrote:
>
> > -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 is always used for mips
> > when build libsanitizer in LLVM. Thus
> >FIRST_32_SECOND_64((_MIPS_SIM == _ABIN32) ? 176
On most hardware, FCSR.ABS2008 is set the value same with FCSR.NAN2008.
Let's use this behaivor by default in GCC, aka
gcc -mnan=2008 -c fabs.c
will imply `-mabs=2008`.
And of course, `gcc -mnan=2008 -mabs=legacy` can continue workable
like previous.
gcc/ChangeLog
* config/mips/m
Schwab
m68k-motorola-sysv portPhilippe De Muyter
mcore port Nick Clifton
microblaze Michael Eager
-mips port YunQiang Su
+mips port YunQiang Su
mmix port Hans-Peter
;;
> mipsisa64r2*)
> - tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64R2
> MIPS_ABI_DEFAULT=ABI_N32"
> + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64R2
> MIPS_ABI_DEFAULT=ABI_N32"
> ;;
> mipsisa64*)
> - tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64
> MIPS_ABI_DEFAULT=ABI_N32"
> + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64
> MIPS_ABI_DEFAULT=ABI_N32"
> ;;
> esac
> ;;
>
> Jakub
>
--
YunQiang Su
Maciej W. Rozycki 于2024年6月27日周四 00:07写道：
>
> On Thu, 20 Jun 2024, YunQiang Su wrote:
>
> > MIPSr6 removes condition trap instructions with imm, so the instruction
> > like `teq $2,imm` will be converted to
> > li $at, imm
> > teq $2, $at
> >
> > Th
Maciej W. Rozycki 于2024年6月28日周五 01:01写道：
>
> On Thu, 27 Jun 2024, YunQiang Su wrote:
>
> > > The missed optimisation in GAS, which used not to trigger pre-R6, is
> > > irrelevant from this change's point of view and just adds noise. I'm
> > > surpri
BNEGI.W/D are used for test7_v2f64 and test7_v4f32 now. It is
an improvment since that we can save a instruction.
ILVR.D is used for test43_v2i64 now, instead of INSVE.D.
gcc/testsuite
gcc.target/mips/msa.c: Fix test7_v2f64, test7_v4f32 and
test43_v2i64.
---
gcc/testsuite/gcc.ta
Currently, we support the cases that strictly fit for the instructions.
For example, for V16QImode, we only support shuffle like
(0<=N0, N1, N2, N3<=3 here)
N0, N1, N2, N3
N0+4N1+4N2+4, N3+4
N0+8N1+8N2+8, N3+8
N0+12 N1+12 N2+12, N
The scan-assembler-times rules only fit for -mfp32 and -mfpxx.
It fails if we are configured as FP64 by default, as it has
one less sdc1/ldc1 pair.
gcc/testsuite
* gcc.target/mips/call-clobbered-1.c: Add -mfpxx.
---
gcc/testsuite/gcc.target/mips/call-clobbered-1.c | 2 +-
1 file changed,
With some recent optimization, -O1/-O2/-O3 can archive almost same
performace/size by stack load/store. Thus lwm/swm will save/store
less callee-saved register. In fact only $16 is saved with swm.
To be sure that this optimization does exist, let's add 2 more
function calls. So that lwm/swm can
We have done so for MIPSr6, which removes the support of condtional
trap with IMM. To be consistent, Let's do so for pre-R6.
We also add 2 new tests
1) be sure that $0 is used.
2) be sure we expand the condtional trap compare with constant,
instead of leaving it to GAS.
We decide to so so for
Ping again.
From: YunQiang Su
PR target/115840.
In riscv_preferred_else_value, we create an uninitialized tmp var
for else value, instead of the 0 (as default_preferred_else_value)
or the pre-exists VAR (as aarch64 does), so that we can use agnostic
policy.
The problem is that `warn_uninit` will emit a
From: YunQiang Su
Uninitialized internal temp variable may be useful in some case,
such as for COND_LEN_MUL etc on RISC-V with V extension: If an
const or pre-exists VAR is used, we have to use "undisturbed"
policy; if an uninitialized VAR is used, we can use "agnostic".
From: YunQiang Su
PR target/115840.
In riscv_preferred_else_value, we create an uninitialized tmp var
for else value, instead of the 0 (as default_preferred_else_value)
or the pre-exists VAR (as aarch64 does), so that we can use agnostic
policy.
The problem is that `warn_uninit` will emit a
Richard Biener 于2024年7月11日周四 20:21写道：
>
> On Thu, Jul 11, 2024 at 2:13 PM YunQiang Su wrote:
> >
> > From: YunQiang Su
> >
> > PR target/115840.
> >
> > In riscv_preferred_else_value, we create an uninitialized tmp var
> > for else value, i
PR target/113955
The `-mlra` option was introduced in 2014 for MIPS, and was set to
default since then. It's time for us to drop no-lra support by
dropping -m(no-)lra options.
gcc:
* config/mips/mips.cc(mips_option_override):
Drop mips_lra_flag variable;
(mips_lra_p): Remo
If `find_a_program` cannot find `as/ld` and we are a cross toolchain,
the final fallback is `as/ld` of system. In fact, we can have a try
with -as/ld before fallback to native as/ld.
This patch is derivatived from Debian's patch:
gcc-search-prefixed-as-ld.diff
gcc
* gcc.cc(execute): Lo
Andrew Pinski 于2024年5月21日周二 20:23写道：
>
> On Tue, May 21, 2024 at 5:12 AM YunQiang Su wrote:
> >
> > If `find_a_program` cannot find `as/ld` and we are a cross toolchain,
> > the final fallback is `as/ld` of system. In fact, we can have a try
> > with -as/ld b
ision (pp, *text->m_args_ptr, precision,
> + int, "d");
> break;
>
> case 'o':
> @@ -1579,8 +1614,8 @@ pp_format (pretty_printer *pp,
> pp_scalar (pp, "%" HOST_WIDE_INT_PRINT "o",
>va_arg (*text->m_args_ptr, unsigned HOST_WIDE_INT));
> else
> - pp_integer_with_precision
> - (pp, *text->m_args_ptr, precision, unsigned, "o");
> + pp_integer_with_precision (pp, *text->m_args_ptr, precision,
> + unsigned, "o");
> break;
>
> case 's':
> @@ -1599,8 +1634,8 @@ pp_format (pretty_printer *pp,
> pp_scalar (pp, HOST_WIDE_INT_PRINT_UNSIGNED,
>va_arg (*text->m_args_ptr, unsigned HOST_WIDE_INT));
> else
> - pp_integer_with_precision
> - (pp, *text->m_args_ptr, precision, unsigned, "u");
> + pp_integer_with_precision (pp, *text->m_args_ptr, precision,
> + unsigned, "u");
> break;
>
> case 'f':
> @@ -1629,8 +1664,8 @@ pp_format (pretty_printer *pp,
> pp_scalar (pp, HOST_WIDE_INT_PRINT_HEX,
>va_arg (*text->m_args_ptr, unsigned HOST_WIDE_INT));
> else
> - pp_integer_with_precision
> - (pp, *text->m_args_ptr, precision, unsigned, "x");
> + pp_integer_with_precision (pp, *text->m_args_ptr, precision,
> + unsigned, "x");
> break;
>
> case '.':
> @@ -2774,6 +2809,18 @@ test_pp_format ()
>ASSERT_PP_FORMAT_2 ("17 12345678", "%wo %x", (HOST_WIDE_INT)15,
> 0x12345678);
>ASSERT_PP_FORMAT_2 ("0xcafebabe 12345678", "%wx %x",
> (HOST_WIDE_INT)0xcafebabe,
> 0x12345678);
> + ASSERT_PP_FORMAT_2 ("-27 12345678", "%zd %x", (ssize_t)-27, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("-5 12345678", "%zi %x", (ssize_t)-5, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("10 12345678", "%zu %x", (size_t)10, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("17 12345678", "%zo %x", (size_t)15, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("cafebabe 12345678", "%zx %x", (size_t)0xcafebabe,
> + 0x12345678);
> + ASSERT_PP_FORMAT_2 ("-27 12345678", "%td %x", (ptrdiff_t)-27, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("-5 12345678", "%ti %x", (ptrdiff_t)-5, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("10 12345678", "%tu %x", (ptrdiff_t)10, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("17 12345678", "%to %x", (ptrdiff_t)15, 0x12345678);
> + ASSERT_PP_FORMAT_2 ("1afebabe 12345678", "%tx %x", (ptrdiff_t)0x1afebabe,
> + 0x12345678);
>ASSERT_PP_FORMAT_2 ("1.00 12345678", "%f %x", 1.0, 0x12345678);
>ASSERT_PP_FORMAT_2 ("A 12345678", "%c %x", 'A', 0x12345678);
>ASSERT_PP_FORMAT_2 ("hello world 12345678", "%s %x", "hello world",
>
> Jakub
>
--
YunQiang Su
Jakub Jelinek 于2024年5月22日周三 17:14写道：
>
> On Wed, May 22, 2024 at 05:05:30PM +0800, YunQiang Su wrote:
> > > --- gcc/gcc.cc.jj 2024-02-09 14:54:09.141489744 +0100
> > > +++ gcc/gcc.cc 2024-02-09 22:04:37.655678742 +0100
> > > @@ -2410,8 +2410,7 @@ read_sp
Jakub Jelinek 于2024年5月22日周三 17:33写道：
>
> On Wed, May 22, 2024 at 05:23:33PM +0800, YunQiang Su wrote:
> > Jakub Jelinek 于2024年5月22日周三 17:14写道：
> > >
> > > On Wed, May 22, 2024 at 05:05:30PM +0800, YunQiang Su wrote:
> > > > > --- gcc/gcc.cc
If `find_a_program` cannot find `as/ld/objcopy` and we are a cross toolchain,
the final fallback is `as/ld` of system. In fact, we can have a try with
-as/ld/objcopy before fallback to native as/ld/objcopy.
This patch is derivatived from Debian's patch:
gcc-search-prefixed-as-ld.diff
gcc
When looking for as/ld/objcopy, `find_a_program/file_at_path` only
try to find the raw name, but won't find the one with -
prefix.
This patch is derivatived from Debian's patch:
gcc-search-prefixed-as-ld.diff
gcc
* gcc.cc(for_each_path): Add more space for -.
(file_at_path): S
commit 05daf617ea22e1d818295ed2d037456937e23530
Author: Jeff Law
Date: Sat May 25 12:39:05 2024 -0600
[committed] [v2] More logical op simplifications in simplify-rtx.cc
does some simplifications, and then `bseli.b $w1,$w0,255` is found that
it is same with `or.v $w1,$w0,$w1`. So there wil
PR Target/84790.
The gp init sequence
li $2,%hi(_gp_disp)
addiu $3,$pc,%lo(_gp_disp)
sll $2,16
addu$2,$3
is generated directly in `mips_output_function_prologue`, and does
not appear in the RTL.
So the IRA/IPA passes are not aware that $2/$3 have been
YunQiang Su 于2024年5月22日周三 17:54写道：
>
> If `find_a_program` cannot find `as/ld/objcopy` and we are a cross toolchain,
> the final fallback is `as/ld` of system. In fact, we can have a try with
> -as/ld/objcopy before fallback to native as/ld/objcopy.
>
> This patch is derivat
Richard Sandiford 于2024年5月29日周三 05:28写道：
>
> YunQiang Su writes:
> > If `find_a_program` cannot find `as/ld/objcopy` and we are a cross
> > toolchain,
> > the final fallback is `as/ld` of system. In fact, we can have a try with
> > -as/ld/objcopy before fa
Kewen Lin 于2024年6月3日周一 11:03写道：
>
> This is to add new port specific hook implementation
> mips_c_mode_for_floating_type, remove macros FLOAT_TYPE_SIZE
> and DOUBLE_TYPE_SIZE, rename LONG_DOUBLE_TYPE_SIZE to
> MIPS_LONG_DOUBLE_TYPE_SIZE since we poison LONG_DOUBLE_TYPE_SIZE
> but some subtarget wa
YunQiang Su 于2024年7月5日周五 16:14写道：
>
> Ping again.
Ping.
mips16.S was missing since
commit 29b74545531f6afbee9fc38c267524326dbfbedf
Date: Thu Jun 1 10:14:24 2023 +0800
MIPS: Add speculation_barrier support
Without mips16.S included, some symbols will miss for mips16, and
so some software will fail to build.
libgcc/ChangeLog:
* config/mi
From: YunQiang Su
We have SHF.fmt and HADD_S/U.fmt with MSA, which can be used for
vector reduc.
For min/max for U8/S8, we can
SHF.B W1, W0, 0xb1 # swap byte inner every half
MIN.B W1, W1, W0
SHF.H W2, W1, 0xb1 # swap half inner every word
MIN.B W2, W2, W1
Victor Do Nascimento 于2024年8月28日周三 23:15写道：
>
> Hello,
>
> Gentle reminder for this simple renaming patch :)
>
Approved, but, it will be better if we can add a test case for it.
> Thanks,
> Victor
>
>
> On 8/15/24 09:44, Victor Do Nascimento wrote:
> > Following the migration of the dot_prod opt
Richard Sandiford 于2024年6月5日周三 22:14写道：
>
> YunQiang Su writes:
> > PR target/113179.
> >
> > In `store_bit_field_using_insv`, we just use SUBREG if value_mode
> >>= op_mode, while in some ports, a sign_extend will be needed,
> > such as MIPS64:
> >
Richard Sandiford 于2024年6月5日周三 23:20写道：
>
> YunQiang Su writes:
> > Richard Sandiford 于2024年6月5日周三 22:14写道：
> >>
> >> YunQiang Su writes:
> >> > PR target/113179.
> >> >
> >> > In `store_bit_field_using_insv`, we just
YunQiang Su 于2024年5月29日周三 10:02写道：
>
> Richard Sandiford 于2024年5月29日周三 05:28写道：
> >
> > YunQiang Su writes:
> > > If `find_a_program` cannot find `as/ld/objcopy` and we are a cross
> > > toolchain,
> > > the final fallback is `as/ld` of system.
*/
> + SLP_TREE_SCALAR_STMTS (res) = vNULL;
> + SLP_TREE_DEF_TYPE (res) = vect_uninitialized_def;
> + res->failed = XNEWVEC (bool, group_size);
> + memset (res->failed, 0, sizeof (bool) * group_size);
> + memset (matches, 0, sizeof (bool) * group_size);
> + return NULL;
> + }
> + --*limit;
> }
> - --*limit;
>
>if (dump_enabled_p ())
> dump_printf_loc (MSG_NOTE, vect_location,
> --
> 2.35.3
--
YunQiang Su
From: YunQiang Su
In mips_insn_cost, COSTS_N_INSNS is missing when we return the cost
if count * ratio > 0.
gcc
* config/mips/mips.cc(mips_insn_cost): Add missing COSTS_N_INSNS
to count.
---
gcc/config/mips/mips.cc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
LT/LE: c.lt.fmt/c.le.fmt on pre-R6 and cmp.lt.fmt/cmp.le.fmt have
different semantic:
c.lt.fmt will signal for all NaN, including qNaN;
cmp.lt.fmt will only signal sNaN, while not qNaN;
cmp.slt.fmt has the same semantic as c.lt.fmt;
lt/le of RTL will signaling qNaN.
while in `s__using_
In mips.cc(mips_reorg_process_insns), there is this claim:
Also delete cache barriers if the last instruction
was an annulled branch. INSN will not be speculatively
executed.
And with -O1 on mips64, we can generate binary code like this,
which fails this test.
gcc/testsuite
LT/LE: c.lt.fmt/c.le.fmt on pre-R6 and cmp.lt.fmt/cmp.le.fmt have
different semantic:
c.lt.fmt will signal for all NaN, including qNaN;
cmp.lt.fmt will only signal sNaN, while not qNaN;
cmp.slt.fmt has the same semantic as c.lt.fmt;
lt/le of RTL will signaling qNaN.
while in `s__using_
nk.
>
Sorry for the delay report. With this patch the test
gcc.target/mips/movcc-3.c fails.
> Jeff
--
YunQiang Su
YunQiang Su 于2024年6月9日周日 18:25写道：
>
> > >
> > > gcc/ChangeLog:
> > >
> > > * ifcvt.cc (cond_move_process_if_block):
> > > Consider the result of targetm.noce_conversion_profitable_p()
> > > when replacing the original se
HLIKELY_ALWAYS)
MIPS_CPU ("mips64r2", PROCESSOR_5KC, MIPS_ISA_MIPS64R2,
PTF_AVOID_BRANCHLIKELY_ALWAYS)
MIPS_CPU ("mips64r3", PROCESSOR_5KC, MIPS_ISA_MIPS64R3,
PTF_AVOID_BRANCHLIKELY_ALWAYS)
MIPS_CPU ("mips64r5", PROCESSOR_5KC, MIPS_ISA_MIPS64R5,
PTF_AVOID_BRANCHLIKELY_ALWAYS)
Here PROCESSOR_4KC and PROCESSOR_5KC are both FPU-less.
> Jeff
>
--
YunQiang Su
Richard Sandiford 于2024年6月6日周四 17:54写道：
>
> YunQiang Su writes:
> > YunQiang Su 于2024年5月29日周三 10:02写道：
> >>
> >> Richard Sandiford 于2024年5月29日周三 05:28写道：
> >> >
> >> > YunQiang Su writes:
> >> > > If `find_a_progra
Sam James 于2024年6月14日周五 09:02写道：
>
> Collin Funk writes:
>
> > When dlopen and pthread_create are in libc the variable is
> > set to "none required", therefore running configure will show
> > the following errors:
> >
> > ./configure: line 8997: test: too many arguments
> > ./configure: line 8999
PR 115416
When we build a cross toolchain, while without --with-sysroot,
target headers are expected in
${test_exec_prefix}/${target_noncanonical}/sys-include
while it is true only with --with-headers option is used. In other
cases, the path should be
${test_exec_prefix}/${target_noncanonical}
Xi Ruoyao 于2024年6月9日周日 21:50写道：
>
> A move/bstrins pair is as fast as a (addi.w|lu12i.w|lu32i.d|lu52i.d)/and
> pair, and twice fast as a srli/slli pair. When the src reg and the dst
Just want to know that why not adjust the RTX cost of bstrins vs srli/slli?
It may benefit more cases.
> reg happ
Richard Biener 于2024年6月6日周四 14:20写道：
>
> On Thu, 6 Jun 2024, YunQiang Su wrote:
>
> > Richard Biener 于2024年5月28日周二 17:47写道：
> > >
> > > The following avoids accounting single-lane SLP to the discovery
> > > limit. As the two testcases show this makes di
PR target/111376.
Currently, we are using LUI/ANDI/BEQZ for on-bit-test if the bitpos>=16,
while in fact we can use SLL/BGEZ.
Note:
1) if bitpos<16, we can use ANDI/BEQZ.
2) For R2+, we have EXT.
Known problems:
1. On some uarch, SLL has more delay, such as 74K:
See the talk in https://gcc
OK for trunk?
--
YunQiang Su
On most uarch, the cost condmove is same as other noraml integer,
and it should be COSTS_N_INSNS(1).
In GCC12 or previous, the condmove is always enabled, and from
GCC13, we start to compare the cost.
The generic rtx_cost give the result of COSTS_N_INSN(2).
Let's define it to COSTS_N_INSN(1) in m
MIPSr6 removes condition trap instructions with imm, so the instruction
like `teq $2,imm` will be converted to
li $at, imm
teq $2, $at
The current version of Gas cannot detect if imm is zero, and output
teq $2, $0
Let's do it in GCC.
gcc
* config/mips/mips.cc(mips_expand_conditional
Currently, we have `mips_expand_vec_cond_expr`, which calculate
cmp_res first. We can just add a new extra argument to ask it
to use operands[3] as cmp_res instead of calculating from operands[4]
and operands[5].
gcc
* config/mips/mips.cc(mips_expand_vec_cond_expr): Add extra
argu
Thanks. Sorry for the noise. I have reverted
8088374a868aacab4dff208ec3e3fde790a1d9a3
c6a9ab8c920f297c4efd289182aef9fbc73f5906
I will submit and back port the modification of gcc_cv_as_mips_explicit_relocs
separately.
@Collin Funk Can you sent a new correct/full patch?
We check gcc_cv_as_mips_explicit_relocs if gcc_cv_as_mips_explicit_relocs_pcrel
only, while gcc_cv_as_mips_explicit_relocs is used by later code.
Maybe, it is time for use to set gcc_cv_as_mips_explicit_relocs always now,
as it has been in Binutils for more than 20 years.
gcc
* configure.
Collin Funk 于2024年6月20日周四 07:40写道：
>
> I've just fixed the quotes and that typo in one patch. I hope you don't
> mind. When using Autoconf 2.69 and Automake 1.15.1 that copyright diff
> goes away. I'm not familiar with the gcc-autoregen bot but I think this
> should make it happy.
>
> -- >8 --
Maciej W. Rozycki 于2024年6月20日周四 01:24写道：
>
> On Wed, 19 Jun 2024, YunQiang Su wrote:
>
> > MIPSr6 removes condition trap instructions with imm, so the instruction
> > like `teq $2,imm` will be converted to
> > li $at, imm
> > teq $2, $at
> >
> > Th
MIPSr6 removes condition trap instructions with imm, so the instruction
like `teq $2,imm` will be converted to
li $at, imm
teq $2, $at
The current version of Gas cannot detect if imm is zero, and output
teq $2, $0
Let's do it in GCC.
gcc
* config/mips/mips.md(conditional_trap_reg):
YunQiang Su 于2024年6月20日周四 11:20写道：
>
> Maciej W. Rozycki 于2024年6月20日周四 01:24写道：
> >
> > On Wed, 19 Jun 2024, YunQiang Su wrote:
> >
> > > MIPSr6 removes condition trap instructions with imm, so the instruction
> > > like `teq $2,imm` will be converted
The DIV instructions of MIPS won't be trapped themself if the divisor
is zero. The compiler will emit a conditional trap instruct for it.
So the signal will be SIGTRAP instead of SIGFPE.
gcc/testsuite
* c-c++-common/ubsan/overflow-div-3.c: Use SIGTRAP for MIPS.
---
gcc/testsuite/c-c++-co
>
> Then GCC emits the wrong trap instruction, wherever it comes from and
> whatever has caused it. The correct ones for integer division by zero
Thanks so much. It is not the bug of Linux kernel or GCC.
It is a bug of me ;) and qemu.
Qemu didn't pass the code of TEQ correctly; and I haven't ru
Maciej W. Rozycki 于2024年6月21日周五 20:55写道：
>
> On Fri, 21 Jun 2024, Richard Sandiford wrote:
>
> > > We check gcc_cv_as_mips_explicit_relocs if
> > > gcc_cv_as_mips_explicit_relocs_pcrel
> > > only, while gcc_cv_as_mips_explicit_relocs is used by later code.
> > >
> > > Maybe, it is time for use to
Maciej W. Rozycki 于2024年6月21日周五 22:00写道：
>
> On Fri, 21 Jun 2024, Maciej W. Rozycki wrote:
>
> > > Yeah, agreed FWIW. This was necessary while the feature was relatively
> > > new, and while we still supported IRIX as, but I can't see any reasonable
> > > justification for using such an ancient b
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