Re: [PATCH v4] MIPS: add speculation_barrier support

YunQiang Su 于2023年5月12日周五 18:30写道： > > speculation_barrier for MIPS needs sync+jr.hb (r2+), > so we implement __speculation_barrier in libgcc, like arm32 does. > > gcc/ChangeLog: > * config/mips/mips-protos.h (mips_emit_speculation_barrier): New > prototyp

[PATCH v2 2/2] MIPS: Don't expand large unaligned block move

For large unaligned block move, lib call may have better performance than expanding. Let's just return, if length is larger than 64 on O32 larger than 128 on N32/N64. Here are some test results: CPU Aligned O32 N32 N64 Cavium 7130 1 72 192 1

[PATCH v2 1/2] MIPS: Use unaligned access to expand block_move on r6

MIPSr6 support unaligned memory access with normal lh/sh/lw/sw/ld/sd instructions, and thus lwl/lwr/ldl/ldr and swl/swr/sdl/sdr is removed. For microarchitecture, these memory access instructions issue 2 operation if the address is not aligned, which is like what lwl family do. For some situation

[PATCH v5] MIPS: Add speculation_barrier support

speculation_barrier for MIPS needs sync+jr.hb (r2+), so we implement __speculation_barrier in libgcc, like arm32 does. gcc/ChangeLog: * config/mips/mips-protos.h (mips_emit_speculation_barrier): New prototype. * config/mips/mips.cc (speculation_barrier_libfunc): New static

[COMMITTED] MAINTAINERS: Add myself as MIPS port maintainer

+mips port YunQiang Su mmix port Hans-Peter Nilsson mn10300 port Jeff Law mn10300 port Alexandre Oliva @@ -652,7 +652,6 @@ Basile Starynkevitch Jakub Staszak

[PATCH] MAINTAINERS: move Matthew Fortune to Write After Approval

In 4fe6e12204535545edf7f035d4dc79c1404058cf, I should have added Matthew Fortune to the Write After Approval section, while replacing the MIPS Maintainer position. ChangeLog: * MAINTAINERS (Write After Approval): move Matthew Fortune to Write After Approval. --- MAINTAINERS | 1 +

[RFC] Store_bit_field_1: Use mode of SUBREG instead of REG

PR #104914 When work with int val; ((unsigned char*)&val)[0] = *buf; The RTX mode is obtained from REG instead of SUBREG, which make D is used instead of . Thus something wrong happens on sign-extend default architectures, like MIPS64. gcc/ChangeLog: PR: 104914. * expmed.cc(st

Re: [RFC] Store_bit_field_1: Use mode of SUBREG instead of REG

> 2023年7月12日 15:44，Richard Biener 写道： > > On Wed, Jul 12, 2023 at 5:20 AM YunQiang Su wrote: >> >> PR #104914 >> >> When work with >> int val; >> ((unsigned char*)&val)[0] = *buf; >> The RTX mode is obtained from REG instead

[PATCH] Store_bit_field_1: Use SUBREG instead of REG if possible

PR #104914 When work with int val; ((unsigned char*)&val)[3] = *buf; if (val > 0) ... The RTX mode is obtained from REG instead of SUBREG, which make D is used instead of . Thus something wrong happens on sign-extend default architectures, like MIPS64. Let's use str_rtx and mode of str_rtx

[PATCH v2] Store_bit_field_1: Use SUBREG instead of REG if possible

PR #104914 When work with int val; ((unsigned char*)&val)[3] = *buf; if (val > 0) ... The RTX mode is obtained from REG instead of SUBREG, which make D is used instead of . Thus something wrong happens on sign-extend default architectures, like MIPS64. Let's use str_rtx and mode of str_rtx

[PATCH] MIPS: improve -march=native arch detection

If we cannot get info from options and cpuinfo, we try to get from: 1. getauxval(AT_BASE_PLATFORM), introduced since Linux 5.7 2. _MIPS_ARCH from host compiler. This can fix the wrong loader usage on r5/r6 platform with -march=native. gcc/ChangeLog: * config/mips/driver-native.cc (ho

[RFC] Combine zero_extract and sign_extend for TARGET_TRULY_NOOP_TRUNCATION

PR #104914 On TRULY_NOOP_TRUNCATION_MODES_P (DImode, SImode)) == true platforms, zero_extract (SI, SI) can be sign-extended. So, if a zero_extract (DI, DI) following with an sign_extend(SI, DI) can be merged to a single zero_extract (SI, SI). gcc/ChangeLog: PR: 104914. * combine.

Re: [PATCH v5] MIPS: Add speculation_barrier support

Richard Earnshaw (lists) via Gcc-patches 于2023年6月8日周四 20:36写道： > > > On 01/06/2023 05:26, YunQiang Su wrote: > > speculation_barrier for MIPS needs sync+jr.hb (r2+), > > so we implement __speculation_barrier in libgcc, like arm32 does. > > > > gcc/ChangeLog: >

[PATCH] MIPS: Use -mnan value for -mabs if not specified

On most hardware, FCSR.ABS2008 is set the value same with FCSR.NAN2008. Let's use this behaivor by default in GCC, aka gcc -mnan=2008 -c fabs.c will imply `-mabs=2008`. And of course, `gcc -mnan=2008 -mabs=legacy` can continue workable like previous. gcc/ChangeLog: * config/mips/

[PATCH v3] MIPS: add speculation_barrier support

speculation_barrier for MIPS needs sync+jr.hb (r2+), so we implement __speculation_barrier in libgcc, like arm32 does. gcc/ChangeLog: * config/mips/mips-protos.h (mips_emit_speculation_barrier): New prototype. * config/mips/mips.cc (speculation_barrier_libfunc): New static

[PATCH v4] MIPS: add speculation_barrier support

speculation_barrier for MIPS needs sync+jr.hb (r2+), so we implement __speculation_barrier in libgcc, like arm32 does. gcc/ChangeLog: * config/mips/mips-protos.h (mips_emit_speculation_barrier): New prototype. * config/mips/mips.cc (speculation_barrier_libfunc): New static

[PATCH] MIPS: don't expand large block move

On platform with LWL/LWR, mips_block_move_loop is always used, which expand __buildin_memcpy/strcpy to a loop of lwl/lwr/swl/swl etc. For short (normally <=64), it has better performance, but when the src/dest are long, use memcpy/strcpy lib call may have better performance. At the same time, lib

Re: [PATCH] MIPS: don't expand large block move

Maciej W. Rozycki 于2023年5月20日周六 03:21写道： > > On Fri, 19 May 2023, Jeff Law wrote: > > > > diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc > > > index ca491b981a3..00f26d5e923 100644 > > > --- a/gcc/config/mips/mips.cc > > > +++ b/gcc/config/mips/mips.cc > > > @@ -8313,6 +8313,12 @@

[PATCH 1/3] MIPS: add -mcompact-branches=prefer option

For MIPSr6, we may wish to use compact-branches only. Currently, we have to use `always' option, while it is mark as conflict with pre-R6. cc1: error: unsupported combination: ‘mips32r2’ -mcompact-branches=always It make some trouble for distributions to make -mcompact-branches=always default fo

[PATCH 3/3] MIPS: fix compact-branches test FAIL for PIC default configuration

GCC may be configured to use PIC by default, then the test with -mno-abicall may fail. Just add -fno-PIC option for it. --- gcc/testsuite/gcc.target/mips/compact-branches-5.c | 2 +- gcc/testsuite/gcc.target/mips/compact-branches-6.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff -

[PATCH 2/3] MIPS: add builtime option for -mcompact-branches

For R6+, it allows to configure gcc to use compact branches only. --- gcc/config.gcc | 18 +- gcc/doc/install.texi | 23 +++ 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 17fea83b2e4..7d50e7995d2 10064

[PATCH 1/2] MIPS: unaligned load: use SImode for SUBREG if OK (PR98996)

index ddf4c7f92d7..fb12eeb971d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2021-02-15 YunQiang Su + + PR target/98996 + * config/mips/mips.c (mips_expand_ext_as_unaligned_load): + If TARGET_64BIT and dest is SUBREG, we check the width, if it + equal to

[PATCH 2/2] ada: add 128bit operation to MIPS N32 and N64

and N32. --- gcc/ada/ChangeLog| 6 ++ gcc/ada/Makefile.rtl | 12 2 files changed, 18 insertions(+) diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 43973550502..32e92c55ef8 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,9 @@ +2021-02-03 YunQiang Su

Re: [PATCH 1/2] MIPS: unaligned load: use SImode for SUBREG if OK (PR98996)

Jeff Law 于2021年2月17日周三 上午3:16写道： > > > > On 2/14/21 6:33 PM, YunQiang Su wrote: > > It is found by ada s-pack96.adb ftbfs, due to 96bit load: 96 = 64 + 32. > > While the 32bit pair of l r is mark as SUBREG, so they are > > not in SImode, make it fail to find suitab

[PATCH v2 1/2] MIPS: unaligned load: use SImode for SUBREG if OK (PR98996)

index 0b3bdcee619..3c91791feac 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2021-02-18 YunQiang Su + + PR target/98996 + * config/mips/mips.c (mips_expand_ext_as_unaligned_load): + If TARGET_64BIT and dest is SUBREG, we check the width, if it + equal to

[PATCH v2 2/2] ada: add 128bit operation to MIPS N32 and N64

and N32. --- gcc/ada/ChangeLog| 6 ++ gcc/ada/Makefile.rtl | 12 2 files changed, 18 insertions(+) diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 52faefaa2ae..3565a32c5ac 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,9 @@ +2021-02-18 YunQiang Su

Re: [PATCH v2 2/2] ada: add 128bit operation to MIPS N32 and N64

/ada/ChangeLog > > index 52faefaa2ae..3565a32c5ac 100644 > > --- a/gcc/ada/ChangeLog > > +++ b/gcc/ada/ChangeLog > > @@ -1,3 +1,9 @@ > > +2021-02-18 YunQiang Su > > + > > + PR ada/98996 > > + * Makefile.rtl (LIBGNAT_TARGET_PAIRS, EXTRA_G

Re: [PATCH 2/3] MIPS: add builtime option for -mcompact-branches

Maciej W. Rozycki 于2021年2月17日周三 上午3:45写道： > > On Tue, 16 Feb 2021, Jeff Law via Gcc-patches wrote: > > > > diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi > > > index 4c38244ae58..6b9520569ba 100644 > > > --- a/gcc/doc/install.texi > > > +++ b/gcc/doc/install.texi > > > @@ -1464,6 +1464,2

[PATCH v2 1/2] MIPS: Not trigger error for pre-R6 and -mcompact-branches=always

For MIPSr6, we may wish to use compact-branches only. Currently, we have to use `always' option, while it is mark as conflict with pre-R6. cc1: error: unsupported combination: ‘mips32r2’ -mcompact-branches=always Just ignore -mcompact-branches=always for pre-R6. This patch also defines __mip

[PATCH v2 2/2] MIPS: add builtime option for -mcompact-branches

For R6+ target, it allows to configure gcc to use compact branches only. --- gcc/config.gcc | 12 +++- gcc/doc/install.texi | 19 +++ 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 17fea83b2e4..047f5631067 100644 -

[PATCH v3 1/2] MIPS: Not trigger error for pre-R6 and -mcompact-branches=always

gcc.target/mips/compact-branches-8.c create mode 100644 gcc/testsuite/gcc.target/mips/compact-branches-9.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index eb1a44ae676..caa3fda48ce 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2021-02-20 YunQiang Su + + * config/mips/mips.

[PATCH v3 2/2] MIPS: add builtime option for -mcompact-branches

| 19 +++ 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index caa3fda48ce..c5fae50e782 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2021-02-20 YunQiang Su + + * config.gcc: add -with-compact-branches=policy

Re: [PATCH v2 2/2] ada: add 128bit operation to MIPS N32 and N64

Arnaud Charlet 于2021年2月18日周四 下午4:51写道： > > > > > For MIPS N64 and N32: > > > > add GNATRTL_128BIT_PAIRS to LIBGNAT_TARGET_PAIRS > > > > add GNATRTL_128BIT_OBJS to EXTRA_GNATRTL_NONTASKING_OBJS > > > > > > > > gcc/ada/ChangeLog: > > > > PR ada/98996 > > > > * Makefile.rtl (LIBGNAT_T

Re: [PATCH v2 2/2] ada: add 128bit operation to MIPS N32 and N64

--- > > gcc/ada/ChangeLog| 6 ++ > > gcc/ada/Makefile.rtl | 12 > > 2 files changed, 18 insertions(+) > > > > diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog > > index 52faefaa2ae..3565a32c5ac 100644 > > --- a/gcc/ada/Cha

[PATCH v3 1/2] MIPS: unaligned load: use SImode for SUBREG if OK (PR98996)

index 3bd877243b7..e86d7817d9d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2021-02-23 YunQiang Su + + PR target/98996 + * config/mips/mips.c (mips_expand_ext_as_unaligned_load): + If TARGET_64BIT and dest is SUBREG, we check the width, if it + equal to

[PATCH v3 2/2] ada: add 128bit operation to MIPS N32 and N64

, EXTRA_GNATRTL_NONTASKING_OBJS). --- gcc/ada/ChangeLog| 6 ++ gcc/ada/Makefile.rtl | 12 2 files changed, 18 insertions(+) diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 52faefaa2ae..fb09986bde0 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,9 @@ +2021-02-23 YunQiang Su

[PATCH v4 1/2] MIPS: unaligned load: use SImode for SUBREG if OK (PR98996)

It is found by ada s-pack96.adb ftbfs, due to 96bit load: 96 = 64 + 32. While the 32bit pair of l r is mark as SUBREG, so they are not in SImode, make it fail to find suitable insn. gcc/ChangeLog: PR target/98996 * config/mips/mips.c (mips_expand_ext_as_unaligned_load): If

[PATCH v4 2/2] ada: add 128bit operation for MIPS N32 and N64

For MIPS N64 and N32: add GNATRTL_128BIT_PAIRS to LIBGNAT_TARGET_PAIRS add GNATRTL_128BIT_OBJS to EXTRA_GNATRTL_NONTASKING_OBJS gcc/ada/ChangeLog: PR ada/98996 * Makefile.rtl: add 128Bit operation file for MIPS N64 and N32 to LIBGNAT_TARGET_PAIRS and EXTRA_GNA

[PATCH v4 1/2] MIPS: Not trigger error for pre-R6 and -mcompact-branches=always

For MIPSr6, we may wish to use compact-branches only. Currently, we have to use `always' option, while it is mark as conflict with pre-R6. cc1: error: unsupported combination: ‘mips32r2’ -mcompact-branches=always Just ignore -mcompact-branches=always for pre-R6. This patch also defines __mip

[PATCH v4 2/2] MIPS: add builtime option for -mcompact-branches

For R6+ target, it allows to configure gcc to use compact branches only. gcc/ChangeLog: * config.gcc: add -with-compact-branches=policy build option. * doc/install.texi: Likewise. --- gcc/config.gcc | 12 +++- gcc/doc/install.texi | 19 +++ 2 files ch

[PATCH] MIPS: R6: load/store can process unaligned address

MIPS release 6 requires the lw/ld/sw/sd can work with unaligned address, while it can be implemented by full hardware or trap&emulate. Since it is may be fully done by hardware, we add an option -m(no-)unaligned-access, the kernel may need it. gcc/ChangeLog: * config/mips/mips.h (ISA_HAS

Re: [PATCH 2/3] MIPS: add builtime option for -mcompact-branches

Maciej W. Rozycki 于2021年3月4日周四 上午7:50写道： > > On Fri, 19 Feb 2021, YunQiang Su wrote: > > > > My understanding therefore is that the original assumption that `optimal' > > > will serve people best is no longer true. > > > > > > > I guess

[PATCH] MIPS: use N64 ABI by default if the triple end with -gnuabi64

gcc/ChangeLog: PR target/102089 * config.gcc: MIPS: use N64 ABI by default if the triple end with -gnuabi64, which is used by Debian since 2013. --- gcc/config.gcc | 14 ++ 1 file changed, 14 insertions(+) diff --git a/gcc/config.gcc b/gcc/config.gcc index 0

[PATCH] libffi: Fix MIPS r6 support

for some instructions, MIPS r6 uses different encoding other than the previous releases. 1. mips/n32.S disable .set mips4: since it casuses old insn encoding is used. https://github.com/libffi/libffi/pull/396 2. mips/ffi.c: the encoding for JR is hardcoded: we need to use different value

Re: [PATCH v2] [MIPS]: add .module mipsREV to all output asm file

在 2021/6/18 11:29, YunQiang Su 写道: Currently, the asm output file for MIPS has no rev info. It can make some trouble, for example: assembler is mips1 by default, gcc is fpxx by default. To assemble the output of gcc -S, we have to pass -mips2 to assembler. gcc/ChangeLog: * gcc

[PATCH v3] MIPS: add .module mipsREV to all output asm file

Currently, the asm output file for MIPS has no rev info. It can make some trouble, for example: assembler is mips1 by default, gcc is fpxx by default. To assemble the output of gcc -S, we have to pass -mips2 to assembler. gcc/ChangeLog: * gcc/config/mips/mips.c (mips_module_isa_name): New

Re: [PATCH v2] [MIPS]: add .module mipsREV to all output asm file

Xi Ruoyao via Gcc-patches 于2021年8月28日周六 下午3:09写道： > > On Fri, 2021-08-27 at 15:36 -0600, Jeff Law wrote: > > > It's easier when someone has to debug the code later. > > enums show up in debug output by default, while #defines do not. > > > > > > > switch (mips_isa) > > >{ > > > case MIPS_

[PATCH 1/3] md/define_c_enum: support value assignation

Currently, the enums from define_c_enum and define_enum can only has values one by one from 0. In fact we can support the behaviour just like C, aka like (define_enum "mips_isa" [mips1=1 mips2 mips32=32 mips32r2]), then we can get enum mips_isa { MIPS_ISA_MIPS1 = 1, MIPS_ISA_MIPS2 = 2,

[PATCH 2/3] MIPS: use mips_isa enum instead hardcoded numbers

Currently mips-cpu.defs and mips.h are using hardcoded numbers for isa level. Let's replace them with more readable enum mips_isa. gcc/ChangeLog: * config/mips/mips.md: define_enum "mips_isa". * config/mips/mips.h (struct mips_cpu_info): use enum instead of int for 'isa'

[PATCH 3/3] MIPS: add .module mipsREV to all output asm file

Currently, the asm output file for MIPS has no rev info. It can make some trouble, for example: assembler is mips1 by default, gcc is fpxx by default. To assemble the output of gcc -S, we have to pass -mips2 to assembler. gcc/ChangeLog: * gcc/config/mips/mips.c (mips_module_isa_name): New

Re: [PATCH] libffi: Fix MIPS r6 support

Xi Ruoyao via Gcc-patches 于2021年8月28日周六 下午3:25写道： > > On Fri, 2021-08-27 at 15:28 -0600, Jeff Law via Gcc-patches wrote: > > > > > > On 8/26/2021 10:58 PM, YunQiang Su wrote: > > > for some instructions, MIPS r6 uses different encoding other than > > >

[PATCH v2] libffi: Fix MIPS r6 support

for some instructions, MIPS r6 uses different encoding other than the previous releases. 1. mips/n32.S disable .set mips4: since it casuses old insn encoding is used. https://github.com/libffi/libffi/pull/396 has been accepted as: 94c102aa69b04337f63498e0e6551fcdce549ae5 2. mips/ffi.c:

Re: [PATCH 2/3] MIPS: use mips_isa enum instead hardcoded numbers

Xi Ruoyao 于2021年8月29日周日 下午1:54写道： > > On Sat, 2021-08-28 at 08:05 -0400, YunQiang Su wrote: > > Currently mips-cpu.defs and mips.h are using hardcoded numbers > > for isa level. > > > > Let's replace them with more readable enum mips_isa. > > Good, but th

[PATCH v2] MIPS: add .module mipsREV to all output asm file

Currently, the asm output file for MIPS has no rev info. It can make some trouble, for example: assembler is mips1 by default, gcc is fpxx by default. To assemble the output of gcc -S, we have to pass -mips2 to assembler. gcc/ChangeLog: * gcc/config/mips/mips.c (mips_module_isa_name): New

Re: [PATCH v2] MIPS: add .module mipsREV to all output asm file

Please ignore this post, as I mistakenly used -1 instead of -2. YunQiang Su 于2021年8月30日周一 上午10:57写道： > > Currently, the asm output file for MIPS has no rev info. > It can make some trouble, for example: > assembler is mips1 by default, > gcc is fpxx by default. > To asse

[PATCH v2 1/2] MIPS: use mips_isa enum instead hardcoded numbers

Currently mips-cpu.defs, mips.h, netbsd.h and config.gcc are using hardcoded numbers for isa level. Let's replace them with more readable enum mips_isa. gcc/ChangeLog: * config/mips/mips.h (struct mips_cpu_info): define enum mips_isa; use enum instead of int for 'isa' member.

[PATCH v2 2/2] MIPS: add .module mipsREV to all output asm file

Currently, the asm output file for MIPS has no rev info. It can make some trouble, for example: assembler is mips1 by default, gcc is fpxx by default. To assemble the output of gcc -S, we have to pass -mips2 to assembler. gcc/ChangeLog: * gcc/config/mips/mips.c (mips_module_isa_name): New

Re: [PATCH] libffi: Fix MIPS r6 support

在 2021/8/30 5:00, Jeff Law 写道: On 8/28/2021 1:23 AM, Xi Ruoyao wrote: On Fri, 2021-08-27 at 15:28 -0600, Jeff Law via Gcc-patches wrote: On 8/26/2021 10:58 PM, YunQiang Su wrote: for some instructions, MIPS r6 uses different encoding other than the previous releases. 1. mips/n32.S disable

Re: [PATCH] libffi: Fix MIPS r6 support

Jeff Law via Gcc-patches 于2021年8月30日周一 下午9:48写道： > > > > On 8/30/2021 2:47 AM, YunQiang Su wrote: > > 在 2021/8/30 5:00, Jeff Law 写道: > >> > >> > >> On 8/28/2021 1:23 AM, Xi Ruoyao wrote: > >>> On Fri, 2021-08-27 at 15:28 -0600, Jeff Law v

[PATCH v2] md/define_c_enum: support value assignation

Currently, the enums from define_c_enum and define_enum can only has values one by one from 0. In fact we can support the behaviour just like C, aka like (define_enum "mips_isa" [(mips1 1) mips2 (mips32 32) mips32r2]), then we can get enum mips_isa { MIPS_ISA_MIPS1 = 1, MIPS_ISA_MIPS2

[PATCH v3] md/define_c_enum: support value assignation

Currently, the enums from define_c_enum and define_enum can only has values one by one from 0. In fact we can support the behaviour just like C, aka like (define_enum "mips_isa" [(mips1 1) mips2 (mips32 32) mips32r2]), then we can get enum mips_isa { MIPS_ISA_MIPS1 = 1, MIPS_ISA_MIPS2

Re: [PATCH v2] md/define_c_enum: support value assignation

YunQiang Su 于2021年8月31日周二 下午7:09写道： > > Currently, the enums from define_c_enum and define_enum can only > has values one by one from 0. > > In fact we can support the behaviour just like C, aka like > (define_enum "mips_isa" [(mips1 1) mips2 (mips32 32) mips32r2])

[PATCH v2] MIPS: improve -march=native arch detection

If we cannot get info from options and cpuinfo, we try to get from: 1. getauxval(AT_BASE_PLATFORM), introduced since Linux 5.7 2. _MIPS_ARCH from host compiler. mnan=2008 option is also used if __mips_nan2008__ is used. This can fix the wrong loader usage on r5/r6 platform with -march=native.

[PATCH] MIPS: fix building on multiarch platform

On platforms that support multiarch, such as Debian, the filesystem hierarchy doesn't fellow the old Irix style: lib & lib/ for native lib64 for N64 on N32/O32 systems lib32 for N32 on N64/O32 systems libo32 for O32 on N64/N32 systems Thus we cannot #define STANDAR

[PATCH v3] MIPS: IPL is 8bit in Cause and Status registers if TARGET_MCU

If MIPS MCU extension is enable, the IPL section in Cause and Status registers has been expand to 8bit instead of 6bit. In Cause: the bits are 10-17. In Status: the bits are 10-16 and 18. MD00834-2B-MUCON-AFP-01.03.pdf: P49 and P61. gcc/ChangeLog: * config/mips/mips.cc (mips_expand_prol

Re: [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU

在 2022/2/12 16:47, Maciej W. Rozycki 写道: On Fri, 11 Feb 2022, Jeff Law wrote: If MIPS MCU extension is enable, the IPL section in Cause register has been expand to 8bit instead of 6bit. gcc/ChangeLog: * config/mips/mips.cc (mips_expand_prologue): IPL is 8bit for MCU ASE. OK

[PATCH] MIPS: use 8bit for IPL in Cause register

Since MIPS r2, the IPL section in Cause register has been expand to 8bit instead of 6bit. Since __attribute__((interrupt)) is only supported for r2+, we don't need to detect the target. gcc/ChangeLog: * config/mips/mips.cc (mips_expand_prologue): IPL is 8bit for r2+. --- gcc/c

[PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU

If MIPS MCU extension is enable, the IPL section in Cause register has been expand to 8bit instead of 6bit. gcc/ChangeLog: * config/mips/mips.cc (mips_expand_prologue): IPL is 8bit for MCU ASE. --- gcc/config/mips/mips.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) d

Re: [PATCH] MIPS: improve -march=native arch detection

On Tue, Aug 02, 2022 at 11:10:09AM +, YunQiang Su wrote: > If we cannot get info from options and cpuinfo, we try to get from: > 1. getauxval(AT_BASE_PLATFORM), introduced since Linux 5.7 > 2. _MIPS_ARCH from host compiler. > > This can fix the wrong loader usage on r5/r

Re: [PATCH] MIPS: improve -march=native arch detection

YunQiang Su 于2022年8月2日周二 19:11写道： > > If we cannot get info from options and cpuinfo, we try to get from: > 1. getauxval(AT_BASE_PLATFORM), introduced since Linux 5.7 > 2. _MIPS_ARCH from host compiler. > > This can fix the wrong loader usage on r5/r6 platform with > -m

Re: [PATCH] Add MIPS Linux support to gcc.misc-tests/linkage.c (testsuite/51748)

Richard Sandiford via Gcc-patches 于2021年9月1日周三 下午4:55写道： > > apinski--- via Gcc-patches writes: > > From: Andrew Pinski > > > > This adds MIPS Linux support to gcc.misc-tests/linkage.exp. Basically > > copying what was done for MIPS IRIX and changing the options to be correct. > > > > OK? > > >

Re: [PATCH v3] md/define_c_enum: support value assignation

Andrew Pinski via Gcc-patches 于2021年9月2日周四 上午5:28写道： > > On Tue, Aug 31, 2021 at 4:22 AM YunQiang Su wrote: > > > > Currently, the enums from define_c_enum and define_enum can only > > has values one by one from 0. > > > > In fact we can support

[PATCH v3] MIPS: add .module mipsREV/.set arch= to all output asm file

Currently, the asm output file for MIPS has no rev info. It can make some trouble, for example: assembler is mips1 by default, gcc is fpxx by default. To assemble the output of gcc -S, we have to pass -mips2 to assembler. The same situation is for some CPU has extension insn. Octeon is an ex

Re: [PATCH v3] MIPS: add .module mipsREV/.set arch= to all output asm file

Maciej W. Rozycki 于2021年9月3日周五 上午9:48写道： > > On Thu, 2 Sep 2021, YunQiang Su wrote: > > > diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c > > index 493d3de48..743a1d0fe 100644 > > --- a/gcc/config/mips/mips.c > > +++ b/gcc/config/mips/mips.c > >

Re: [PATCH v3] MIPS: add .module mipsREV/.set arch= to all output asm file

YunQiang Su 于2021年9月3日周五 上午9:53写道： > > Maciej W. Rozycki 于2021年9月3日周五 上午9:48写道： > > > > On Thu, 2 Sep 2021, YunQiang Su wrote: > > > > > diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c > > > index 493d3de48..743a1d0fe 100644 > > >

[PATCH v4] MIPS: add .module arch and ase to all output asm

Currently, the asm output file for MIPS has no rev info. It can make some trouble, for example: assembler is mips1 by default, gcc is fpxx by default. To assemble the output of gcc -S, we have to pass -mips2 to assembler. The same situation is for some CPU has extension insn. Octeon is an ex

Re: [RFC 1/7] Avoid references to register names in instruction output patterns.

Dragan Mladjenovic via Gcc-patches 于2021年9月26日周日 下午9:26写道： > > This allows us to choose the different names if needed in the future. > I try to apply this patch to current gcc, I get this error: /build/mips-mti-elf/srcs-gcc/gcc/testsuite/gcc.c-torture/compile/20010226-1.c: In function 'foo':^M /b

[PATCH v3] MIPS: R6: load/store can process unaligned address

MIPS release 6 requires the lw/ld/sw/sd can work with unaligned address, while it can be implemented by full hardware or trap&emulate. Since it doesn't have to be fully done by hardware, we add a pair of options -m(no-)unaligned-access. Kernels may need them. gcc/ChangeLog: * config/mips

[PATCH v5 1/2] MIPS: Not trigger error for pre-R6 and -mcompact-branches=always

For MIPSr6, we may wish to use compact-branches only. Currently, we have to use `always' option, while it is mark as conflict with pre-R6. cc1: error: unsupported combination: ‘mips32r2’ -mcompact-branches=always Just ignore -mcompact-branches=always for pre-R6. This patch also defines __mip

[PATCH v5 2/2] MIPS: add builtime option for -mcompact-branches

For R6+ target, it allows to configure gcc to use compact branches only if avaiable. gcc/ChangeLog: * config.gcc: add -with-compact-branches=policy build option. * doc/install.texi: Likewise. * config/mips/mips.h: Likewise. --- gcc/config.gcc | 13 +++-- gc

[PATCH v2] MIPS: R6: load/store can process unaligned address

MIPS release 6 requires the lw/ld/sw/sd can work with unaligned address, while it can be implemented by full hardware or trap&emulate. Since it is may be fully done by hardware, we add an option -m(no-)unaligned-access, the kernel may need it. gcc/ChangeLog: * config/mips/mips.h (ISA_HAS

[commit] MIPS: Add -m(no-)strict-align option

We support options -m(no-)unaligned-access 2 years ago, while currently most of other ports prefer -m(no-)strict-align. Let's support -m(no-)strict-align, and keep -m(no-)unaligned-access as alias. gcc * config/mips/mips.opt: Support -mstrict-align, and use TARGET_STRICT_ALIGN as t

Re: CI for "Option handling: add documentation URLs"

actice for this cases? Should I push a new commit? Or in fact a single commit is preferred? -- YunQiang Su

[commit] Regenerate opt.urls

Fixes: acc38ff59976 ("MIPS: Add -m(no-)strict-align option") gcc/ChangeLog: * config/riscv/riscv.opt.urls: Regenerated. * config/rs6000/sysv4.opt.urls: Likewise. * config/xtensa/xtensa.opt.urls: Likewise. --- gcc/config/riscv/riscv.opt.urls | 2 +- gcc/config/rs6000/sys

[PATCH] Predefine __STRICT_ALIGN__ if STRICT_ALIGNMENT

Arm32 predefines __ARM_FEATURE_UNALIGNED if -mno-unaligned-access, and RISC-V predefines __riscv_misaligned_avoid, while other ports that support -mstrict-align/-mno-unaligned-access don't have such macro, and these backend macros are only avaiable for c-family. Note: Arm64 always predefine __ARM_F

Re: [PATCH] Predefine __STRICT_ALIGN__ if STRICT_ALIGNMENT

Sam James 于2024年3月17日周日 14:04写道： > > YunQiang Su writes: > > > Arm32 predefines __ARM_FEATURE_UNALIGNED if -mno-unaligned-access, > > and RISC-V predefines __riscv_misaligned_avoid, while other ports > > that support -mstrict-align/-mno-unaligned-access don'

[PATCH] MIPS: Predefine __mips_strict_alignment if STRICT_ALIGNMENT

Arm32 predefines __ARM_FEATURE_UNALIGNED if -mno-unaligned-access, and RISC-V predefines __riscv_misaligned_avoid. Let's define __mips_strict_alignment for MIPSr6 and -mstrict-align is used. Not that, this macro is always defined for pre-R6. gcc config/mips/mips.h (TARGET_CPU_CPP_BUILTIN

Re: [PATCH v2] MIPS: Add MIN/MAX.fmt instructions support for MIPS R6

Jie Mei 于2024年3月25日周一 17:46写道： > > This patch adds the smin/smax RTL mode for the > min/max.fmt instructions. > > Also, since the min/max.fmt instrucions applies to the > IEEE 754-2008 "minNum" and "maxNum" operations, this > patch also provides the new "fmin3" and > "fmax3" modes. > > gcc/ChangeL

Re: [PATCH] mips: Fix C23 (...) functions returning large aggregates [PR114175]

Xi Ruoyao 于2024年3月20日周三 15:12写道： > > We were assuming TYPE_NO_NAMED_ARGS_STDARG_P don't have any named > arguments and there is nothing to advance, but that is not the case > for (...) functions returning by hidden reference which have one such > artificial argument. This is causing gcc.dg/c23-st

Re: [PATCH] MIPS: Fix wrong MSA FP vector negation

Xi Ruoyao 于2024年2月5日周一 02:01写道： > > We expanded (neg x) to (minus const0 x) for MSA FP vectors, this is > wrong because -0.0 is not 0 - 0.0. This causes some Python tests to > fail when Python is built with MSA enabled. > > Use the bnegi.df instructions to simply reverse the sign bit instead. > >

Re: CI for "Option handling: add documentation URLs"

e documentation. > > But we should first apply this diff. Could you double check it is > sane/correct? > > Thanks, > > Mark -- YunQiang Su

[commit] invoke.texi: Fix some skipping UrlSuffix problem for MIPS

The problem is that, there are these lines in mips.opt.urls: ; skipping UrlSuffix for 'mabi=' due to finding no URLs ; skipping UrlSuffix for 'mno-flush-func' due to finding no URLs ; skipping UrlSuffix for 'mexplicit-relocs' due to finding no URLs These lines is not fixed by this patch due

[commit] MIPS: Add ATTRIBUTE_UNUSED to mips_start_function_definition

Fix build warning: mips.cc: warning: unused parameter 'decl'. gcc * config/mips/mips.cc (mips_start_function_definition): Add ATTRIBUTE_UNUSED. --- gcc/config/mips/mips.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/

Re: [pushed][PR112918][LRA]: Fixing IRA ICE on m68k

ltilib \ --with-arch-32=mips32r2 --with-fp-32=xx \ --enable-multiarch --enable-targets=all \ --with-arch-64=mips64r2 --prefix=/usr --disable-libsanitizer 4. make -j -- YunQiang Su

[PATCH] MIPS: avoid $gp store if global_pointer is not $gp

$GP is used for expanding GOT load, and in the afterward passes, we will try to use a temporary register instead. If sucess, we have no need to store and reload $gp. The example of failure is that the function calls a preemtive function. We shouldn't use $GP for any other purpose in the code we g

Re: MIPS: the method of getting GOT address for PIC code

YunQiang Su 于2023年8月25日周五 15:16写道： > > When working on LLVM, I found this problem > https://github.com/llvm/llvm-project/issues/64974. > Maybe it's time for us to reconsider the way of getting GOT address > for PIC code. > I have my draft patch pushed to GitHub: htt

Re: [PATCH v2] LoongArch: testsuite:Added additional vectorization "-mlsx" option.

e option is needed to > > enable vectorizations. For example, ia64,x86,aarch64, and riscv > > architectures, vectorization is enabled by default. > > But no. The default baseline of 32-bit x86 is i686, which is basically > a Pentium III launched in 1999 without any vector instructions. > > We are still missing something here. > There is a line #define vector __attribute__((vector_size(4*sizeof(int I guess it is the syntax needs to be supported. -- YunQiang Su

Re: [PATCH] combine: Don't optimize SIGN_EXTEND of MEM on WORD_REGISTER_OPERATIONS targets [PR113010]

++ b/gcc/testsuite/gcc.c-torture/execute/pr113010.c > @@ -0,0 +1,9 @@ > +int minus_1 = -1; > + > +int > +main () > +{ > + if ((0, 0xul) >= minus_1) There is a warning option: -Wsign-compare Warn when a comparison between signed and unsigned values could produce an incorrect result when the signed value is converted to unsigned. > +__builtin_abort (); > + return 0; > +} > -- > 2.34.1 > -- YunQiang Su

[commit] Sanitizer/MIPS: Use $t9 for preemptible function call

From: YunQiang Su Currently, almost all of the shared libraries of MIPS, rely on $t9 to get the address of current function, instead of PCREL instructions, even on MIPSr6. So we have to set $t9 properly. To get the address of preemptible function, we need the help of GOT. MIPS/O32 has .cpload

[PATCH] MIPS: Accept arguments for -mexplicit-relocs

GAS introduced explicit relocs since 2001, and %pcrel_hi/low were introduced in 2014. In future, we may introduce more. Let's convert -mexplicit-relocs option, and accpet options: none, base, pcrel. We also update gcc/configure.ac to set the value to option the gas support when GCC itself is

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