[AArch64][SVE] Utilize ASRD instruction for division and remainder

ret Added new tests. Built and regression tested on aarch64-none-elf. Best Regards, Yuliang Wang gcc/ChangeLog: 2019-09-23 Yuliang Wang * config/aarch64/aarch64-sve.md (asrd3): New pattern for ASRD. * config/aarch64/iterators.md (UNSPEC_ASRD): New unspec. (ASRDIV)

[AArch64][SVE2] Shift-Right Accumulate combine patterns

add z0.s, z0.s, z1.s ... after ssraz0.s, z1.s, #{IMM} Unsigned: beforelsr z0.s, z0.s, #{IMM} add z0.s, z0.s, z1.s ... after usraz0.s, z1.s, #{IMM} Built and regression tested on aarch64-none-elf. Best Regards, Yuliang Wang

RE: [AArch64][SVE] Utilize ASRD instruction for division and remainder

Hi Richard, I have renamed the optabs and associated identifiers as per your suggestion. Thanks. Regards Yuliang gcc/ChangeLog: 2019-09-27 Yuliang Wang * config/aarch64/aarch64-sve.md (sdiv_pow23): New pattern for ASRD. * config/aarch64/iterators.md (UNSPEC_ASRD

RE: [AArch64][SVE] Utilize ASRD instruction for division and remainder

Apologies for the accidental change, and added the underscore. Regards Yuliang gcc/ChangeLog: 2019-09-27 Yuliang Wang * config/aarch64/aarch64-sve.md (sdiv_pow23): New pattern for ASRD. * config/aarch64/iterators.md (UNSPEC_ASRD): New unspec. * internal

RE: [AArch64][SVE] Utilize ASRD instruction for division and remainder

Thanks for the corrections, updated. Regards Yuliang (no ChangeLog updates) -Original Message- From: Richard Sandiford Sent: 27 September 2019 11:20 To: Yuliang Wang Cc: gcc-patches@gcc.gnu.org; nd Subject: Re: [AArch64][SVE] Utilize ASRD instruction for division and remainder

[AArch64][SVE2] Fix for new test in r276174

Hi, The new test added as part of r276174 fails on an ilp32 target, which this patch fixes. Thanks to Christophe Lyon for pointing this out. Regression tested on aarch64-none-elf. Best Regards, Yuliang Wang gcc/testsuite/ChangeLog: 2019-10-04 Yuliang Wang * gcc.target/aarch64

RE: [AArch64][SVE2] Shift-Right Accumulate combine patterns

Hi Christophe, Thanks for pointing this out, uploaded a fix. Regards, Yuliang From: Christophe Lyon Sent: 04 October 2019 09:25 To: Richard Sandiford Cc: Yuliang Wang ; gcc-patches@gcc.gnu.org; nd Subject: Re: [AArch64][SVE2] Shift-Right Accumulate combine patterns On Fri, 27 Sep 2019 at

[AArch64][SVE2] Support for EOR3 and variants of BSL

y -> NBSL x, y, x NAND x, y -> NBSL x, y, y Built and tested on aarch64-none-elf. Best Regards, Yuliang Wang gcc/ChangeLog: 2019-10-16 Yuliang Wang * config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3) (aarch64_sve2_nor, aarch64_sve2_nand) (aarch64_

RE: [AArch64][SVE2] Support for EOR3 and variants of BSL

Hi Richard, Thanks for the suggestions, updated. Regards, Yuliang gcc/ChangeLog: 2019-10-17 Yuliang Wang * config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3) (aarch64_sve2_nor, aarch64_sve2_nand) (aarch64_sve2_bsl, aarch64_sve2_nbsl) (aarch64_sve2_bsl1n

RE: [AArch64][SVE2] Support for EOR3 and variants of BSL

Thanks very much, updated. Regards, Yuliang gcc/ChangeLog: 2019-10-17 Yuliang Wang * config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3) (aarch64_sve2_nor, aarch64_sve2_nand) (aarch64_sve2_bsl, aarch64_sve2_nbsl) (aarch64_sve2_bsl1n, aarch64_sve2_bsl2n

[AArch64][SVE2] Fix for r277110 (BSL variants)

; Built and tested on aarch64-none-elf. Regards, Yuliang Wang gcc/ChangeLog: 2019-10-17 Yuliang Wang * match.pd (/* (x & ~m) | (y & m) -> ... */): Modified fold pattern. * genmatch.c (convert3): New convert operation to support the above. gcc/

[match.pd] Mid-end fix for r277110

; Built and tested on aarch64-none-elf. Regards, Yuliang Wang gcc/ChangeLog: 2019-10-17 Yuliang Wang * match.pd (/* (x & ~m) | (y & m) -> ... */): Modified fold pattern. * genmatch.c (convert3): New convert operation to support the above. gcc/

[PATCH][AArch64] Vectorize MULH(R)S patterns with SVE2 instructions

... vectorizes with SHRNT/SHRNB * 32-bit and 8-bit input/output types * Signed output types SMULLT/SMULLB are generated instead SQRDMULH was considered as a potential single-instruction optimization but saturates the intermediate value instead of truncating. Best Regards, Yuliang Wang

RE: [PATCH][AArch64] Vectorize MULH(R)S patterns with SVE2 instructions

Hi Richard, Thanks for your comments and advice; I have applied the relevant changes. Regards, Yuliang UPDATE: Added new tests. Built and regression tested on aarch64-none-elf and aarch64-linux-gnu. gcc/ChangeLog: 2019-09-1 Yuliang Wang PR tree-optimization/89386

[PATCH] Reduction of conditional operations for vectorization

, Yuliang Wang gcc/ChangeLog: 2019-09-19 Yuliang Wang * match.pd (for cnd (cond vec_cond)): New match statements for the above patterns. * doc/sourcebuild.texi (vect_condred_si): Document new target selector. gcc/testsuite/ChangeLog: 2019-09-19 Yuliang Wang

RE: [PATCH] Reduction of conditional operations for vectorization

CTS (arg) ...) return NULL_TREE; ... For instance, this causes infinite recursion in gcc.dg/vect/fast-math-vect-call-2 because ARG is a float literal. Regards, Yuliang -Original Message- From: Richard Biener Sent: 20 September 2019 13:02 To: Yuliang Wang Cc: gcc-patches@gcc.gnu.org;