patch to solve PR49936

The following patch makes gcc4.7 behaving as gcc4.6 for the case described on http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49936. The patch was successfully bootstrapped on x86_64 and ppc64. Committed as rev 177916. 2011-08-19 Vladimir Makarov PR rtl-optimization/49936

Re: patch to solve PR49936

On 08/20/2011 06:13 AM, Richard Sandiford wrote: Hi Vlad, Vladimir Makarov writes: The following patch makes gcc4.7 behaving as gcc4.6 for the case described on http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49936. The patch was successfully bootstrapped on x86_64 and ppc64. Committed as rev

Re: patch to solve PR49936

On 08/20/2011 06:39 PM, Vladimir Makarov wrote: On 08/20/2011 06:13 AM, Richard Sandiford wrote: Hi Vlad, Vladimir Makarov writes: The following patch makes gcc4.7 behaving as gcc4.6 for the case described on http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49936. The patch was successfully

[lra] Rewriting caller saves subpass.

subpass run in some cases. The patch was successfully tested on bootstrap of x86_64 and ppc64 and improved GCC compile speed (in release mode) by about 1%. 2011-08-23 Vladimir Makarov * lra-int.h (lra_debug_save_data): Remove. (lra_save_restore): Change the prototype

patch to solve recent SPEC2000 degradation

performance problem and was successfully bootstrapped on x86-64. Committed as rev. 178019. 2011-08-23 Vladimir Makarov * ira.c (ira_init_register_move_cost): Check small subclasses through ira_reg_class_max_nregs and ira_available_class_regs. Index: ira.c

Re: patch to solve recent SPEC2000 degradation

On 08/25/2011 05:57 AM, Richard Sandiford wrote: Vladimir Makarov writes: Instead of using explicitly necessary number of registers, I used contains_reg_of_mode which also checks the number of necessary registers but also it checks that the register class can hold value of given mode

Re: patch to solve recent SPEC2000 degradation

On 08/25/2011 02:07 PM, Richard Sandiford wrote: Vladimir Makarov writes: On 08/25/2011 05:57 AM, Richard Sandiford wrote: Vladimir Makarov writes: Instead of using explicitly necessary number of registers, I used contains_reg_of_mode which also checks the number of necessary

[lra] a small patch for LRA speedup.

pseudos for simpler and better allocation which called df_insn_rescan after each change. With the new caller-saves subpass we don't need to do that any more. The patch was successfully bootstrapped on x86-64 and ia64. 2011-08-25 Vladimir Makarov * lra.c (remove_scratches): Don

Re: New automaton_option "collapse-ndfa"

On 08/25/2011 06:21 PM, Bernd Schmidt wrote: On 07/18/11 18:47, Vladimir Makarov wrote: But I guess comb-vector is popular for a reason. We could tolerate slow compression time because it is done once but worse compression and slower access would have a really bad impact on the compiler time

[lra] patch to fix ppc32 code size degradation and a small clean up

to spilled pseudos. The patch also contains a clean up of function mark_not_eliminable. The patch was bootstrapped on x86-64 and ppc64. 2011-08-26 Vladimir Makarov * lra-constraints.c (best_reload_nregs): New variable. (process_alt_operands): Add preferences for smaller hard

PING: patch to solve PR48455 and improve code size for -Os

http://gcc.gnu.org/ml/gcc-patches/2011-08/msg01349.html

[lra] reverting a patch

. 2011-09-02 Vladimir Makarov Revert: 2011-08-26 Vladimir Makarov * lra-constraints.c (best_reload_nregs): New variable. (process_alt_operands): Add preferences for smaller hard registers involved. Increase reject for all failed non registers

[lra] Fix ppc64 bootstrap failure

The following patch fixes compiler crash on stage3 of bootstrap. The patch was successfully bootstrapped on x86/x86-64 and ppc64. 2011-09-09 Vladimir Makarov * lra-constraints.c (equivalence_change_p): Rename to debug_loc_equivalence_change_p. Process subreg of reg whose

[lra] patch to solve code size regression on ppc32 SPEC2000

patch was successfully bootstrapped on x86/x86-64 and ppc32. 2011-09-12 Vladimir Makarov * lra-constraints.c (best_reload_nregs): New variable. (process_alt_operands): Add heuristics based on number regs involved in relaods and based on '*' constraints. Increase re

[lra] patch to use equiv for restoring values around calls

on x86-64 and ppc64. 2011-09-15 Vladimir Makarov * lra.c (remove_scratches): Rescan changed insns. (lra): Call df_analyze after lr_save_restore if necessary. * lra-int.h (lr_save_restore): Change the prototype. * lra-saves.c (struct save_regs): Rename mem_reg to

[lra] patch mostly to simplify work with bound pseudos.

on x86/x86-64 and ppc64. 2011-09-23 Vladimir Makarov * ira-int.h (struct target_ira_int): Remove x_ira_reg_classes_intersect_p. (ira_reg_classes_intersect_p): Remove. * ira.h (struct target_ira): Add x_ira_reg_classes_intersect_p. (ira_reg_classes_intersect_p): New macro

[lra] pseudo assignment improvements

valgrind error (reading uninitialized data). The patch was successfully bootstrapped on x86/x86-64 and ppc64. 2011-09-29 Vladimir Makarov * lra-int.h (lra_get_copy): New prototype. * lra.c (lra_get_copy): New function. * lra-saves.c (lra_save_restore): Ignore scratches

Re: [0/4] Modulo scheduling with haifa-sched for C6X

On 09/27/2011 08:36 AM, Bernd Schmidt wrote: Ping: http://gcc.gnu.org/ml/gcc-patches/2011-09/msg00811.html Bernd, sorry for the delay. I thought for long time about this approach because we already have selective scheduler which with some modifications could be used for this. Selective sc

[lra] patch to improve elimination and inheritance

register to inheritance pseudo and connected reload pseudos. And, finally, different changes to speed up LRA and some bug fixes are also in the patch. The patch was successfully bootstrapped on x86/x86-64 and ppc64. Committed as revision 179942. 2011-10-13 Vladimir Makarov * lra

Re: [PATCH] Add explicit VIS intrinsics for addition and subtraction.

On 09/28/2011 06:38 PM, Eric Botcazou wrote: [Vlad, if you have a few minutes, would you mind having a look at the couple of questions at the end of the message? Thanks in advance]. No problem. Here are the results of the investigation. Pseudo 116 needs to be assigned a hard register. It is

Re: Predication during scheduling

On 10/13/2011 05:01 PM, Bernd Schmidt wrote: On 09/30/11 17:29, Bernd Schmidt wrote: This patch allows a backend to set a new scheduler flag, DO_PREDICATION, which will make the haifa scheduler try to move insns across jumps by predicating them. On C6X, the primary benefit is to fill jump delay

Re: [PATCH] sel-sched: forbid differing modes in substitution (PR 50205)

On 09/07/2011 05:38 AM, Alexander Monakov wrote: Hello, The patch repairs a problem when we attempt to substitute an insn like (... (cmp (mem (reg:DI ax)) (reg:SI ax))) (note different modes) through (set (reg:DI ax) (reg:DI dx)), which leaves the (reg:SI ax) part of the comparison intact, causi

Re: [PATCH] sel-sched: fix merging of LHS reg availability (PR 50340)

On 09/13/2011 12:42 PM, Alexander Monakov wrote: Fixed as follows, bootstrapped and regtested on x86_64-linux and ia64-linux (without java, with one recent SRA patch reverted to unbreak bootstrap) with sel-sched enabled at -O2. OK for trunk? Ok with a small code format change below. (a small

[lra] patch to discourage some register usage on x86/x86-64

The following patch discourages usage of BP, R12, and R13 as it results in larger addresses on x86/x86-64. Committed as rev. 185533. 2012-03-19 Vladimir Makarov * config/i386/i386.c (ix86_register_bank): Add special treatment for BP, R12, and R13. Index: config/i386/i386.c

[lra] spilling general class pseudos into SSE regs instead of memory (a target hooks driven implementation)

bootstrapped on x86/x86-64 with additional options -mtune=corei7 -march=corei7. Committed as rev. 185884. 2012-03-27 Vladimir Makarov * common.opt (flra-reg-spill): New option. * doc/tm.texi (TARGET_SPILL_CLASS, TARGET_SPILL_CLASS_MODE): New hooks. * target.def (spill_class

Re: [lra] spilling general class pseudos into SSE regs instead of memory (a target hooks driven implementation)

On 03/28/2012 02:39 AM, Ye Joey wrote: On Wed, Mar 28, 2012 at 1:07 AM, Vladimir Makarov wrote: The following patch implements general spilling one class pseudos into another class hard registers *instead of memory* in LRA. Can't find the patch itself Sorry, my bad. Here is the

patch to fix a bug in coloring in multi-register allocnos presence.

03-29 Vladimir Makarov * ira-color.c (setup_left_conflict_sizes_p): Process all conflicting objects. Index: ira-color.c === --- ira-color.c (revision 185967) +++ ira-color.c (working copy) @@ -821,7 +

[lra] patch to bootstrap GCC with LRA on MIPS64EL

The following patch makes GCC bootstrap successful on mips64el with LRA usage. Committed as rev. 186198. 2012-04-06 Vladimir Makarov * config/mips/mips.c: Include lra.h. (mips_expand_fcc_reload): Add code for LRA. * lra-int.h (lra_get_allocno_class

Re: RFC reminder: an alternative -fsched-pressure implementation

On 04/10/2012 09:35 AM, Richard Sandiford wrote: Hi Vlad, Back in Decemember, when we were still very much in stage 3, I sent an RFC about an alternative implementation of -fsched-pressure. Just wanted to send a reminder now that we're in the proper stage: http://gcc.gnu.org/ml/gcc-patches/2011

Re: haifa-sched: Fix problems with cc0 in prune_ready_list

On 04/11/2012 10:08 AM, Bernd Schmidt wrote: On 02/10/2012 08:01 PM, Vladimir Makarov wrote: On 02/08/2012 10:01 AM, Bernd Schmidt wrote: We found a scheduler problem while testing Coldfire targets. The prune_ready_list function I introduced doesn't take SCHED_GROUPs into account, whic

Re: RFC: IRA patch to reduce lifetimes

On 04/11/2012 10:35 AM, Bernd Schmidt wrote: On 12/23/2011 05:31 PM, Vladimir Makarov wrote: On 12/21/2011 09:09 AM, Bernd Schmidt wrote: This patch was an experiment to see if we can get the same improvement with modifications to IRA, making it more tolerant to over-aggressive scheduling. THe

Re: RFC reminder: an alternative -fsched-pressure implementation

On 04/10/2012 09:35 AM, Richard Sandiford wrote: Hi Vlad, Back in Decemember, when we were still very much in stage 3, I sent an RFC about an alternative implementation of -fsched-pressure. Just wanted to send a reminder now that we're in the proper stage: http://gcc.gnu.org/ml/gcc-patches/2011

Re: RFC reminder: an alternative -fsched-pressure implementation

On 04/17/2012 04:29 AM, Richard Sandiford wrote: Vladimir Makarov writes: On the other hand, I don't think that 1st insn scheduling will be ever used for x86. And although the SPECFP2000 rate is the same on x86-64 I saw that some SPECFP2000 tests benefit from your algorithm on x86-64

[lra] patch to fix most mips testsuite regressions

The following patch fixes most GCC testsuite regressions of LRA on mips64. Committed as rev. 186598. 2012-04-19 Vladimir Makarov * config/mips/mips.c (mips_expand_fcc_reload): Remove code for LRA. Add an assertion. (mips_secondary_reload): New function

Re: [PATCH][IRA] Avoid undefined behavior in ira_allocno_object_iter_cond

On 04/19/2012 08:14 AM, Richard Guenther wrote: This gave me headaches debugging a VRP "miscompile" of ira-build.c. Number of iteration analysis concluded that the allocno object iterators do not iterate because it sees accesses to ->objects[n] for a loop i = 0; i< n; ++i. This is because ira_a

Re: RFC reminder: an alternative -fsched-pressure implementation

On 04/23/2012 11:42 AM, Ulrich Weigand wrote: Vladimir Makarov wrote: I have a mixed feeling with the patch. I've tried it on SPEC2000 on x86/x86-64 and ARM. Model algorithm generates bigger code up to 3.5% (SPECFP on x86), 2% (SPECFP on 86-64), and 0.23% (SPECFP on ARM) in comparison wit

[lra] patch to bootstrap GCC with LRA on PA-RISC

The following patch makes GCC bootstrap on PA-RISC successful. Committed as rev. 186724. 2012-04-23 Vladimir Makarov * targhooks.h (default_different_addr_displacement_p): Declare. * targhooks.c (default_different_addr_displacement_p): New function

[lra] patch to fix some LRA failures of GCC tests on PA-RISC

The following patch fixes some testsuite regressions of LRA in comparison with reload on PA-RISC. There are still few regressions which I'll work on later. The patch was bootstrapped on x86/x86-64. Committed as rev. 186823. 2012-04-25 Vladimir Makarov * lra-constrai

Re: [PR50764, PATCH] Fix for ICE in maybe_record_trace_start with -fsched2-use-superblocks

On 11/22/2011 04:39 AM, Tom de Vries wrote: On 17/11/11 17:53, Maxim Kuvyrkov wrote: On 17/11/2011, at 9:58 PM, Tom de Vries wrote: On 11/15/2011 10:07 PM, Maxim Kuvyrkov wrote: On 30/10/2011, at 8:17 AM, Tom de Vries wrote: Richard, I have a tentative fix for PR50764. Richard, Tom's pat

Re: [lra] patch mostly implementing pseudo live range split

On 11/30/2011 12:09 AM, Jeff Law wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 11/29/11 15:03, Vladimir Makarov wrote: This patch contains a part of my several last weeks work on LRA. 1. The major change is to add pseudo live range split transformation to the existing inheritance

Re: [PATCH] Fix up begin_move_insn (PR rtl-optimization/48721)

On 11/30/2011 12:43 PM, Jakub Jelinek wrote: Hi! When INSN is followed by BARRIER, we should add the new dummy basic block after the barrier, not before it. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2011-11-30 Jakub Jelinek PR rtl-optimization/48721

Re: [PATCH] Treat tail calls as scheduling barriers (PR rtl-optimization/48721)

On 11/30/2011 12:54 PM, Jakub Jelinek wrote: Hi! As discussed in the PR, I think tail calls are best handled as full scheduling barriers, scheduling tail calls before other insns effectively means we remove those other insns, but isn't dead insn removal the job of other passes instead? In any ca

Re: [lra] patch mostly implementing pseudo live range split

On 12/02/2011 08:35 AM, Hans-Peter Nilsson wrote: On Tue, 29 Nov 2011, Vladimir Makarov wrote: 3. The patch rewrite the way of dealing with the secondary memory moves in constraint pass of LRA. Previously we generated secondary moves if macro SECONDARY_MEMORY_NEEDED says so

patch to fix PR21617

-12-12 Vladimir Makarov PR rtl-optimization/21617 * ira-color.c (bucket_allocno_compare_func): Don't compare allocno classes. Compare number of hard registers needed. Index: ira-color.c === --- ira-co

patch for PR49865

the performance is about 0.3%. The patch was successfully bootstrapped on x86/x86-64. The patch has been committed as rev. 182553. 2011-12-20 Vladimir Makarov PR target/49865 * ira-costs.c (find_costs_and_classes): Prefer registers even if the memory cost is the same

Re: patch to fix PR21617

On 12/22/2011 06:19 AM, Ilya Enkovich wrote: 2011/12/13 Vladimir Makarov: The following patch solves PR 21617 which is described on http://gcc.gnu.org/bugzilla/show_bug.cgi?id=21617. Just adding number of necessary hard registers solves the problem but creates 2% SPEC2000 perlbmk degradation

Re: RFC: IRA patch to reduce lifetimes

On 12/21/2011 09:09 AM, Bernd Schmidt wrote: For a customer I've looked into improving code for 456.hmmer on a mips64 target. The benchmark responds to -fsched-pressure, which reduces lifetimes of a few registers. This patch was an experiment to see if we can get the same improvement with modifi

Re: RFC: An alternative -fsched-pressure implementation

On 12/23/2011 06:46 AM, Richard Sandiford wrote: So it looks like two pieces of work related to scheduling and register pressure are being posted close together. This one is an RFC for a less aggressive form of -fsched-pressure. I think it should complement rather than compete with Bernd's IRA

[lra] patch to fix an arm testsuite degradation

The following patch fixes a degradation of 20060102-1.c on ARM. Not updating REG notes resulted in removing an insn after LRA as it was wrongly considered dead. The patch was successfully bootstrapped on x86/x86-64. Committed as rev. 182664. 2011-12-23 Vladimir Makarov * lra.c

Re: [lra] patch to fix an arm testsuite degradation

On 12/23/2011 04:17 PM, Paolo Carlini wrote: Hi Vladimir, The following patch fixes a degradation of 20060102-1.c on ARM. unless I'm badly mistaken, I see you using quite often the form 'degradation', which is somewhat unusual in this mailing list. Are you using it like 'regression' or you

Re: RFC: An alternative -fsched-pressure implementation

On 12/28/2011 08:51 AM, Richard Sandiford wrote: Vladimir Makarov writes: In the end I tried an ad-hoc approach in an attempt to do something about (2), (3) and (4b). The idea was to construct a preliminary "model" schedule in which the only objective is to keep register pressure to

Re: RFC: An alternative -fsched-pressure implementation

On 01/09/2012 07:45 AM, Bernd Schmidt wrote: On 12/23/2011 12:46 PM, Richard Sandiford wrote: In the end I tried an ad-hoc approach in an attempt to do something about (2), (3) and (4b). The idea was to construct a preliminary "model" schedule in which the only objective is to keep register pre

Re: FW: patch to fix PR21617

On 12/29/2011 06:41 AM, Igor Zamyatin wrote: Ilya is on vacation so I'll make the answer. Overall score became worse on 0.3%. Ok, thanks. It is in the range of measure error for some processors. But Intel processors range is pretty small. Did you use Atom for measuring? I'll try to find a

Re: [PATCH SMS 2/2, RFC] Register pressure estimation for the partial schedule (re-submission)

On 01/03/2012 04:25 AM, Revital1 Eres wrote: Attached is an updated version with the two changes mentioned above taken from the previous patch. Tested and bootstrap with the other patch in the series on ppc64-redhat-linux, enabling SMS on loops with SC 1. Thanks again, Revital IRA changes a

patch for PR40761.

The following patch solves PR40761 which is described on http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40761. The patch was bootstrapped on x86/x86-64 with -O2 and -O0 with checking enabled. Committed as rev. 183312. 2012-01-19 Vladimir Makarov PR rtl-optimization/40761

Re: FW: patch to fix PR21617

On 01/18/2012 02:30 PM, Zamyatin, Igor wrote: Yes, we use Atom for EEMBC measurements. We'll be glad to help you with your findings. Thanks. Unfortunately I tried several alternative patches but I did not find a better solution (it is mostly code size degradation on CoreI7). Now I am even

Re: FW: patch to fix PR21617

On 01/19/2012 03:52 PM, Vladimir Makarov wrote: On 01/18/2012 02:30 PM, Zamyatin, Igor wrote: Yes, we use Atom for EEMBC measurements. We'll be glad to help you with your findings. Thanks. Unfortunately I tried several alternative patches but I did not find a better solution (it is m

Re: FW: patch to fix PR21617

On 01/23/2012 06:32 AM, Igor Zamyatin wrote: Unfortunately patch doesn't help neither for separate EEMBC_2_0 tests nor for the whole benchmark. Do you want me to do some debugging here? For now I am out of ideas how to fix the PR in alternative way without some performance degradation on SPEC

Re: [PATCH] Assume PATTERN is always non-NULL in sched-deps.c (PR middle-end/51986)

On 01/25/2012 03:10 PM, Jakub Jelinek wrote: Hi! This PR is about a warning that rev may be used uninitialized when sched_get_condition_with_rev_uncached is inlined into its caller. It in fact may be used uninitialized if PATTERN (insn) is ever NULL. But IMNSHO everything in the compiler assumes

Re: Fix genautomata option parsing

On 01/27/2012 12:20 PM, Bernd Schmidt wrote: I noticed that genautomata does not accept any of the options it is trying to handle, since init_rtx_reader_args already errors out for all of them. This was probably broken by some gensupport reorganization way back. Fixed with this patch; I also rem

[lra] patch to fix some bugs in LRA for arm

The following patch fixes some bugs in caller-saves pseudo splitting found on ARM toolchain. But ARM bootstrap failure is not fixed yet. The patch was successfully bootstrapped on x86/x86-64. Committed as rev. 183639. 2012-01-27 Vladimir Makarov * lra-int.h

patch for PR49800

The following patch solves PR49800 which is described on http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49800. The patch was successfully bootstrapped on x86/x86-64. Committed as rev. 183843. 2012-02-02 Vladimir Makarov PR rtl-optimization/49800 * haifa-sched.c (sched_init

Re: haifa-sched: Fix problems with cc0 in prune_ready_list

On 02/08/2012 10:01 AM, Bernd Schmidt wrote: We found a scheduler problem while testing Coldfire targets. The prune_ready_list function I introduced doesn't take SCHED_GROUPs into account, which can lead to a random insn being scheduled between a cc0 setter and user. The patch below fixes it, OK?

[lra] patch to fix bootstrap on ARM

The following patch fixes arm bootstrap for LRA. The problem was in pseudo live range splitting and wrong assignment to multi-registers pseudos with the same value. The patch was successfully bootstrapped on x86/x86-64 and ARM. Committed as rev. 184109. 2012-02-10 Vladimir Makarov * lra

[lra] fixing x86 gcc testsuite regressions

The following tiny patch fixes testsuite regressions on x86-64 occurred after latest merge (this weekend). The patch was successfully bootstrapped on x86/x86-64. Committed as rev. 184173. 2012-02-13 Vladimir Makarov * lra.c (check_rtl): Ignore addr with UNSPEC. Index: lra.c

Re: [lra] fixing x86 gcc testsuite regressions

On 02/13/2012 05:07 PM, Steven Bosscher wrote: On Mon, Feb 13, 2012 at 10:50 PM, Vladimir Makarov wrote: The following tiny patch fixes testsuite regressions on x86-64 occurred after latest merge (this weekend). Hello Vladimir, Could you please also update http://gcc.gnu.org/svn.html

[lra] a patch to fix some x86-64 SPECFP2000 regressions

The following patch fixes some x86-64 SPECFP2000 regressions. The wrong choosing register class for split pseudos resulted in wrong assignments to reload pseudos afterwards. The patch was successfully bootstrapped on x86/x86-64. Committed as rev. 184215. 2012-02-14 Vladimir Makarov

[lra] patch to fix a wrong code generation for bulldozer.

The following patch fixes wrong code generation for SPEC2000 mesa when we use tuning for bulldozer. The patch was successfully bootstrapped on x86/x86-64. Committed as rev. 184278. 2012-02-15 Vladimir Makarov * lra-coalesce.c (lra_coalesce): Check the split pseudos too. Index: lra

Re: [PATCH?, 4.7 regression] Crash in ira-costs.c with -fschedule-insns -fsched-pressure -fdump-rtl-sched1

On 02/14/2012 12:00 PM, Ulrich Weigand wrote: Hello, compiling anything, even just an empty function, with -fschedule-insns -fsched-pressure -fdump-rtl-sched1 causes the compiler to crash: Program received signal SIGSEGV, Segmentation fault. 0x0840d9e0 in REG_N_REFS (regno=58) at ../../gcc-h

Re: [PATCH] Don't decrease mem_cost for special MEMs, even with REG_EQUIV (PR rtl-optimization/52208)

On 02/16/2012 01:56 AM, Jakub Jelinek wrote: Hi! As mentioned in the PR, if SET_SRC MEM (with REG_EQUIV note) isn't a MEM that can be used in general operations, but requires some specialized instruction to load it, decreasing its mem_cost results sometimes in worse code, the MEM is loaded with

[lra] add most common case to choose reg class for split pseudo

I found there are too many rejecting pseudo splits because I excluded most common case of choosing register class for split pseudo. The following patch fixes this. Committed as rev. 184315. 2012-02-16 Vladimir Makarov * lra-constraints.c (choose_split_class): Check allocno_class too

[lra] patch to fix a bootstrap failure on SPARC64

on x86/x86-64. Committed as rev. 18. 2012-02-21 Vladimir Makarov * lra-constraints.c (inherit_in_ebb): Put split save before jump using the pseudo. Index: lra-constraints.c === --- lra-constraints.c

Re: IRA: Fix WORDS_BIG_ENDIAN usage

On 02/20/2012 04:10 PM, Bernd Schmidt wrote: For C6X, I added a patch to separate out a REG_WORDS_BIG_ENDIAN macro from WORDS_BIG_ENDIAN. Since the patch was originally for 4.5, it missed a few new instances in IRA where we need to change which macro we use. The following patch makes big-endian k

[lra] patch to fix SPARC bootstrap failure

The following patch fixes SPARC64 bootstrap failure finally. The patch was successfully bootstrapped on x86/x86-64, SPARC64, and ARM. Committed as rev. 184510. 2012-02-22 Vladimir Makarov * lra-constraints.c (narrow_reload_pseudo_class): New function. (match_reload): Call it

[lra] a patch to fix a testsuite regression on SPARC.

The following patch fixes a few SPARC GCC testsuite regressions. The patch was successfully bootstrapped on x86/x86-64. Committed as rev. 184512. 2012-02-23 Vladimir Makarov * lra-eliminations.c (update_reg_eliminate): Make hard register unallocatable when we make it a

[lra] a path to fix GCC crash on s390

The following patch fixes a compiler crash on s390 during the bootstrap. Unfortunately it is not enough to fix the current s390 bootstrap failure. The patch was successfully bootstrapped on x86/x86-64. Committed as rev. 184524. 2012-02-23 Vladimir Makarov * lra-constraints.c

[lra] patch for S390 bootstrap.

The following patch fixes some bugs preventing S390x bootstrap. The patch is still not fixing the S390 bootstrap yet but I am working on it. The patch was successfully bootstrapped on x86/x86-64. Committed as rev. 184561. 2012-02-24 Vladimir Makarov * lra-assigns.c

[lra] patch to fix some testsuite regressions on s390

The following patch fixes a few GCC testsuite regressions on s390x (the bootstrap on s390x is still broken). The patch was successfully bootstrapped on x86/x86-64. Committed as rev. 184608. 2012-02-27 Vladimir Makarov * lra-eliminations.c (eliminate_regs_in_insn): Rewrite by

[lra] patch to simulate reload behaviour

The following patch adds reload behaviour to LRA for some cases. Some targets assumes such behaviour. The patch was successfully bootstrapped on x86/x86-64. Committed as rev. 184631. 2012-02-28 Vladimir Makarov * lra-constraints.c (check_and_process_move): Process source first

[lra] patch to fix arm bootstrap.

). Committed as rev. 184637. 2012-02-28 Vladimir Makarov * lra-constraints.c (get_op_mode): Use mode from the machine description first. (match_reload, process_addr_reg, simplify_operand_subreg) (curr_insn_transform): Put after-reloads before already existing

[lra] a patch to fix s390 bootstrap

The following patch finally fixes s390 bootstrap. The patch was successfully bootstrapped on s390x, x86/x86-64, power7, arm, sparc64, and ia64. Committed as rev. 184749. 2012-03-01 Vladimir Makarov * lra-lives.c (pseudos_live_through_calls): New sparseset

[lra] a patch to fix a live-range splitting problem in EBB

. 2012-03-05 Vladimir Makarov * lra-constraints.c (simplify_operand_subreg): Treat out subreg operand which is a part of the pseudo as in/out one. (get_live_on_other_edges): Move lower and add non-input operands of jump to the bitmap. Index: lra-constraints.c

RFA: patch for PR48757

The following patch solves PR48757. It is just a slight modification of code for PR48633. 2011-05-24 Vladimir Makarov PR rtl-optimization/48757 * ira-build.c (loop_with_eh_edge_p): Rename to loop_with_complex_edge_p, check edges on complexity, make function

Re: The TI C6X port

On 11-05-23 5:45 AM, Bernd Schmidt wrote: Ping: C6X scheduler changes. http://gcc.gnu.org/ml/gcc-patches/2011-05/msg00747.html I think it is ok. I spent a lot of time looking at the change. It looks ok to me although it is hard to be sure because the code is too complicated. So it is good t

Re: RFA: patch to fix PR48971

On 11-05-24 8:24 PM, Hans-Peter Nilsson wrote: On Fri, 13 May 2011, Vladimir Makarov wrote: The following patch solves the problem described on http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48971 The patch was successfully bootstrapped on x86-64 and checked for ppc64, ia64, i686-linux, i686

Re: RFA: patch to fix PR48971

On 05/25/2011 04:26 PM, Eric Botcazou wrote: Thanks for reporting this. It was a very sensitive change therefore I checked so many targets (about 10) but apparently not all of them. I'll look at the CRIS problem tomorrow. This broke SPARC (in default mode) as well: eric@atlantis:~/build/gcc/s

RFA: a patch for PR49154

class because the registers are common and that is attributed that the class has no subclasses. The patch was bootstrapped on x86-64 and teststed on the same targets (about 10 of them) + regular SPARC (without soft floating point). Ok to commit? 2011-05-25 Vladimir Makarov PR rtl

RFA: another patch to solve PR49154

This patch solves http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49154 for CRIS. The problem was in that the pressure classes did not contain SRP register and the assert failed. OK to commit? 2011-05-25 Vladimir Makarov PR rtl-optimization/49154 * config/cris/cris.h

Re: RFA: another patch to solve PR49154

On 11-05-25 6:58 PM, Hans-Peter Nilsson wrote: On Wed, 25 May 2011, Vladimir Makarov wrote: This patch solves http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49154 for CRIS. The problem was in that the pressure classes did not contain SRP register and the assert failed. I'm not sure I under

Re: RFA: another patch to solve PR49154

On 05/26/2011 04:47 AM, Hans-Peter Nilsson wrote: On Wed, 25 May 2011, Vladimir Makarov wrote: On 11-05-25 6:58 PM, Hans-Peter Nilsson wrote: On Wed, 25 May 2011, Vladimir Makarov wrote: This patch solves http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49154 for CRIS. The problem was in that the

Re: Sched patch: better condition mutex testing

On 05/27/2011 04:14 AM, Bernd Schmidt wrote: When regrename is enabled, it makes new copies of its replacement registers, which means that pointer equality tests can't be used afterwards to check whether two regs are equal. sched_insn_conditions_mutex_p has one such test, and it causes pessimized

[lra] a patch to build ARM

Here is the patch to build arm-elf target with simulator. It has been committed to the branch. 2011-06-01 Vladimir Makarov * lra-eliminations.c (lra_eliminate_reg_if_possible): Fix a typo. (process_insn_for_elimination): Invalidate insn data if the insn code was

[lra] patch to speed up LRA

The following patch removes coalescing when it is not necessary, decrease number of insns to process for constraints, fix a typo, and implements Joseph Myers proposals. The patch was successfully bootstraped (with LRA which is default) on x86-64, itanium, and ppc64. 2011-06-09 Vladimir

Re: [lra] A new branch

On 06/07/2011 09:46 AM, Joseph S. Myers wrote: On Mon, 30 May 2011, Vladimir Makarov wrote: * doc/tm.texi.in (TARGET_REGISTER_BANK): New hook. Please include the text of documentation for new hooks in target.def instead of tm.texi.in where possible (so tm.texi.in just has the @hook

Re: FORBIDDEN_INC_DEC_CLASSES in ira-costs.c

On 06/08/2011 12:37 PM, Hans-Peter Nilsson wrote: There's a lot of dead code inside the obsolete (removed in 2009) and nowhere else set #ifdef FORBIDDEN_INC_DEC_CLASSES. Remove and poison? Yes, I believe so. I'd say borderline obvious, but maybe there's instead reason to reinstate it, if that

Re: Fix PR49154-related SEGV in IRA. And ping.

On 06/08/2011 10:27 PM, Hans-Peter Nilsson wrote: First, a ping for ; updated regclass documentation. Ok? Sorry for the delay. I actually thought about a better formulation for some time and forgot about this because I had to work on

Re: FORBIDDEN_INC_DEC_CLASSES in ira-costs.c

On 11-06-10 8:35 AM, Hans-Peter Nilsson wrote: On Thu, 9 Jun 2011, Hans-Peter Nilsson wrote: * ira-costs.c: Remove #ifdefs on dead FORBIDDEN_INC_DEC_CLASSES. Adjust comments. * system.h (FORBIDDEN_INC_DEC_CLASSES): Poison. Index: ira-costs.c =

Re: [PATCH] sel-sched: Avoid placing bookkeeping code above a fence (PR49349)

On 06/14/2011 07:34 AM, Alexander Monakov wrote: Hello, Quoting myself from the PR audit trail, It's a rare bug in sel-sched: we fail to schedule some code in non-pipelining mode. The root cause is that we put bookkeeping instructions above a fence that is placed on the last insn (uncond. jump

Re: Ping: The TI C6X port

On 06/06/2011 07:26 AM, Bernd Schmidt wrote: Ping^3 for the C6X port. Now with extra patches: Additional preliminary scheduler tweaks: http://gcc.gnu.org/ml/gcc-patches/2011-05/msg02408.html It is ok for me. Thanks, Bernd. Allow alternatives in attr "predicable": http://gcc.gnu.org/ml/gcc-pa

[lra] a patch to speed LRA up

The following patch considerably speeds LRA up. The patch was successfully bootstrapped on x86-64, ia64, and ppc64. 2011-06-15 Vladimir Makarov * lra-assigns.c (live_pseudos_reg_renumber): New array. (init_lives): Initialize the array. (finish_lives): Free the array

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