Hi
This patch fixes a couple of more tests that are giving out warnings with
-Wreturn-type:
- g++.dg/ext/pr57735.C
- gcc.target/arm/pr54300.C
*** gcc/testsuite/ChangeLog ***
2017-11-10 Sudakshina Das
* g++.dg/ext/pr57735.C: Add -Wno-return-type for test.
* gcc.target/arm/pr
Hi
This patch fixes the test case armv8_2-fp16-move-1.c for
arm-none-linux-gnueabihf where 2 of the scan-assembler directives were failing.
We now generate less vmov between core and VFP registers. Thus changing those
directives to reflect that.
Is this ok for trunk?
If yes could someone commi
Hi Kyrill
Thanks I have made the change.
Sudi
From: Kyrill Tkachov
Sent: Thursday, November 16, 2017 5:03 PM
To: Sudi Das; gcc-patches@gcc.gnu.org
Cc: nd; Ramana Radhakrishnan; Richard Earnshaw
Subject: Re: [PATCH][ARM] Fix test armv8_2-fp16-move-1.c
Hi Sudi,
On 16/11/17 16:37, Sudi
trunk? If yes could someone post it on my behalf?
Sudi
*** gcc/testsuite/ChangeLog ***
2017-11-22 Sudakshina Das
* gcc.target/arm/armv8_2-fp16-move-1.c: Add -mfloat-abi=hard option.
From: Kyrill Tkachov
Sent: Monday, November 20, 2017 2:20 PM
To: Christophe Lyon
Cc: Sudi Das
Hi
Since Richard Biener's commit from 16th May:
commit 2f05c3c7324cd293b7b2ba197e0a88d9749361cc
Author: rguenth
Date: Wed May 16 13:08:04 2018 +
the test case slp_5.c had started showing a couple of XPASS failures.
XPASS: gcc.target/aarch64/sve/slp_5.c -march=armv8.2-a+sve scan-assembler
, w0
add sp, sp, 16
ret
.size f4, .-f4
Thanks
Sudi
From: Wilco Dijkstra
Sent: Thursday, April 13, 2017 1:01 PM
To: Richard Biener; Jakub Jelinek
Cc: Sudi Das; GCC Patches; nd; Richard Earnshaw; James Greenhalgh
Subject: Re: [PATCH][GCC] Simplification of 1U << (
immediate constraint.
(Db): Likewise.
2017-08-07 Sudakshina Das
* gcc.target/aarch64/bic_imm_1.c: New test.
* gcc.target/aarch64/orr_imm_1.c: Likewise.
From: Richard Earnshaw (lists)
Sent: Friday, May 5, 2017 2:30 PM
To: Sudi Das; gcc-patches@gcc.gnu.org
Cc: nd; Marcus
Hi all
During combine GCC tries to merge CMP (with zero) and AND into a TST. However,
in cases where an ANDS operand is not compatible, this was being missed. Adding
a define_split where this operand was moved to a register seems to help out.
For example for a test :
int
f (unsigned char *p)
Hi all
This is a fix for PR 80131
Currently the code A << (B - C) is not simplified.
However at least a more specific case of 1U << (C -x) where C = precision(type)
- 1 can be simplified to (1 << C) >> x.
This is done by adding a new simplification rule in match.pd
So for a test case :
unsign
Hello all
This patch adds the support for BIC (vector, immediate) and ORR (vector,
immediate) SIMD patterns to the AArch64 backend.
One of the examples of this is : (with -O2 -ftree-vectorize)
void
bic_s (short *a)
{
for (int i = 0; i < 1024; i++)
a[i] &= ~(0xff);
}
which now produces :
: Wednesday, September 20, 2017 11:39 AM
To: Sudi Das
Cc: Richard Earnshaw; gcc-patches@gcc.gnu.org; nd; Marcus Shawcroft
Subject: Re: [PATCH][AArch64] Add BIC-imm and ORR-imm SIMD pattern
On Mon, Aug 07, 2017 at 02:56:09PM +0100, Sudi Das wrote:
>
> Hi Richard
>
> I have updat
Still waiting on Jakub's comment on whether there are more things needed at the
backend. But I have updated the patch according to Richard's comments.
Thanks
Sudi
From: Richard Biener
Sent: Friday, August 4, 2017 11:16 AM
To: Sudi Das
Cc: Wilco Dijkstra; Jakub Jelinek; GCC P
.
(Db): Likewise.
2017-09-27 Sudakshina Das
* gcc.target/aarch64/bic_imm_1.c: New test.
* gcc.target/aarch64/orr_imm_1.c: Likewise.
Thanks
Sudi
From: James Greenhalgh
Sent: Tuesday, September 26, 2017 8:04:38 PM
To: Sudi Das
Cc: Richard Earnshaw; gcc-patches@gcc.gnu.org; nd
(lists)
Sent: Thursday, September 28, 2017 9:55 AM
To: Sudi Das; James Greenhalgh
Cc: gcc-patches@gcc.gnu.org; nd; Marcus Shawcroft
Subject: Re: [PATCH][AArch64] Add BIC-imm and ORR-imm SIMD pattern
On 27/09/17 18:57, Sudi Das wrote:
>
>
> Hi James
>
> I have made the reque
Hi Steve
Sorry about this.
I am on it. I have a fix and I am running tests on it right now.
Sudi
From: Steve Ellcey
Sent: Thursday, October 5, 2017 12:05 AM
To: Richard Earnshaw; Sudi Das; James Greenhalgh
Cc: gcc-patches@gcc.gnu.org; nd; Marcus Shawcroft
Subject: Re: [PATCH][AArch64] Add
Hi
This patch is a fix for PR 82440.
The predicates aarch64_reg_or_bic_imm and aarch64_reg_or_orr_imm missed out on
checking for a CONST_VECTOR before calling aarch64_simd_valid_immediate
function.
Also I think James forgot to add the test cases in the original patch submitted.
Testing done :
): Likewise.
*** gcc/testsuite/ChangeLog ***
2017-10-05 Sudakshina Das
* gcc.target/aarch64/bic_imm_1.c: New test.
* gcc.target/aarch64/orr_imm_1.c: Likewise..
Thanks
Sudi
From: Jakub Jelinek
Sent: Friday, October 6, 2017 11:11 AM
To: Sudi Das
Cc: gcc-patches@gcc.gnu.org; nd
Das; Jakub Jelinek
Cc: gcc-patches@gcc.gnu.org; nd; sell...@cavium.com; Marcus Shawcroft; James
Greenhalgh
Subject: Re: [PATCH][AArch64] Fix ICE caused in aarch64_simd_valid_immediate
On 06/10/17 12:01, Sudi Das wrote:
>
> Hi Jakub
>
> I have modified the entries:
>
>
Hi Jakub
As per the discussions, I have a created a bug report for the possible
regression this may cause.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82454
Sudi
From: Wilco Dijkstra
Sent: Tuesday, September 26, 2017 2:20 PM
To: Sudi Das; Jakub Jelinek
Cc: Richard Biener; GCC Patches; nd
a
Sent: Monday, October 9, 2017 2:02 PM
To: Richard Biener; Sudi Das
Cc: Jakub Jelinek; GCC Patches; nd; Richard Earnshaw; James Greenhalgh
Subject: Re: [PATCH][GCC] Simplification of 1U << (31 - x)
Richard Biener wrote:
> I think the patch is ok with these changes but obviously we
Hi all
This is a cleanup patch to remove the macro TARGET_EITHER. This macro seems to
have become irrelevant in recent times since its previous definition had been
commented out and replaced with 1.
Bootstrapped and tested on arm-none-linux-gnueabihf.
Sudi
2017-03-10 Sudakshina Das
Hi all
The backend pattern for combining a CMP+SHIFT was missing out on a case when
comparing with zero. This was happening because aarch64_select_cc_mode
(SELECT_CC_MODE) was not returning the correct mode (in this case CC_SWP) which
was needed to identify the combine. This patch adds this mis
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