Hi all
The backend pattern for combining a CMP+SHIFT was missing out on a case when
comparing with zero. This was happening because aarch64_select_cc_mode
(SELECT_CC_MODE) was not returning the correct mode (in this case CC_SWP) which
was needed to identify the combine. This patch adds this missing case.
For the test case :
int f3 (int x, int y)
{
int res = x << 3;
return res != 0;
}
We are now generating (at -O2)
f3:
cmp wzr, w0, lsl 3
cset w0, ne
ret
instead of :
f3:
lsl w0, w0, 3
cmp w0, 0
cset w0, ne
ret
Added this new test and checked for regressions on bootstrapped
aarch64-none-linux-gnu.
Ok for stage 1?
Thanks
Sudi
2017-03-10 Sudakshina Das <sudi....@arm.com>
* config/aarch64/aarch64.c (aarch64_select_cc_mode): Return CC_SWP for
comparision with zero.
2017-03-10 Sudakshina Das <sudi....@arm.com>
* gcc.target/aarch64/cmp_shifted_reg_1.c: New Test.diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 714bb79..01af2a7 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -4707,7 +4707,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
the comparison will have to be swapped when we emit the assembly
code. */
if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode)
- && (REG_P (y) || GET_CODE (y) == SUBREG)
+ && (REG_P (y) || GET_CODE (y) == SUBREG || y == const0_rtx)
&& (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
|| GET_CODE (x) == LSHIFTRT
|| GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND))
diff --git a/gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c b/gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c
new file mode 100644
index 0000000..cacecf4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 " } */
+
+int f3 (int x, int y)
+{
+ int res = x << 3;
+ return res != 0;
+}
+
+/* We should combine the shift and compare */
+/* { dg-final { scan-assembler "cmp\.*\twzr, w\[0-9\]+, lsl 3" } } */
