[PATCH v2 0/3] RISC-V: vectorised memory operations

lmul * add new unit tests to check that riscv-autovec-lmul is respected * PR target/112109 added to changelog for patch 1/3 as requested Sergei Lewis (3): RISC-V: movmem for RISCV with V extension RISC-V: setmem for RISCV with V extension RISC-V: cmpmem for RISCV with V extension gc

[PATCH v2 1/3] RISC-V: movmem for RISCV with V extension

gcc/ChangeLog * config/riscv/riscv.md (movmem): Use riscv_vector::expand_block_move, if and only if we know the entire operation can be performed using one vector load followed by one vector store gcc/testsuite/ChangeLog PR target/112109 * gcc.target/riscv/rvv/base/movmem-1.

[PATCH v2 3/3] RISC-V: cmpmem for RISCV with V extension

gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_vector::expand_vec_cmpmem): New function declaration. * config/riscv/riscv-string.cc (riscv_vector::expand_vec_cmpmem): New function; this generates an inline vectorised memory compare, if and only if we know the entire oper

[PATCH v2 2/3] RISC-V: setmem for RISCV with V extension

gcc/ChangeLog * config/riscv/riscv-protos.h (riscv_vector::expand_vec_setmem): New function declaration. * config/riscv/riscv-string.cc (riscv_vector::expand_vec_setmem): New function: this generates an inline vectorised memory set, if and only if we know the entire operation

Re: [PATCH v2 1/3] RISC-V: movmem for RISCV with V extension

Hi, this patchset has been tested with the following configurations: rv64gcv_zvl128b rv64gcv_zvl256b rv32imafd_zve32x1p0 rv32gc_zve64f_zvl128b Will fix the formatting in v3. Thanks On Wed, Dec 20, 2023 at 5:28 AM Jeff Law wrote: > > > On 12/19/23 02:53, Sergei Lewis wrote: > >

Re: [PATCH v2 2/3] RISC-V: setmem for RISCV with V extension

2023 at 5:38 AM Jeff Law wrote: > > > On 12/19/23 02:53, Sergei Lewis wrote: > > gcc/ChangeLog > > > > * config/riscv/riscv-protos.h (riscv_vector::expand_vec_setmem): > New function > > declaration. > > > > * config/risc

[PATCH 0/3] RISC-V: vectorised memory operations

imple cases we do have an unambiguous performance win without sacrificing too much code size compared to a libc call. Signed-off-by: Sergei Lewis --- Sergei Lewis (3): RISC-V: movmem for RISCV with V extension RISC-V: setmem for RISCV with V extension RISC-V: cmpmem for RISCV with V exte

[PATCH 2/3] RISC-V: setmem for RISCV with V extension

gcc/ChangeLog * config/riscv/riscv-protos.h (riscv_vector::expand_vec_setmem): New function declaration. * config/riscv/riscv-string.cc (riscv_vector::expand_vec_setmem): New function: this generates an inline vectorised memory set, if and only if we know the entire operation

[PATCH 1/3] RISC-V: movmem for RISCV with V extension

gcc/ChangeLog * config/riscv/riscv.md (movmem): Use riscv_vector::expand_block_move, if and only if we know the entire operation can be performed using one vector load followed by one vector store gcc/testsuite/ChangeLog * gcc.target/riscv/rvv/base/movmem-1.c: New test --- gcc/

[PATCH 3/3] RISC-V: cmpmem for RISCV with V extension

gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_vector::expand_vec_cmpmem): New function declaration. * config/riscv/riscv-string.cc (riscv_vector::expand_vec_cmpmem): New function; this generates an inline vectorised memory compare, if and only if we know the entire oper

Re: [PATCH 2/3] RISC-V: setmem for RISCV with V extension

The thinking here is that using the largest possible LMUL when we know the operation will fit in fewer registers potentially leaves performance on the table - indirectly, due to the unnecessarily increased register pressure, and also directly, depending on the implementation. On Mon, Dec 11, 2023

Re: Re: [PATCH 2/3] RISC-V: setmem for RISCV with V extension

more reasonable. > > -- > juzhe.zh...@rivai.ai > > > *From:* Sergei Lewis > *Date:* 2023-12-11 22:58 > *To:* juzhe.zh...@rivai.ai > *CC:* gcc-patches ; Robin Dapp > ; Kito.cheng ; jeffreyalaw > > *Subject:* Re: [PATCH 2/3] RISC-V: setme